JPH05206815A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit capable of compensating loss due to the base current of a transistor to constitute a current switching circuit in the current switching circuit using a differential circuit in the semiconductor integrated circuit. CONSTITUTION:NPN transistors 6, 7 are connected differentially, and each collector is connected to a current output terminal 2, 3. In the NPN transistors 8, 9, bases are connected respectively to control signal input terminals 4, 5, and emitters are connected to the NPN transistor 11 in common, and the collectors are connected to a power terminal 12 in common. The base and the collector of the NPN transistor 10 are connected to the common junction of the emitters of the NPN transistors 6, 7 together with the base of the NPN transistor 11. The emitters of the NPN transistors 10, 11 are connected to a current input terminal 1 in common.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a differential type current switching circuit composed of bipolar transistors.

[0002]

2. Description of the Related Art As a conventional semiconductor integrated circuit, a differential type current switching circuit as shown in FIG. 4 is known. Figure 4
, The terminal 1 is an input terminal, the terminals 2 and 3 are first and second output terminals, and the terminals 4 and 5 are first and second control signal input terminals, respectively. As shown in FIG. 4, the first NPN transistor 6 has a collector connected to the terminal 2, a base connected to the terminal 4, and an emitter shared with the emitter of the second NPN transistor 7 at the terminal 1.
It is connected to the. The second NPN transistor 7 has a collector connected to the terminal 3 and a base connected to the terminal 5.

Next, the operation of the conventional semiconductor integrated circuit shown in FIG. 4 configured as described above will be described. Terminal 4,
5, first and second control signals having opposite polarities are applied to each other, and these control signals are applied to the bases of the first NPN transistor 6 and the second NPN transistor 7 which are differentially connected. Is entered. A current I1 is supplied to the terminal 1 in a direction flowing out from the terminal 1. The currents I2 and I3 output from the terminals 2 and 3 to the outside are
Assuming that the potentials of the second control signals are ΔV and −ΔV, respectively, and the grounded-emitter current amplification factors (hereinafter referred to as hFE) of the first and second NPN transistors 6 and 7 are the same, the following formula 1 and formula It is represented by 2.

[0004]

## EQU1 ## I2 = (hFE / (hFE + 1)) × (I1 / 2) × {1 + tanh (ΔV / VT)}

[0005]

## EQU00002 ## I3 = (hFE / (hFE + 1)). Times. (I1 / 2) .times. {1-tanh (.DELTA.V / VT)}

VT in the equations 1 and 2 is VT = KT
/ Q. Here, K is Boltzmann's constant, T is absolute temperature, q is elementary charge, and VT at room temperature (27 ° C)
Is about 26 mV.

When ΔV, which is the potential of the first control signal, is set to be 5 to 10 times VT, tanh (10) ≈
Since tanh (5) ≈1, the value of the current I3 is almost 0 from the equation 2, and the value of the current I2 is almost (hFE / (h
FE + 1)) × I1. When the polarities of the potentials of the first and second control signals are reversed, that is, when the polarities of the control signals applied to the terminals 4 and 5 are reversed, the value of the current I2 becomes almost 0 and the current I3 The value is almost (hFE / (hFE +
1)) × I1. That is, when the amplitude of the control signal applied to the terminals 4 and 5 is 2ΔV (about 260 mV to 520 mV), and the potential of the terminal 4 is higher than the potential of the terminal 5,
The current input to terminal 1 is multiplied by hFE / (hFE + 1) and output from terminal 2. When the potential of terminal 5 is higher than the potential of terminal 4, the current input to terminal 1 is hFE / (hFE +
1) It is multiplied and output from the terminal 3.

Therefore, in the conventional semiconductor integrated circuit shown in FIG. 4, whether the current is applied to the terminal 2 or the terminal 3 according to the first and second control signals applied to the terminals 4 and 5. It operates as a current switching circuit for switching.

[0009]

However, in the conventional semiconductor integrated circuit described above, not all of the input current is output from the respective output terminals, but the amount of the base current of the transistor for switching the output. It is output only after receiving the loss. Therefore, this output current has a value obtained by multiplying the input current by a coefficient hFE / (hFE + 1) depending on hFE of the transistor. Therefore, the conventional semiconductor integrated circuit described above has a problem that the output current also fluctuates when hFE fluctuates due to variations in semiconductor manufacturing, and hFE itself has a temperature dependency. Therefore, there is a problem that the output current fluctuates in accordance with the temperature change, and therefore, it cannot be used especially in applications requiring high accuracy and high stability.

The present invention has been made in view of the above problems, and in a current switching circuit using a differential circuit in a semiconductor integrated circuit, it is possible to compensate for a loss due to a base current of a transistor forming the current switching circuit. An object of the present invention is to provide a semiconductor integrated circuit that can be manufactured.

[0011]

A semiconductor integrated circuit according to the present invention includes a differential switching circuit including a plurality of transistors whose emitters are commonly connected on one semiconductor substrate, and an emitter of the differential switching circuit. And a current mirror circuit which inputs a control signal from a common connection point of the current mirror circuit and which has an input current source as a ground point, and an output current of the current mirror circuit is used as an input current of the differential switching circuit. ..

[0012]

In the semiconductor integrated circuit according to the present invention, in the differential switching circuit in the semiconductor integrated circuit, in order to compensate the loss of the output current due to the base current of the plurality of transistors forming the differential switching circuit, The compensation circuit is provided with a current mirror circuit in which a control signal is input from the common connection point of the emitters of the switching circuit and the current input source is the ground point. This compensating circuit supplies a current having a value corresponding to the potential of the emitter of the differential switching circuit to the differential switching circuit, so that the influence of the hFE of the transistor on the output current of the semiconductor integrated circuit is extremely reduced. be able to.

[0013]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to the first embodiment of the present invention. Description of parts having the same reference numerals and functions as those of the conventional semiconductor integrated circuit shown in FIG. 4 will be omitted. The terminal 12 is a power supply terminal. In the third and fourth NPN transistors 8 and 9, the bases are respectively connected to the terminals 4 and 5, the emitters are commonly connected to the sixth NPN transistor 11, and the collectors are commonly connected to the terminal 12. The base and collector of the fifth NPN transistor 10 are connected to the base of the sixth NPN transistor 11 and the common connection point of the emitters of the first and second NPN transistors 6 and 7. The emitters of the fifth and sixth NPN transistors 10 and 11 are commonly connected to the terminal 1.

All the transistors used in the semiconductor integrated circuit according to the first embodiment are configured as an integrated circuit on one semiconductor substrate and have the same shape, so that their characteristics are almost the same. They are all aligned and can be regarded as the same. Therefore, hFE as a parameter can be regarded as the same for all the transistors.

Next, the operation of the semiconductor integrated circuit according to the first embodiment constructed as described above will be described. The current I1 supplied from the outside to the terminal 1 is the fifth and sixth N
It is equally distributed to the emitters of the PN transistors 10 and 11. As a result, the current I67 flowing through the common emitter connection point of the first and second NPN transistors 6 and 7 and the current I89 flowing through the common emitter connection point of the third and fourth NPN transistors 8 and 9 are as follows. Formula 3,
It is expressed by Equation 4.

[0017]

[Equation 3] I67 = ((hFE + 2) / (hFE + 1)) × (I1 / 2)

[0018]

[Equation 4] I89 = (hFE / (hFE + 1)) × (I1 / 2)

When the potentials of the first and second control signals applied to the terminals 4 and 5 are ΔV and −ΔV, respectively, the currents I2 and I3 output from the terminals 2 and 3 to the outside.
Is I67 shown in Expression 3 as I1 in Expression 1 and Expression 2
By replacing
It is represented by.

[0020]

## EQU5 ## I2 = {((hFE + 1) ² -1) / ((hFE + 1) ² +1)} × (I1 / 4) × {1 + tanh (ΔV / VT)}

[0021]

## EQU6 ## I3 = {((hFE + 1) ² -1) / ((hFE + 1) ² +1)} × (I1 / 4) × {1-tanh (ΔV / VT)}

Comparing equation 1 and equation 5, the coefficient hFE / (hFE + 1) in equation 1 is calculated as the coefficient {((hFE + 1) ^2-
1) / ((hFE + 1) ² +1)} × (1/2). Usually, hFE is about 100, so hFE /
(hFE + 1) ≈ 0.9910, so {((hFE + 1) ² -1) / ((hFE +
1) ² +1)} x (1/2) ≈ 0.9998. Therefore, although the output current of the conventional semiconductor integrated circuit receives a loss of about 0.9% of the output current due to the base current of the transistor, the output current of the semiconductor integrated circuit according to the first embodiment is Only about 0.02% of the output current is lost.

As a result, in the semiconductor integrated circuit according to the first embodiment, the loss of the output current caused by the finite value of hFE is reduced, so that the output current is affected by the variation of hFE due to the temperature change. Get smaller.

Third and fourth NPN transistors 8, 9
By equalizing the collector-emitter voltages of the fifth NPN transistor 10 and the sixth NPN transistor 11 to eliminate the influence of the Early voltage of the fifth and sixth NPN transistors 10 and 11, 6th NPN
This is a compensating transistor forming a current mirror circuit for making the hFEs of the transistors 10 and 11 substantially equal.

In Expression 5, since the coefficient 1/2 is added more than that in Expression 1, the output current becomes 1/2 of the input current, but the characteristics of the current switching circuit. However, since it is mainly required that the ratio of the input current and the output current is always constant, this attenuation of the output current is not a problem.

Next, a second embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to the second embodiment of the present invention. Description of parts having the same reference numerals and functions as those of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 1 will be omitted. The terminal 13 is a bias input terminal, and the third NP
It is connected to the base of the N-transistor 8. Further, the bias applied to the terminal 13 is such that the fifth NPN transistor 10 and the sixth NPN transistor 11 are in a state where either the first NPN transistor 6 or the second NPN transistor 7 is conducting. It is a bias for equalizing the collector-emitter voltage, and has a value equal to the high level potential of the control signal applied to the terminals 4 and 5.

With the above configuration, in the second embodiment, the number of Early voltage compensating transistors in the first embodiment can be reduced by one.

Next, a third embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to the third embodiment of the present invention. Descriptions of parts having the same reference numerals and functions as those of the semiconductor integrated circuits according to the first and second embodiments of the present invention shown in FIGS. 1 and 2 will be omitted. The terminal 14 is a third output terminal and the terminal 15 is a third control signal input terminal. Terminal 1
4 is connected to the collector of the seventh NPN transistor 16, and the terminal 15 is connected to the base of the seventh NPN transistor 16. The emitter of the seventh NPN transistor 16 is commonly connected to the emitters of the first and second NPN transistors 6 and 7. The terminals 4, 5 and 15 are control signal input terminals, and one of these terminals is set to a high potential and the other two terminals are set to the same low potential, so that the terminals 2, 3, 14 are Current can be output from one of the terminals. The potential difference between the high potential and the low potential applied to the terminals 4, 5, 15 may be set to about 260 mV to 520 mV as in the first and second embodiments.

As described above, in the semiconductor integrated circuit according to the third embodiment, the number of outputs that can be switched is easily increased by adding another transistor to the differential transistor used in the current switching circuit. be able to.

[0030]

As described above, according to the semiconductor integrated circuit of the present invention, in the current switching circuit using the differential circuit in the semiconductor integrated circuit, the loss due to the base current of the transistors forming the differential circuit is compensated. In addition, since the compensation circuit based on the current mirror circuit is provided, the influence of the transistor hFE on the output current can be made extremely small. As a result, the semiconductor integrated circuit according to the present invention can obtain an output current having high stability against variations in hFE and temperature fluctuations.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1, 2, 3, 4, 5, 12; Terminals 6, 7, 8, 9, 10, 11; NPN transistor

Claims (1)

[Claims] 1. A differential switching circuit composed of a plurality of transistors whose emitters are commonly connected on one semiconductor substrate, and a control signal is input from a common connection point of the emitters of the differential switching circuit and an input current is supplied. And a current mirror circuit having a source as a ground point, and an output current of the current mirror circuit is used as an input current of the differential switching circuit.