JP2686582B2 - Arbitrary waveform generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitrary waveform generator which sequentially calls a plurality of arbitrary waveform data stored in a memory and outputs a corresponding waveform signal.

[0002]

2. Description of the Related Art A conventional technique is disclosed in Japanese Patent Laid-Open No. 3-136178. An example of this is shown in FIG. The waveform memory 1 stores a plurality of types of waveform data. The sequence memory 10 stores information that determines the output order of waveforms. This information is information on a start address (first address) and an end address (last address) for each waveform. The address generator 30 supplies an address to the waveform memory 1 when calling data from the waveform memory 1. At this time, the address generator 30 uses the start address received from the sequence memory 10 as an initial value, and sequentially increases the address according to the clock. When the end address detecting means 40 detects that the address output from the address generator 30 reaches the end address, it generates a match signal. When this coincidence signal is generated, a new start address is loaded (reset) in the address generator 30. As a result, a new address is supplied to the waveform memory and a new waveform signal is generated.

[0003]

However, according to the above-described invention, since the coincidence signal is generated after the end address is detected and the start address of the new waveform data is reset in the address generator 30, the waveform output When the clock speed becomes high, the start address cannot be set at the proper timing. That is, there is a possibility that a delay may occur when switching the waveform.

5 and 6 show timing charts when the clock is low speed and high speed, respectively. Considering the time point indicated by the broken line 55 in FIG. 5, a match signal is generated because the address generator 30 has already output the end address, and when the clock rises at the time point indicated by the broken line 55, the address generator 30 is The starting address is loaded. However, considering the time point indicated by the broken line 65 in FIG. 6, there is a possibility that the match signal has not yet been established although the end address has already been generated in the address generator 30. In this case, even if the clock rises at the time of the broken line 65, the start address is not loaded in the address generator 30. Therefore, delay and instability occur in switching the waveform.

Therefore, an object of the present invention is to provide an arbitrary waveform generator capable of generating a waveform even at a high clock speed without causing a delay and an unstable state when switching a plurality of types of waveforms. Is.

[0006]

An arbitrary waveform generator of the present invention stores a plurality of defined waveform data in a waveform memory 1 and supplies an address to the waveform memory 1 to sequentially read the waveform data. In an arbitrary waveform generator for generating a waveform signal corresponding to data, a data address supply means (sequence memory) 10 for supplying a start address and output period data of one desired waveform data among a plurality of waveform data. , With the start address as the initial value,
Waveform memory 1 uses addresses that sequentially change according to the clock.
And an address generator 30 to be supplied to the counter and a counter means 60 for counting a predetermined number of holding clocks determined according to the output period data and generating an output signal. The output signal of the counter means allows the initial value of the address generator to be reset immediately after the output period of the waveform data determined according to the output period data has expired. In this way, the initial value of the address generator can be reset immediately after the expiration of the waveform data output period.
It is possible to stably switch the waveform.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an embodiment of the present invention. The waveform memory 1 stores a plurality of types of waveform data. The sequence memory 10 stores information that determines the output order of waveforms. This information is the start address and output period data for each waveform. These pieces of information are output when the sequence memory 10 receives the address from the control / arithmetic circuit 4. The control / arithmetic circuit 4 also generates a clock serving as a reference for operation. The address generator 30 generates an address to be supplied to the waveform memory 1 when reading the waveform data from the waveform memory 1. At this time, the address generator 30 uses the start address received from the sequence memory 10 as an initial value and increases the addresses to be sequentially output according to the clock. The waveform data output from the waveform memory becomes a waveform signal converted into an analog signal by the analog / digital converter 3. The output period data is output at the same time as the start address is output from the sequence memory 10. The counter 60 sequentially decreases the value of the counter in accordance with the clock with the output period data as an initial value. When the value of the counter 60 becomes "0", the flip-flop 70 latches the carry signal which is its output signal. Then flip-flop 7
In response to the output signal of 0, the start address of new waveform data is reset in the address generator 30, and the new waveform signal is output.

2 and 3 show timing charts when the clock in the present invention is low speed and high speed, respectively. The counter 60 is the sequence memory 10
Based on the output period data received from the address generator 30, the address generator 30 generates a carry signal at the same time as the value "0" at the clock immediately before the clock at which the end address is generated. Carry signal is flip-flop 7
When 0 is latched and the clock rises at the points of broken lines 25 and 35, the address generator 30 and the counter 60 are supplied with new start address and output period data, respectively.

According to the present invention, the generation of the end address can be known in advance by counting the output period data. Therefore, when a new start address is reset in the address generator 30, a delay and an unstable state may occur. Absent. In the embodiments shown in FIGS. 2 and 3, the counter value of the clock immediately before the end address is generated by the address generator 30 is set to "0". 'May be used. Also, '0'
Other than the above, for example, the carrier signal may be generated by "1". Furthermore, the initial value set in the counter is "0".
Alternatively, only the numerical value designated by the output period data may be counted.

According to the present invention, the end address is generated by counting the output period data, that is, the waveform data is generated.
Data output period has expired, the delay and error
New to the address generator 30 without causing a stable state
You can reset the starting address. In the embodiments shown in FIGS. 2 and 3, the counter value of the clock immediately before the end address is generated by the address generator 30 is set to "0". 'May be used. Also, for example, other than "0"
It may be generated a key Yari signal 1 '. Further, the initial value set in the counter may be set to “0” and only the numerical value designated by the output period data may be counted.

[Brief description of the drawings]

FIG. 1 is an embodiment of the arbitrary waveform generator of the present invention.

FIG. 2 is a timing chart when the clock is low in the arbitrary waveform generator of the present invention.

FIG. 3 is a timing chart when the clock is high speed in the arbitrary waveform generator of the present invention.

FIG. 4 is an example of a conventional arbitrary waveform generator.

FIG. 5 is a timing chart when the clock is low in the conventional arbitrary waveform generator.

FIG. 6 is a timing chart when the clock is high speed in the conventional arbitrary waveform generator.

[Explanation of symbols]

 1 Waveform Memory 10 Data / Address Supplying Means 30 Address Generator 60 Counter Means

Claims (1)

(57) [Claims] 1. An arbitrary waveform generator that stores a plurality of defined waveform data in a waveform memory, supplies an address to the waveform memory to sequentially read the waveform data, and generates a waveform signal corresponding to the waveform data. Data address supplying means for supplying a start address and output period data of one of the plurality of pieces of waveform data, and an address that sequentially changes according to a clock with the start address as an initial value in the waveform memory an address generator for supplying, and a counter means for generating a predetermined number by counting the clock output signal that is determined in accordance with the output period data comprises a by the output signal of said counter means, said output period de
After the output period of the above waveform data determined according to the data
Immediately arbitrary waveform generator according to claim <br/> it is possible resetting the initial value of the address generator.