JPS6231453A - Memory controller - Google Patents

Abstract

PURPOSE:To facilitate the easy conversion of a memory controller into an IC by reading out the written data in synchronization with a clock to write it to a memory circuit and supplying no write enable signal to the memory circuit during a section where a latching mistake is produced. CONSTITUTION:A waveform 9 showing the changing point of the write information is latched 4 by a multiplied clock 10 like the latches 2 and 3 for the input data 1 and a write address 8. Then a signal having a waveform 12 is drawn out and supplied to an AND gate 27 together with a write request signal 13. The gate 27 delivers a write enable signal having a waveform 14 and supplies it to a memory 15. Thus the write enable signal 14 is inhibited in a data unfixed area and no writing is carried out to the memory 15. While a read request signal 17 given from a read request generating circuit 25 is supplied to an address switch 19. The both the write and read addresses 11 and 18 are switched with each other and supplied to the memory 15. Thus the write/read control is carried out.

Description

[Detailed description of the invention] This invention relates to a device.

Conventional technology In conventional memory control devices, data is latched and written to the memory circuit using a clock signal that is phase-synchronized with input data as a write clock signal to the memory circuit, and is phase-synchronized with a certain reference signal. The configuration is such that data is read from the memory circuit using a read clock signal.

FIG. 3 is a configuration diagram of a conventional memory control device. The input data 1 is latched by the latch circuit 2 using the write clock signal 5 (frequency FW) which is phase-synchronized with the data 1. The output of the latch circuit 28 is the write/read address 1 of the address generation circuit 29 using the write clock signal 5 and the read clock signal 26 (frequency FR).
6 and a write enable signal 14 (normally a signal 1) are written to the memory circuit 16 and read from the memory circuit 15 as necessary. The read data is latched in the latch circuit 20 using the read clock signal 26 and output.

FIG. 4 shows an example of the write request generation circuit 24 that generates the write enable signal (WE) 16 of the conventional memory control device shown in FIG. 3, and FIG. 5 is a timing chart thereof. The write request generation circuit 24 includes a monomulti 30. resistance(
R)31. Capacitor (composed of q32, Rsl
, C32 is selected to be approximately equal to the minimum WE width of the memory circuit 16. Also, a write clock signal with a period T (human waveform in FIG. 5) is applied as an input signal to the monomulti 30, and from the falling edge of the waveform A, the width Tw
A write enable signal C (waveform C in FIG. 5) is output. Since the memory control device shown in FIG. 3 is configured to give priority to reading, it is necessary to inhibit the write enable signal C within the read cycle (width TR of waveform B in FIG. 6). Here, a read request signal B (waveform B in FIG. 6) is applied to the clear terminal of the monomulti 3o. That is, as shown in FIG. 5, within the read request signal width (TR) of waveform B, the write enable signal C is always at a high level.

By the way, like the pulse d written in the write enable signal C, by the time the width Tw obtained by monomultiple is reached,
When read request signal B is generated, the width is narrower than normal;
Since the write to memory is not completed, another write enable signal is required. Pulse e plays this role. A normal TTL monomulti IC (for example, 74LS123, etc.) uses a pulse f of a constant width from a waveform A as an input signal.
In addition to generating q, etc., at the rise of waveform B applied to the clear terminal, only when waveform A is low level, a certain width (Tw) from the rise of waveform B is generated.
outputs pulses e, h, etc.

That is, FIG. 4 is an example of effectively utilizing the characteristics of monomulti.

By the way, within the write clock period T shown in waveform A, - pulses a (width TR) indicating a read cycle and one write cycle width (Tw) must be generated. Depending on the phase of B, the pulse d
However, it is unclear which pulse e corresponds to the write cycle. Therefore, how much margin is required and the following relational expression must be satisfied?

T 〉2 TW + TR Assuming that the write cycle and read cycle widths are equal,
Usually, the following formula is used.

Write clock period T 〉 (memory access time) x 3 ... River (1
) Problems to be Solved by the Invention These conventional circuits require a monomulti-circuit to generate a write signal to the memory, and are unsuitable for IC implementation. In addition, when the frequency of the write clock signal becomes high when the memory control circuit is configured with read priority (high-speed search mode in a VTR, etc.), memory with short access time should be used to satisfy equation (1). I needed to use it. In other words, expensive memory had to be used.

In view of this point, it is an object of the present invention to provide a memory control device suitable for IC implementation.

Means for Solving the Problems The present invention provides a method for writing input data generated asynchronously to a read clock corresponding to a read cycle of data from a memory circuit into the memory circuit using gaps between the read cycles. provides two or more write cycles for each one, and supplies the input data and the write address corresponding to the input data to the re-circuit at a clock multiple of the read clock, and... 1. Supplying a write request signal corresponding to the write cycle to the memory circuit, and disabling the write request signal when the multiplied clock is a change point of the input data and the latched data becomes uncertain. This is a memory control device featuring the following features.

According to the above-described configuration, the present invention latches write data using a clock synchronized with a read clock and writes it into the memory circuit, and also prevents the write enable signal from being supplied to the memory circuit during a period in which a latch error occurs.

Embodiment FIG. 1 is a block diagram showing an embodiment of the memory control device of the present invention, and FIG. 2 is a time chart for explanation.

The input data 1 is latched by the latch circuit 2 using the multiplication clock 1o generated from the read clock 26 and written to the memory circuit 5, and the read data from the memory circuit 15 is latched by the read clock 26 in the latch 2o and output. It is output as data 21.

FIG. 2 shows an example of the waveform of each signal line in FIG. 1.

However, the waveform numbers in FIG. 2 and the signal line numbers in FIG. 1 match.

Write clock 5 (waveform 5 in FIG. 2) is applied to write address generation circuit 6, and write address 8 of waveform 8 is generated.At the same time, data change point extraction circuit 7 detects that the vicinity of the rising edge of write clock 5 is negative. A waveform 9 that becomes a sexual pulse is output.

On the other hand, according to the read clock 26, the read address generation circuit 22 outputs the read address 18 (waveform 18), the clock multiplier circuit 23 outputs the multiplier clock 10 (waveform 1o), and the write request generation circuit 24 outputs the read address 18 (waveform 18). Request signal B (waveform B) is output, and read request signal 17 (waveform 17) is output from read request generation circuit 26.

In this embodiment, the first half of one cycle of the read clock 26 is devoted to the write cycle, as shown in waveform 17, and the second half is devoted to the read cycle.

Assuming that the write and read accesses of the memory circuit 16 are equal, write operations can be performed twice in the write cycle (W) period. Therefore, as shown in waveform B, two pulses (write request signal) are generated in the write cycle (W).

In order to write input data 1 at a position defined by read clock 26 as shown above, input data 1 and
The write address 8 is latched by the latch 2 and the latch 3, respectively, using the multiple clock 10. When the write address 8 and input data 1 are latched by the multiplication clock 10 as shown in waveform 10, the rising edge of the multiplication clock 1o (a, b in the same waveform...
...e, f...) The waveform has a changing point. Tip 9: Information shown in waveform 8 W0...W4
As shown in the information (WO to W4) shown in waveform 11, a positional shift occurs. However, since the rising edge d of waveform 1o coincides with the changing point of waveform 8, the latched data does not confirm whether information W2 is information W3, and when a latch error occurs, it is completely meaningless. It becomes information.

In order to prevent writing such uncertain data, the present invention prohibits the following.

That is, in the same way as input data 1 and write address 8 are latched, waveform 9 indicating a change point of write information is latched by latch 4 using multiplication clock 10, and a signal having waveform 12 is derived. Waveform 12 is input to one side of AND gate 27, and one input is supplied with write request signal 13. The AND gate 27 outputs a write enable signal (WE) 14 as shown in the waveform 14, and the memory 16
supplied to In this manner, the write enable signal (WE) 14 is inhibited in the data transfer area to prevent writing to the memory 16.

Further, the read request signal 1 from the read request generation circuit 25
7 is supplied to the address switch (SW) 19, and the waveform 16
After the write address 11 and the read address 18 are switched as shown in FIG.

Effects of the Invention According to the present invention, assuming that the memory write and read access times are the same, the memory access time only needs to satisfy the following relational expression (2).

Read clock period T 〉(memory access time) x3 ・・・・・・・・・
・(2) What this formula means is the formula (1
), the memory access time is not affected by the write clock cycle T, and is very effective in devices such as VTRs where the write clock cycle changes during high-speed search.

In fact, in the embodiment, since the write information is latched with a double clock, it is possible to process even if the write clock period T is about %.

Furthermore, unlike the conventional example, analog circuits such as mono-multiple circuits are not used, so the configuration is suitable for logic ICs such as gate arrays.

Additionally, in general, in systems that process high-speed data, in order to reduce processing data cycles, input data is supplied to a serial-to-parallel converter, written to memory, and read data is supplied to a parallel-to-serial converter for output. Although this method is normally used, the present invention can be applied to such a configuration as well, and similar effects can be obtained.

In the description of the embodiment, write information is latched with a double clock, but it can also be realized with a higher clock, and in this case, data processing is possible even when the write clock is twice or more than the read clock.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the memory control device of the present invention, FIG. 2 is a timing chart for explaining FIG. 1, FIG. 3 is a block diagram of a conventional memory control device, and FIG. FIG. 3 is a circuit diagram of the main part, and FIG. 5 is a timing chart showing the operation of FIG. 4. 2 to 4...Latch, 6...Write address generation circuit, 7...Data change point extraction circuit,
15...Memory circuit, 2o...Latch, 22...Read address generation circuit, 23...
. . . Clock multiplier circuit, 24 . . . Write request generation circuit, 25 . . . Read request generation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
0 ward statement mQ de -ka phrase ke da =! Mi 3rd
Figure 4: Figure 4: Figure 5

Claims (1)

[Claims] When input data generated asynchronously with a read clock corresponding to a read cycle of data from the memory circuit is written to the memory circuit using the gap between the read cycles, each piece of input data requires two or more write cycles. and latches the input data and a write address corresponding to the input data at a clock multiple of the read clock and supplies the input data to the memory circuit, and supplies a write request signal corresponding to the write cycle to the memory circuit. . A memory control device, wherein the write request signal is inhibited when the multiplied clock is at a changing point of input data and the latched data becomes uncertain.