JPH0193845A - Microprocessor - Google Patents

Abstract

PURPOSE:To shorten an access time by dividing an address into the respective bits of a high order and a low order, a comparing the value of an address high order at a preceding address latch time and the value of the address high order in a present bus cycle and outputting the high order bit from the low order bit of an address bus interface in case of decidence. CONSTITUTION:An address generating part 12 coupled to a bus interface unit 15 is provided to a 16 bit microprocessor 11 and the high order 8 bits from the generating part 12 are stored in a 8 bit latch 13. At an address latch state time, the high order 8 bits in the latch 13 and the high order 8 bits of an address from the generating part 12 in the next bus cycle are compared with a decidence detecting circuit 4. Then, an address latch state is generated from a unit 15 with a decident output from the circuit when the both are different values and the address high order is outputted to an external output low order 1e or an external input and output data bus 1g.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to microprocessors. More particularly, the present invention relates to a novel configuration of a microprocessor, particularly an address bus interface section.

BACKGROUND OF THE INVENTION FIG. 2 is a diagram schematically showing the configuration of an interface with a memory in a conventional microprocessor.

21 is a microprocessor with a 16-bit address bus and an 8-bit data bus; 22 is an 8-bit human output latch; 2a is a data bus DO to 7; 2b is an address latch enable (hereinafter abbreviated as ALE) signal; 2C is address bus A8~15.2d is read signal (TU),
2e represents a write signal ("W lower"), and 2f represents address buses AO-7.

Figure 2A shows the timing of each signal when a read operation is performed on the memory in this figure.The lower 8 bits of the address are multiplexed with data and bus, and are the first state of the bus cycle. It is output onto the data bus at TI and held in an externally provided 8-bit latch by the address latch enable signal.

An address is given to the memory by the output of this latch and the upper 8 pins of the address, and during the period T2T3, IJ-
Data is retrieved from memory by activating the code signal.

In this way, conventional microprocessors use one bus
The lower part of the address is held in an external latch at the beginning of the cycle,
Since the data was retrieved from the memory in the next two states, three states were required to retrieve the data from the memory.

Problems to be Solved by the Invention In the conventional microprocessor described above, a state for latching the lower 8 bits of an address is always inserted at the beginning of a bus cycle such as when reading or writing to memory, so the access time to memory is shortened. It has the disadvantage that it takes a lot of time for a microprocessor where the address bus and data bus are separate.

Means for Solving the Problems According to the invention, an internal address of at least m bits wide
In a microprocessor equipped with a bus, the address is divided into upper X bits (x≦m/2) and lower m−x bits, and the lower m−x bits address bus Equipped with a bus interface to the outside including an X-bit latch signal output,
Furthermore, the upper X of the addresses output from the address generation section
The discrepancy detection circuit includes a latch that holds the value of a bit when an address latch cycle occurs, and a discrepancy detection circuit that compares the output of the latch with the value of the upper X via of the address output from the address generation section. An address launch state is generated by the address mismatch signal output from the detection circuit, and the lower m of the address bus interface is
A microprocessor is provided which is characterized in that it outputs upper X bits of an address from -x bits.

Further, as will be specifically described later, according to a preferred embodiment of the present invention, in a microprocessor equipped with an address bus and a data bus each having an address width of m bits and a data width of n bits, , top X
bit (x5m) and lower m−x bits, and address bus interface of lower m−x bits, and n
It has a bus interface to the outside that includes a data bus interface for bits and a launch signal output for the address of the upper X bits. It includes a latch that is held when a cycle occurs, and a mismatch detection circuit that compares the output of the latch with the value of the upper X bits of the address output from the address generation section, and is generated by an address mismatch signal output from the mismatch detection circuit. In the address launch state, the data has
Output the upper X bits of the address from the interface,
Furthermore, a microprocessor is provided which is characterized in that an address latch signal is output from an address upper X bit latch signal output.

The microprocessor of the present invention has a latch that holds the upper via of the address output from the address generation section, and a mismatch detection method that manually detects the output of the latch and the value of the upper bit of the address output from the address generation section. It has a circuit.

That is, in contrast to the conventional microprocessor described above, the microprocessor of the present invention stores data in the upper part of the address.
bus or the lower address bus, and compares the upper address value at the previous address latch with the upper address value at the current bus cycle, and only if they do not match, the address bus is It has an original feature of inserting an address latch state and outputting the upper part of the address than the lower part of the data bus or address bus.

The present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one embodiment of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 is a block diagram depicting the configuration of an embodiment of a 16-bit microprocessor according to the present invention, with particular attention paid to the bus interface section.

This microprocessor 11 has a bus interface unit 15 which is an interface to the outside.
The address generating section 12 is coupled to the address generating section 12 . Also,
The output of the address generator 12 is also input to an 8-bit latch 13 that latches the upper 8 bits of the address, and the output of this 8-bit latch 13 and the upper 8 bits of the output of the address generator 12 described above are combined. A mismatch detection circuit 14 is provided to compare and detect mismatch between the two. still,
Each signal line is as follows.

1a Near address bus AO~15. 1b Near address upper latch output, IC: Mismatch output, 1d: Data bus DO~7. 1e: external output address lower AO to 7.1f near address latch enable signal (hereinafter referred to as ALE), 1g = external output data bus DO to 7 The circuit configured as described above is as follows. It works like this.

In a certain address latch state, the high-order 8 bits of the address held in the 8-bit latch 13 and the high-order 8 bits of the address output from the address generator 12 in the next bus cycle are detected in the mismatch detection circuit 14. be compared.

Here, if both are the same value, the addresses manually input to the mismatch detection circuit 14 are the same value, and the mismatch output I
C is not output. Therefore, bus interface unit 15 does not generate an address latch state for latching the value of the upper eight bits of the address.

゛ On the other hand, the value held in the 8-bit latch 13 and
If the upper 8 bits of the address output from the address generation section 12 are different values, a mismatch output from the mismatch detection circuit 14 is output. Accordingly, the bus interface unit 15 generates an address latch state and outputs the address high order to the external output address low or external output data bus.

The interface between the microprocessor and the memory according to the present invention will be described below with reference to two specific configuration examples.

FIG. 3 is a diagram illustrating an example of the configuration of an interface section with a memory of a microprocessor in which the upper 8 bits of an address and a data bus are multiplexed.

31 is a microprocessor, 32 is a latch, 3a is a data bus DO to 7.3b is ALE, 3C is an address bus lower order AO to 7.3d is a read signal (TU), 3e is a write signal (WT), 3f is address bus upper A8
~15 respectively.

In the figure, the timing of each signal when a read operation is performed on the memory is shown in FIG. 3A.

As is clear from the figure, if the value of the upper 8 bits of the address does not change, the bus cycle ends in two states, T and T2.

That is, if the upper 8 bits of the address in the previous bus cycle are different from the upper 8 bits of the address in the current bus cycle, the address latch state (TAL) is inserted as described above with reference to FIG. . This TAL
The upper eight bits of the address that are output from the data bus are held by the latch 32. Thereafter, the T and T2 states are generated at the same timing as in a normal bus cycle, and a 16-bit address is given to the memory, thus allowing data to be taken out by a read signal.

Thus, in the micro processor according to the present invention,
An address latch state occurs only when the address value in the previous bus cycle and the address value in the current bus cycle differ for the upper eight bits of the address.

Furthermore, FIG. 4 shows a microprocessor in which the upper 8 bits of the address and the lower 8 bits of the address are multiplexed, especially the dynamic RAM (hereinafter referred to as DRAM).
FIG.

41 is a microprocessor with a 16-bit address bus (divided into upper 8 bits and lower 8 bits) and an 8-bit data bus; 42 is a DRAM with a word x 8-bit page mode in 64; and 43 is a two-man power AND gate (negative 4a is data bus DO~7.4b is AL
E, 4c is address bus AO~7.4d is read signal (TU), 4e is write signal (v'T), 4f is A
It represents the ND gate 43 output.

In this figure, the timing of each signal when a read/write operation is performed on the DRAM42 is shown in the fourth A.
As shown in the figure.

First, during address latch state (TAL),
The upper 1 address is output from AO to 7, and ALE is output at the first half clock of that state. ALE is D
Since it is connected to the RAM row address strobe ffFS'), the DRAMO row address is selected in synchronization with the rising edge of ALE. Next T, T,
In the state, the lower 1 of the address is output from AO~7, and when the read signal ff'U) falls, the output of the AND gate 43 falls, and the column address strobe falls, and the column address is selected and read from the memory. Data 1 is retrieved.

When performing a write operation within the same row address, the address latch state does not occur, so m remains activated, the lower 2 of the address is output to AO to 7, the write signal falls, and the AND date is The output also falls, the column address strobe and write enable ("W'T") are activated, and data 2 on the data bus becomes the upper 1 address and lower 2 address on the DRAM.
is written to the cell selected by .

As described in detail, according to the present invention, the high-order address is multiplexed with the data bus or the low-order address, and the high-order address in the previous bus cycle and the high-order address in the current bus cycle are By comparing the values and generating an address latch state only if they do not match, the bus cycle can be shorter than that of a conventional microprocessor in which the lower address and data buses are multiplexed. , which has the effect of improving the processing speed of the processor.

In addition, when connecting DRAM as memory, not only can it be connected with a simple circuit, but write operations are performed in page mode within the same row address, so
It has the effect of shortening memory and access time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. FIG. 2 is a diagram of an interface with a memory in a conventional microprocessor. FIG. 2A is a timing chart of a conventional microprocessor when reading memory. FIG. 3 is an interface diagram between the upper 8 bits of the address and the memory of the microprocessor in which the data bus is multiplexed. FIG. 3A is a timing chart at the time of memory read in a microprocessor in which the upper 8 bits of the address and the data bus are multiplexed. Figure 4 shows a microprocessor and DR in which the upper 8 bits of the address and the lower 8 bits of the address are multiplexed.
It is an interface diagram with AM. Figure 4A shows the upper 8 bits of the address and the lower 8 bits of the address.
2 is a timing chart of memory read/write operations of a microprocessor in which bits are multiplexed. [Main reference numbers] 11... Microprocessor, 12... Address generation unit, 13... 8-bit latch, 14... Mismatch detection circuit, 15... Bus interface unit, 1a...・
・Address bus AO~15, ■b... Address upper latch output, IC... Mismatch output, 1d... Data bus DO~7. 1e...External output address lower AO~7.1f...
Address latch enable signal, 1g...External output data bus DO~7.21...Microprocessor, 22...8-bit latch, 2a...Data bus DO~7. 2b...address latch enable signal, 2c...
... Address bus A8 to 15.2d ... Read signal (TU>, 2e... Write signal (WTi
”), 2f...Address bus AO~7. 31...Microprocessor 32...Latch, 3a...Data bus, 3b...ALE. 3c...Address bus lower AO~ 7.3d・・
・Read signal (TU), 3e...Write signal ("Wπ), 3f...Address bus lower A8~15.41...
Microprocessor, 42...DRAM. 43... 2-person AND gate, 4a... Data bus Do~7. 4b...ALE. 4c...Address bus AO~7. 4d... Read signal (TU), 4e... Write signal (1 signal), 4f... AND gate 43 output

Claims (1)

[Scope of Claim] In a microprocessor equipped with an internal address bus having a width of at least m bits, the address is divided into upper x bits (x≦m/2) and lower m-
x bits, and has a bus interface to the outside including an address bus interface for the lower m−x bits and a latch signal output for the upper x bits of the address, and furthermore, the upper x
A latch that holds the value of a bit when an address latch cycle occurs, and a mismatch detection circuit that compares the output of the latch and the value of the upper x bits of the address output from the address generation section, and the mismatch detection circuit The address mismatch signal output by the circuit generates an address latch state, and the address
A microprocessor characterized in that it outputs upper x bits of an address from lower m-x bits of a bus interface.