JPS61136320A - Timing pulse generating circuit of synchronizing type counter - Google Patents

Abstract

PURPOSE:To synchronize a processing system operated by a synchronizing type counter and a processing system operated by a clock signal generator, by starting the counting of the synchronizing type counter by the first clock generated by the clock signal generator. CONSTITUTION:A pulse generator PG is triggered by an input, sends out a pulse output of 'L' to a D type flip-flop FF and a reset terminal of a cock signal generator CO for a prescribed period, and sets an output of the D type flip-flop FF and an output of the clock signal generator CO to 'L' and 'H', respectively. A synchronizing type counter SC goes to a reset state by the output of the D type flip-flop FF. When the prescribed period elapses, the output of the pulse generator goes to 'H', the output of the clock signal generator CO falls and goes to 'L', and thereafter, a clock is outputted. By a rise of the first clock, the output of the D type flip-flop FF goes to 'H', and the synchronizing type counter SC starts a counting operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a timing pulse generation circuit for a synchronous counter.

(Prior Art) As a timing pulse generation circuit for a synchronous counter used, for example, as a memory address signal generation circuit, a configuration as shown in FIG. 5 is conventionally known.

In FIG. 5, 1 is the input terminal of the reference pulse, and (a) in FIG.
The reference pulse S1 of pulse generator PG1. When applied to PG2, from the pulse generation 11PCI, the reference pulse Sl becomes low level for a time period TI from time t1 when it changes from low level to high level as shown in FIG. A signal S2 as shown in (b) is output and supplied to the reset terminal R of the synchronous counter SC, and the reference pulse 81 described above is output from the pulse r generator PG2 from the low level state. From time t1 when the state changes to high level, Tl )τ2
A signal S3 as shown in FIG. 6(c) which remains at a low level for a time length r2 having the relationship: is output, and is supplied to the reset terminal R of the clock signal generator CO, Ru.

The clock signal generator CO described above generates a clock signal S4 as shown in FIG. 6(d) from time t2 when its reset terminal R changes from a low level state to a high level state. and convert it into a synchronous counter SC
The signal is supplied to the clock terminal T of the clock terminal T and the terminal 3 for transmitting a signal to the outside.

Therefore, the synchronous counter SC receives the reset terminal R of the synchronous counter from among the clock signal S4 output from the clock signal generation @CO after time t2 as described above.
Time t5 when a clock signal that changes from a low level state to a high level state appears for the first time after time t4 when the clock signal changes from a low level state to a high level state
The synchronous counter S starts counting the clock signal from
The count output from C is sent to output terminal 2.

(Problems to be Solved by the Invention) In the conventional example shown in FIG. 5, the reset terminal R of the synchronous counter SC changes from a low level state to a high level state from time t4. By keeping the clock signal S4 supplied to the clock terminal T of the synchronous counter SC from the previous time t2, the reset terminal R of the synchronous counter SC changes from a low level state to a high level state. Since clock signal counting is started from time t5 when the clock signal that changes from a low level state to a high level state appears for the first time after time t4, the clock signal S4 generated by clock signal generation @CO Within the
A clock signal S is sent to the external signal sending terminal 3 from time t2 before the synchronous counter SC starts counting.
4 is being sent out, there is a discrepancy between the operation of the clock signal S4 from the signal sending terminal 3 and the operation of the signal processing system including a memory that operates based on the address signal. However, improvements were required.

(Means for Solving the Problems) The present invention provides a method for connecting a D-type flip-flop with a load terminal or a reset terminal to a clock signal generator by applying a pulse having a timing related to the timing of a reference pulse. A means for resetting both;
means for supplying the output signal from the D-type flip-flop with the load terminal or reset terminal to the reset terminal or load terminal of the synchronous counter; The trigger terminal of the D-type flip-flop,
The present invention provides a timing pulse generation circuit for a synchronous counter, comprising means for supplying a clock terminal to a clock terminal of the synchronous counter.

(Example) Hereinafter, specific contents of a timing pulse generation circuit for a synchronous counter of the present invention will be described in detail with reference to the accompanying drawings.

1 to 3 show different embodiments of the timing pulse generation circuit of the synchronous counter of the present invention. In each figure, 1 is the reference pulse input terminal, and 2 is the counting output signal of the synchronous counter. Output terminal, 3 is a terminal for sending a signal to the outside, 4 is a high-level voltage supply terminal, 5 is a reset terminal or load terminal in a synchronous counter, S
C is a synchronous counter, FF is a D-type flip-flop with a load terminal or reset terminal, and CO is a clock signal generator. Also, in FIGS. 1 and 2.

PG is a pulse generator, and in the circuit arrangement shown in Figs. 1 and 2, a pulse is generated by the reference pulse S1 shown in Fig. 4 (a), which is supplied to the reference pulse input terminal 1. In the device PG, the reference pulse 3-1 becomes low level between time t1 and time t2 when it changes from low level to high level, as shown in FIG. 4(b). A signal S5 with a pulse width τ is generated.

Further, the circuit and arrangement shown in FIG. 3 have a reference pulse S1 supplied to its reference pulse input terminal 1.

This is an embodiment in which the signal has the same pulse width τ as the signal S5 shown in FIG. 4(b), and the circuit arrangement shown in FIG. 2nd rM
The pulse generator PG provided in the circuit arrangement shown in FIG. 3 is not provided, therefore, the reference pulse input terminal 1 in the circuit arrangement shown in FIG. The output signal S5 from the pulse generator-PG provided in the circuit arrangement shown in FIG. The explanation of its structure and operation is the same as the explanation of the structure and operation of the circuit arrangement shown in Figure 1, so the explanation thereof is as follows. Omitted.

Now, in the circuit arrangement of the embodiment shown in the first diagram, the signal S5 generated by the pulse generator PG is sent to the reset terminal of the D-type flip-flop FF with a load terminal or a reset terminal, and the reset terminal of the clock signal generator CO. It is supplied to terminal R.

The D-type flip-flop FF with a load terminal or reset terminal and the clock signal generator CO are shown in FIG.
While the signal S5 shown in b) is at a low level, it is in a reset state.

For the load terminal and data terminal of a D-type flip-flop FF with a load terminal or reset terminal, terminal 4 is used.
A high level voltage is applied to the trigger terminal T thereof, and the output signal S7 ((d) in FIG. 4) of the above-mentioned clock signal generator CO is supplied to the trigger terminal T thereof.

The output signal S7 of the clock signal generator CO mentioned above is also supplied to the clock terminal T of the synchronous counter SC. In addition, the output signal S6 of the D-type flip-flop FF with the load terminal or reset terminal described above (((
C)) is supplied to the reset terminal or load terminal 5 of the synchronous counter SC.

The timing pulse generation circuit of the synchronous counter shown in FIG.
Then, the pulse generator PG sends a signal S5 of pulse width τ from time t1 to time t2 to the reset terminal R of the D-type flip-flop FF with a load terminal or reset terminal and the reset terminal R of the clock signal generator @CO. The D-type flip-flop FF with a load terminal or reset terminal and the clock signal generator C are supplied from K.
O is in a reset state while the signal S5 is at a low level.

At time t2 when the signal S5 described above changes from a low level state to a high level state, the clock signal generator CO starts oscillating the clock signal.

Clock signal S generated by clock signal generator CO
7, a trigger pulse is applied to the trigger terminal R of the D-type flip-flop FF with a load terminal or a reset terminal (at the time t3 described above)
2), the D-type flip-flop FF with a load terminal or reset terminal is triggered by the rising edge of the clock signal S) at time t3 when it first changes from a low level state to a high level state after 2). At time t4, which is a moment later than t3, its output signal S
The state of No. 6 changes from a low level state to a high level state.

Therefore, the synchronous counter SC, which was reset by the low level state of the signal S6, is reset at the time t.
4, the counting operation of the number of output pulses of the clock signal generator CO is started.

That is, since the synchronous counter SC in the timing pulse generation circuit of the synchronous counter of the present invention starts counting from the first clock signal generated by the clock signal generator CO, the address signal output from the synchronous counter SC The operation of the signal processing system including the memory that operates based on the clock signal generation @CO
There will be no deviation between the clock signal output from the clock signal and the signal processing operation in the external signal processing system supplied via the signal sending terminal 3.

In the embodiment shown in FIG. 2, a pulse is generated at the load terminal of a D-type flip-flop FF with a load terminal or a reset terminal. It supplies an output signal S5 of 1 kPG, and also supplies a dog low level voltage to its data terminal via terminal 6, and further supplies its output signal to the synchronous counter SC from its Q bar terminal. The circuit arrangement is the same as that of the first embodiment shown in the above-mentioned figure except that

Since the circuit arrangement of the embodiment shown in the second diagram also performs the same operation as the circuit arrangement of the embodiment shown in the first diagram, the circuit arrangement shown in the second Wi also has a synchronous counter SC. The operation of a signal processing system including a memory that operates based on the address signal output from the clock signal generator CO, and the external circuit that is supplied with the clock signal output from the clock signal generator CO via the signal transmission terminal 3. There will be no discrepancy between the signal processing operation in the signal processing system.

(Effects of the Invention) As is clear from the detailed explanation above, the timing pulse generation circuit of the synchronous counter of the present invention is capable of generating a load by applying a pulse having a timing related to the timing of the reference pulse. means for resetting both the D-type flip-flop with a load terminal or reset terminal and the clock signal generator; means for supplying the output from the clock signal generator to the trigger terminal of the D-type flip-flop with the load terminal or reset terminal, and the clock terminal of the synchronous counter. Since this is a timing pulse generation circuit for a synchronous counter, this J! ! According to the timing pulse generation circuit of the synchronous counter of the present invention, the synchronous counter SC starts counting from the first glock signal generated by the clock signal generator CO, so the address output from the synchronous counter SC The operation of the signal processing system, which includes a memory that operates based on signals, and the clock signal generator CO
Therefore, there is no difference between the clock signal output from the clock signal and the signal processing operation in the external signal processing system supplied via the signal sending terminal 3, and the timing pulse of the synchronous counter of the present invention does not occur. According to the generating circuit.

The above-mentioned conventional problems are successfully solved.

[Brief explanation of the drawing]

Figures 1 to 31i! I is a block diagram of each embodiment of the timing pulse generation circuit of the synchronous counter of the present invention, FIGS. 4 and 6 are waveform diagrams for explanation, and FIG. 5 is a block diagram of a conventional example. PG, PGI, PG2...Pulse generator, CO...
Clock signal generator, SC...synchronous counter, F
F: D-type flip-flop with load terminal or reset terminal.

Claims (1)

[Claims] means for resetting both a D-type flip-flop with a load terminal or a reset terminal and a clock signal generator by applying a pulse having a timing related to the timing of the reference pulse, and the load terminal as described above; or a means for supplying an output signal from a D-type flip-flop with a reset terminal to a reset terminal or a load terminal of a synchronous counter; A timing pulse generation circuit for a synchronous counter, comprising means for supplying a pulse to a trigger terminal of the synchronous counter and a clock terminal of the synchronous counter.