JP2679224B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2679224B2
JP2679224B2 JP6243889A JP6243889A JP2679224B2 JP 2679224 B2 JP2679224 B2 JP 2679224B2 JP 6243889 A JP6243889 A JP 6243889A JP 6243889 A JP6243889 A JP 6243889A JP 2679224 B2 JP2679224 B2 JP 2679224B2
Authority
JP
Japan
Prior art keywords
sealing resin
die bonding
die bond
printing system
adhesive agent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6243889A
Other languages
Japanese (ja)
Other versions
JPH02241040A (en
Inventor
啓 黒田
立郎 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6243889A priority Critical patent/JP2679224B2/en
Publication of JPH02241040A publication Critical patent/JPH02241040A/en
Application granted granted Critical
Publication of JP2679224B2 publication Critical patent/JP2679224B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Abstract

PURPOSE:To prevent air bubbles from being confined in sealing resin, and increase reliability by a method wherein, after die bonding adhesive agent is arranged so as to occupy an area larger than an IC on a wiring substrate, and the outer periphery of the IC is buried in the die bonding agent to be bonded and fixed, the IC is sealed by printing system with sealing resin. CONSTITUTION:By printing system, die bonding adhesive agent is supplied to a part of a wiring substrate 12, so as to occupy an area larger than a semiconductor integrated circuit 14, and the periphery thereof is buried in the die bonding adhesive agent 13 to be fixed. Then the semiconductor integrated circuit 14 on the wiring substrate 12 is sealed by printing system with sealing resin 17. For example, by printing system, the die bonding adhesive agent 13 like insulative epoxy resin is supplied to a part of the wiring substrate 12 on which conductor wiring 11 is arranged; the IC 14 is arranged at the almost central part and mounted by applying a specified load. After the aluminum pad of the IC 14 and conductor wiring 11 are connected by conductor wires 16 such as gold and aluminum, the following are sealed by printing system with the sealing resin 17; the conductor wiring 11, the die bonding adhesive agent 13, the IC 14, and a part of the conductor wires 16.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体集積回路(以下ICと称す)を配線基板
上に直接マウントするいわゆるCOB(Chip On Board)工
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called COB (Chip On Board) method for directly mounting a semiconductor integrated circuit (hereinafter referred to as an IC) on a wiring board.

従来の技術 従来の半導体パッケージを配線基板(例えばエポキシ
基板,セラミック基板,ガラス基板等)上に実装する面
実装工法に代わって、高密度化,コストダウン等をめざ
したベアチップを直接マウントするCOB工法が量産化の
段階に入ってきた。この製造工程は第2図に示す如く、
導体配線1の施された配線基板2の所定の位置に例えば
エポキシ系のダイボンド接着剤3をディスペンサー,転
写方式等により供給し(第2図a)、上記ダイボンド接
着剤3に合わせてIC4を載置させ、接着固定する(第2
図b)。続いて上記IC4のパッド(図示せず)と上記導
体配線1を金,アルミ等の導体線5で接続し(第2図
c)、更に上記IC4,上記導体線5を例えばポッティン
グ,印刷方式等を用いてエポキシ系の封止樹脂6で封止
する(第2図d)。高密度実装のために上記導体配線1
は上記IC4の近傍まで配線されていることから上記導体
配線1に接触させないために上記ダイボンド接着剤3の
供給量は少なく上記IC4を接着固定しても上記ダイボン
ド接着剤3が上記IC4の端面全面にはみだすことはな
い。つまり上記IC4の裏面の一部には空洞が発生してい
ることになる。この上記IC4の裏面に空洞を持った状態
で大形基板でのCOB工法に敵した常圧充填であるポッテ
ィング,印刷方式で封止樹脂6を供給すると、上記封止
樹脂6は常圧供給であるため上記IC4の裏面の一部にで
きた空洞の中には充填されず気泡7が残ることになる。
更に上記IC4の厚みは通常400μm程度と厚いために、常
圧で上記封止樹脂6を上記IC4の上方から急速に供給す
ると上記IC4の近傍には上記封止樹脂6が完全には供給
されず、同じく上記気泡7が残存することになる。
Conventional technology A COB method that directly mounts a bare chip aiming at high density and cost reduction, instead of the surface mounting method that mounts a conventional semiconductor package on a wiring board (eg epoxy board, ceramic board, glass board, etc.) Has entered the stage of mass production. This manufacturing process is as shown in FIG.
For example, an epoxy-based die bond adhesive 3 is supplied to a predetermined position of the wiring board 2 on which the conductor wiring 1 is applied by a dispenser, a transfer method or the like (Fig. 2a), and the IC 4 is mounted in accordance with the die bond adhesive 3 described above. Place and bond and fix (second
Figure b). Then, the pad (not shown) of the IC4 and the conductor wiring 1 are connected by a conductor wire 5 of gold, aluminum or the like (Fig. 2c), and further, the IC4 and the conductor wire 5 are potted, printed, etc. Is used to seal with an epoxy-based sealing resin 6 (FIG. 2d). Conductor wiring 1 for high-density mounting
Since it is wired up to the vicinity of the IC4, it does not come into contact with the conductor wiring 1, so the amount of the die bond adhesive 3 supplied is small, and even if the IC4 is adhered and fixed, the die bond adhesive 3 is entirely on the end surface of the IC4. There is nothing to see. That is, a cavity is formed in a part of the back surface of the IC4. When the sealing resin 6 is supplied by the potting and printing method, which is the normal pressure filling that complies with the COB method on the large-sized substrate with the cavity on the back surface of the IC4, the sealing resin 6 is supplied at the normal pressure. Therefore, the air bubbles 7 remain without being filled in the cavity formed in a part of the back surface of the IC4.
Further, since the thickness of the above IC4 is usually as thick as about 400 μm, when the sealing resin 6 is rapidly supplied from above the IC4 under normal pressure, the sealing resin 6 is not completely supplied in the vicinity of the IC4. Similarly, the bubbles 7 remain.

発明が解決しようとする課題 一般的なICパッケージの場合、リードフレーム上に載
置固定されたICの裏面にダイボンド接着剤の無い空洞が
発生していても、封止方式が数10kg/cm2の圧力で封止樹
脂を充填するトランスファー成形法であるため、比較的
空洞中に封止樹脂が充填され、またICの厚みが厚くとも
同じく充填圧力が高いため封止樹脂に気泡が残ることは
ほとんどない。ところが上記のごとく封止樹脂6の充填
がポッティング,印刷方式のように常圧による方式であ
れば封止樹脂6中に気泡7の残存する確率は大である。
この封止樹脂6中に気泡7を残存させたままIC4の信頼
性試験である例えば121℃,2気圧中に配線基板2を放置
するプレッサークッカー試験にかけた状態を第3図を見
ながら説明する。封止樹脂6中の気泡7も圧力が2気圧
となり配線基板2を大気中に出すと2気圧の気体が封じ
込められた上記気泡7が急激に膨脹して極端にはIC4を
浮きあがらせ上記封止樹脂6を破壊し、導体線5を断線
させる状態が発生する。このような問題点を解決するた
めに、ダイボンド接着剤3の供給面積を広げ、上記IC4
の裏面に空洞ができないようにする方式としてディスペ
ンサー方式では先端の細いマルチノズルを用いるがマル
チノズルではノズル1本ずつの量コントロールが非常に
困難であることと供給量の再現性が問題であった。一方
転写方式では転写治具で引き上げる接着剤の量のばらつ
きが大きくまた厚みのばらつきも大きいものであった。
更に封止樹脂の供給においては、ポッティング方式,印
刷方式ともに供給速度を極端に落とせば気泡を内蔵する
確率は少なかったが量産性に欠けるものであった。
Problems to be Solved by the Invention In the case of a general IC package, even if there is a cavity without a die bond adhesive on the back surface of the IC mounted and fixed on the lead frame, the sealing method is several tens kg / cm 2 Since it is a transfer molding method in which the sealing resin is filled with the pressure of, the cavity is filled with the sealing resin, and even if the thickness of the IC is large, the filling pressure is also high, so that air bubbles do not remain in the sealing resin. rare. However, as described above, if the filling of the sealing resin 6 is a method of normal pressure such as potting and printing, the probability that the bubbles 7 remain in the sealing resin 6 is high.
A state of the reliability test of the IC 4 with the air bubbles 7 remaining in the sealing resin 6, for example, the presser cooker test in which the wiring board 2 is left at 121 ° C. and 2 atmospheric pressure will be described with reference to FIG. . The bubbles 7 in the encapsulation resin 6 also have a pressure of 2 atm, and when the wiring board 2 is exposed to the atmosphere, the bubbles 7 containing the gas at 2 atms expand rapidly and the IC 4 is extremely raised to the above-mentioned encapsulation. A state occurs in which the stop resin 6 is destroyed and the conductor wire 5 is broken. In order to solve such a problem, the supply area of the die bond adhesive 3 is expanded to
In the dispenser method, a multi-nozzle with a thin tip is used as a method for preventing the formation of cavities on the back surface of the nozzle. However, in the multi-nozzle, it was very difficult to control the amount of each nozzle and the reproducibility of the supply amount was a problem. . On the other hand, in the transfer method, the amount of the adhesive pulled up by the transfer jig varies widely and the thickness also varies greatly.
Further, in the supply of the sealing resin, the probability of incorporating air bubbles was low if the supply speed was extremely reduced in both the potting method and the printing method, but the mass productivity was poor.

課題を解決するための手段 そして上記問題点を解決する本発明の技術的手段は、
配線基板上にICより広い面積となるようにダイボンド接
着剤を設け、ICの外周部をこのダイボンド接着剤に埋設
して接着固定し、その後、印刷方式にてICを封止樹脂で
封止するものである。
Means for solving the problems And technical means of the present invention for solving the above problems,
Provide a die bond adhesive on the wiring board so that it has a larger area than the IC, embed the outer periphery of the IC in this die bond adhesive and fix it, and then seal the IC with a sealing resin by a printing method. It is a thing.

作用 このようにICの外周部をダイボンド接着剤が覆ってい
ることにより、ICの端面の急峻な段差が緩和され、封止
樹脂を印刷方式でIC上に供給した場合、気泡が封じ込め
られることがないことから製造歩留りを上げ、信頼性を
向上させることが可能である。
Action By covering the outer periphery of the IC with the die-bonding adhesive in this way, a steep step on the end face of the IC is mitigated, and when the sealing resin is applied onto the IC by printing, air bubbles may be trapped. Since it does not exist, it is possible to increase the manufacturing yield and improve the reliability.

実施例 以下本発明の実施例について図面を参照しながら説明
する。第1図は本発明の実施例によるCOB工法の製造プ
ロセスフローを示す。導体配線11の施された配線基板12
の一部に例えば絶縁性エポキシ樹脂のダイボンド接着剤
13を印刷方式にて供給する(第1図a)。この場合上記
ダイボンド接着剤13の印刷面積は載置するIC14の面積よ
りも大きくしている。例えばIC14が5×5mmであれば印
刷面積は5.5×5.5mmとした。これはIC14の四辺の端面の
一部を上記ダイボンド接着剤13で覆うためである。ちな
みに本実施例での印刷方式は200メッシュのステンレス
スクリーン版を用いており上記ダイボンド接着剤13の厚
みは35μmであった。また印刷方式は上記ダイボンド接
着剤13の印刷面積、厚みの制御が比較的容易であるた
め、上記導体配線11の近傍まで印刷することが可能であ
る。次に上記ダイボンド接着剤13のほぼ中央部に5x5x0.
4mmtのIC14を載置し、所定の荷重をかけマウントする
(第1図b)。この荷重により上記ダイボンド接着剤13
の一部が上記IC14の外周部15の一部に盛り上がり被覆す
る。上記ダイボンド接着剤13の印刷形状が上記IC14と相
似系でしかも大きいことから、上記IC14の四辺の上記外
周面15をほぼ均等に上記ダイボンド接着剤13を覆うこと
になる。このことから上記IC14の上記外周面15の急峻な
段差は上記ダイボンド接着剤13でテーパーが形成され緩
和される。ちなみに上記外周面15への上記ダイボンド接
着剤13の盛り上がりは上記IC14の底辺から0.2mm程度で
あった。また、上記ダイボンド接着剤13は均一な厚みに
印刷されているため、上記配線基板12と上記IC14の裏面
の間には空洞は生じない。続いて上記IC14のアルミパッ
ド(図示せず)と上記導体配線11を例えば金,アルミ等
の導体線16で接続する(第1図c)。最後に上記導体配
線11,ダイボンド接着剤13,IC14,導体線16の一部を封止
樹脂17で封止する(第1図d)。この場合の上記封止樹
脂17の供給方法は所定のパターンが形成された印刷用ス
クリーン、メタル等の印刷版18を用い、例えばウレタン
製のスキージで上記封止樹脂17を印刷塗布する。印刷す
ると上記封止樹脂17の厚みは上記印刷版18と上記配線基
板11の間隔A、上記印刷版18の厚み等で任意に設定が可
能である。ちなみに本実施例では上記印刷版18に厚み0.
2mmのメタルマスクを用い、上記間隔Aを0.5mmに設定し
た場合上記封止樹脂17の厚みは0.6mmであった。本実施
例では上記ダイボンド接着剤13には絶縁性エポキシ樹脂
を用いたが必要に応じて導電性であっても、また、印刷
方式で印刷が可能であればいずれの接着剤でもかまわな
い。更に上記ダイボンド接着剤13の印刷面積を上記IC14
より大きくしているが上記IC14をマウントして上記外周
面15を均等に覆うようにすれば上記ダイボンド接着剤13
の厚みを厚くして、印刷面積は上記IC14より小さくして
も構わない。
Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a manufacturing process flow of a COB method according to an embodiment of the present invention. Wiring board 12 with conductor wiring 11
Die bond adhesive of insulating epoxy resin
13 is supplied by a printing method (Fig. 1a). In this case, the printing area of the die bond adhesive 13 is larger than the area of the IC 14 to be placed. For example, if the IC 14 is 5 × 5 mm, the printing area is 5.5 × 5.5 mm. This is because a part of the four end faces of the IC 14 is covered with the die bond adhesive 13. By the way, in the printing method of this embodiment, a 200-mesh stainless screen plate was used, and the thickness of the die bond adhesive 13 was 35 μm. Further, in the printing method, since it is relatively easy to control the printing area and the thickness of the die bond adhesive 13, it is possible to print up to the vicinity of the conductor wiring 11. Next, 5x5x0 on the center of the die bond adhesive 13.
Place the IC14 of 4 mmt and mount it with a predetermined load (Fig. 1b). This load causes the die bond adhesive 13
Partially bulges and covers a part of the outer peripheral portion 15 of the IC 14. Since the printed shape of the die bond adhesive 13 is similar to the IC 14 and is large, the outer peripheral surfaces 15 on the four sides of the IC 14 are covered with the die bond adhesive 13 almost evenly. Therefore, the steep step on the outer peripheral surface 15 of the IC 14 is relaxed by forming a taper with the die bond adhesive 13. By the way, the protrusion of the die bond adhesive 13 on the outer peripheral surface 15 was about 0.2 mm from the bottom of the IC 14. Further, since the die bond adhesive 13 is printed with a uniform thickness, no cavity is formed between the wiring board 12 and the back surface of the IC 14. Subsequently, the aluminum pad (not shown) of the IC 14 and the conductor wiring 11 are connected by a conductor wire 16 of gold, aluminum or the like (FIG. 1c). Finally, the conductor wiring 11, the die bond adhesive 13, the IC 14, and part of the conductor wire 16 are sealed with a sealing resin 17 (FIG. 1d). In this case, the method of supplying the sealing resin 17 uses a printing screen 18 having a predetermined pattern, a printing plate 18 made of metal or the like, and the sealing resin 17 is applied by printing with a squeegee made of urethane, for example. When printed, the thickness of the sealing resin 17 can be arbitrarily set by the distance A between the printing plate 18 and the wiring board 11, the thickness of the printing plate 18, and the like. By the way, in this embodiment, the printing plate 18 has a thickness of 0.
When a metal mask of 2 mm was used and the interval A was set to 0.5 mm, the thickness of the sealing resin 17 was 0.6 mm. In this embodiment, an insulating epoxy resin is used for the die bond adhesive 13, but any adhesive may be used as long as it is electrically conductive and printing is possible by a printing method. Further, the printing area of the die bond adhesive 13 is set to the IC14
Although it is larger, if the IC 14 is mounted and the outer peripheral surface 15 is evenly covered, the die bond adhesive 13
The printed area may be smaller than the IC14 by increasing the thickness of the IC14.

発明の効果 本発明である印刷方式でダイボンド接着剤を供給する
ことにより配線基板とICの間に空間が生じず、また、IC
の外周面の一部も均等な高さまでダイボンド接着剤で覆
い、ICの段差を緩和した状態で、同じく印刷方式にて封
止樹脂で封止すればICの段差が緩和されていることか
ら、封止樹脂中に気胞が生じることがなく、半導体装置
として信頼性を向上させることが可能となる。更に封止
方式として印刷方式を用いることから量産性を向上させ
ることも可能である。
EFFECT OF THE INVENTION By supplying the die bond adhesive by the printing method of the present invention, no space is created between the wiring board and the IC, and the IC
Part of the outer peripheral surface of the IC is covered with a die-bonding adhesive to a uniform height, and the steps of the IC are alleviated if the steps of the IC are alleviated by encapsulating with an encapsulating resin in the same printing method. Air bubbles are not generated in the sealing resin, and the reliability of the semiconductor device can be improved. Further, since the printing method is used as the sealing method, it is possible to improve mass productivity.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(d)は本発明の製造フローを示す断面
図、第2図(a)〜(d)は従来の製造フローを示す断
面図、第3図は信頼性試験による従来工法のICの破壊状
態を示す断面図である。 13……ダイボンド接着剤、14……IC、15……端面、17…
…封止樹脂、18……印刷版。
1 (a) to 1 (d) are sectional views showing a manufacturing flow of the present invention, FIGS. 2 (a) to 2 (d) are sectional views showing a conventional manufacturing flow, and FIG. 3 is a conventional reliability test. It is sectional drawing which shows the destruction state of IC of a construction method. 13 ... die bond adhesive, 14 ... IC, 15 ... end face, 17 ...
… Encapsulating resin, 18 …… Printing plate.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】配線基板上の一部に印刷方式によりダイボ
ンド接着剤を半導体集積回路より広い面積となるように
供給する工程と、上記ダイボンド接着剤上に半導体集積
回路の外周部を埋設して固定する工程と、上記半導体集
積回路を配線基板上で印刷方式により封止樹脂で封止す
る工程よりなることを特徴とする半導体装置の製造方
法。
1. A step of supplying a die bond adhesive to a part of a wiring board so as to have a larger area than a semiconductor integrated circuit by a printing method, and embedding an outer peripheral portion of the semiconductor integrated circuit on the die bond adhesive. A method of manufacturing a semiconductor device, comprising a step of fixing and a step of sealing the semiconductor integrated circuit on a wiring board with a sealing resin by a printing method.
JP6243889A 1989-03-15 1989-03-15 Method for manufacturing semiconductor device Expired - Fee Related JP2679224B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6243889A JP2679224B2 (en) 1989-03-15 1989-03-15 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6243889A JP2679224B2 (en) 1989-03-15 1989-03-15 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02241040A JPH02241040A (en) 1990-09-25
JP2679224B2 true JP2679224B2 (en) 1997-11-19

Family

ID=13200203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6243889A Expired - Fee Related JP2679224B2 (en) 1989-03-15 1989-03-15 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2679224B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666350B2 (en) * 1991-10-24 1994-08-24 日本レック株式会社 Resin encapsulation method for electrical parts
JP5157098B2 (en) * 2006-07-19 2013-03-06 サンケン電気株式会社 Semiconductor device and manufacturing method thereof
JP2010239162A (en) * 2010-07-26 2010-10-21 Oki Semiconductor Co Ltd Semiconductor device and method of manufacturing the same
JP2014110282A (en) * 2012-11-30 2014-06-12 Toyota Motor Corp Bonding method using paste containing metal fine particle

Also Published As

Publication number Publication date
JPH02241040A (en) 1990-09-25

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