JP3041994B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3041994B2
JP3041994B2 JP3056244A JP5624491A JP3041994B2 JP 3041994 B2 JP3041994 B2 JP 3041994B2 JP 3056244 A JP3056244 A JP 3056244A JP 5624491 A JP5624491 A JP 5624491A JP 3041994 B2 JP3041994 B2 JP 3041994B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
base
chip
semiconductor
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3056244A
Other languages
Japanese (ja)
Other versions
JPH05136214A (en
Inventor
重光 渡辺
芳昭 森田
位 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsumi Electric Co Ltd
Original Assignee
Mitsumi Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsumi Electric Co Ltd filed Critical Mitsumi Electric Co Ltd
Priority to JP3056244A priority Critical patent/JP3041994B2/en
Publication of JPH05136214A publication Critical patent/JPH05136214A/en
Application granted granted Critical
Publication of JP3041994B2 publication Critical patent/JP3041994B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/01005—Boron [B]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、ＩＣカード等の半導体
装置に係り、詳細には、半導体装置を一層薄く、かつ効
率良く生産できる新規のものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IC card and, more particularly, to a novel semiconductor device capable of producing a thinner and more efficient semiconductor device.

【０００２】[0002]

【従来の技術】半導体チップを搭載した薄型の半導体装
置を製作する際に、半導体チップに電気的な接続を得る
方法として、従来は、ワイヤーボンディングやフリップ
チップボンディング等の方法が実施されている。2. Description of the Related Art When a thin semiconductor device on which a semiconductor chip is mounted is manufactured, a method such as wire bonding or flip chip bonding has been conventionally implemented as a method for obtaining electrical connection to the semiconductor chip.

【０００３】ワイヤーボンディング方法は、図９に示さ
れる如くに、基体１２上に半導体チップ１１を搭載し、
この半導体チップ１１上に形成されたチップ電極１４
（半導体チップ１１の接続用電極部）に、これとは別
に、基体１２上に外部取り出し電極１５を形成し、それ
らの電極１４及び１５間を電極取り出し用金ワイヤー１
３で接続するようにされる。In the wire bonding method, as shown in FIG. 9, a semiconductor chip 11 is mounted on a base 12,
Chip electrode 14 formed on this semiconductor chip 11
Separately, an external extraction electrode 15 is formed on the base 12 on the (connection electrode portion of the semiconductor chip 11), and the electrode extraction gold wire 1 is provided between the electrodes 14 and 15.
3 is connected.

【０００４】また、フリップチップボンディング方法
は、図１０に示される如くに、基体１２上にバンプ電極
１６を介して半導体チップ１１を搭載するようにされ
る。In the flip chip bonding method, as shown in FIG. 10, a semiconductor chip 11 is mounted on a base 12 via bump electrodes 16.

【０００５】[0005]

【発明が解決しようとする課題】ところが、上述の２つ
の従来例では、セラミック、ブリント板等の基体１２の
表面に半導体チップを搭載するため、基体１２と半導体
チップ１１の厚みに加え、前者では、ワイヤー１３のル
ープ高さによって薄型化が制限され、後者では、バンプ
電極１６の厚みも加えられて、それぞれその全体の厚み
が極めて大きくなるとともに、特に後者のフリップチッ
プボンディング方法によるバンプ電極のボンディングに
は、高い技術が要求される等の問題がある。However, in the above two prior arts, since the semiconductor chip is mounted on the surface of the base 12 such as a ceramic or a blind board, the thickness of the base 12 and the semiconductor chip 11 is increased. In addition, in the latter case, the thickness of the bump 13 is limited by the loop height of the wire 13, and the thickness of the bump electrode 16 is also added. Has problems such as the need for high technology.

【０００６】また、製作工程の途中のワイヤーボンディ
ングやバンプはんだ等の個別処理に手間と時間を要し、
品質のばらつきや歩留りが悪いといった改善すべき事柄
も残されている。In addition, individual processing such as wire bonding and bump soldering during the manufacturing process requires time and effort,
There are still issues to be improved, such as uneven quality and poor yield.

【０００７】このように、ＩＣカード等の極薄型の半導
体装置、特に、それを一層薄くかつ効率良く生産するに
は、現状の技術では対応しきれなくなっていた。As described above, the current technology has been unable to cope with an extremely thin semiconductor device such as an IC card, and in particular, to produce the thinner and more efficient semiconductor device.

【０００８】かかる点に鑑み本発明は、一層薄く、かつ
効率良く生産できるようにされた半導体装置を提供する
ことを目的とする。[0008] In view of the above, an object of the present invention is to provide a semiconductor device which is thinner and can be efficiently manufactured.

【０００９】[0009]

【課題を解決するための手段】上述の目的を達成すべ
く、本発明に係る半導体装置の製造方法は、外部取り出
し電極が形成された基体の表面とチップ電極が形成され
た半導体チップの表面とを略同一面になるように、基体
の厚み方向に沿って一つもしくは複数の半導体チップを
埋め込み、前記埋め込まれた状態で、前記基体の外部取
り出し電極及び半導体チップのチップ電極を除いてそれ
ぞれの表面上に選択的に絶縁膜を形成し、前記絶縁膜上
に前記基体の外部取り出し電極部と半導体チップのチッ
プ電極とを接続する導体パターンを形成する。また、好
ましく前記半導体チップと前記基体間に充填材を介在さ
せる。 In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention comprises a method of manufacturing a semiconductor device, comprising:
The surface of the substrate on which the electrode is formed and the tip electrode are formed
So that the surface of the semiconductor chip is substantially flush with the surface of the semiconductor chip.
One or more semiconductor chips along the thickness direction of
Embedded, and in the embedded state, the outside of the base is taken out.
Excluding the extraction electrode and the chip electrode of the semiconductor chip
Forming an insulating film selectively on each of the surfaces;
Then, the chip between the external extraction electrode portion of the base and the semiconductor chip
Forming a conductor pattern for connecting to the electrode. Also good
Preferably, a filler is interposed between the semiconductor chip and the base.
Let

【００１０】[0010]

【作用】本発明に係る半導体装置においては、基体の厚
み方向に沿って半導体チップが埋め込まれているため、
半導体チップ上に形成されるチップ電極と基体の表面と
を略面一とすることができ、従って、全体の厚みを半導
体チップの厚み分程度に薄くすることが可能となる。In the semiconductor device according to the present invention, since the semiconductor chip is embedded along the thickness direction of the base,
The chip electrodes formed on the semiconductor chip and the surface of the base can be made substantially flush, so that the entire thickness can be reduced to about the thickness of the semiconductor chip.

【００１１】また、導体配線パターン，電極及び絶縁膜
は、半導体技術で通常用いられる方法と同様に蒸着，Ｃ
ＶＤ，メッキ等によって基体及び半導体チップの上面に
付着させ、フォトリソグラフ技術によってパターンを形
成することで形成することができるので、品質のばらつ
きや歩留りが改善され、かつ生産効率も向上する。Further, the conductor wiring pattern, electrodes and insulating film are formed by vapor deposition, C
Since it can be formed by attaching it to the upper surface of the base and the semiconductor chip by VD, plating or the like and forming a pattern by photolithographic technology, variation in quality and yield are improved, and production efficiency is improved.

【００１２】[0012]

【実施例】以下、本発明の実施例を図面を参照しつつ説
明する。図１〜図８は、本発明に係る半導体装置の各実
施例を示し、それらの図において、対応する部分には共
通の符号を付して重複説明を省略する。Embodiments of the present invention will be described below with reference to the drawings. 1 to 8 show embodiments of a semiconductor device according to the present invention. In those drawings, corresponding parts are denoted by common reference numerals and redundant description is omitted.

【００１３】第１実施例：この例は、図１ａ及びｂに示
される如くに、基体２０の厚み方向に沿って設けられた
凹部２０ａに半導体チップ１１全体が埋め込まれてい
る。この半導体チップ１１は基体２０上に一つもしくは
複数個、目的とする用途の容量に応じて適数個埋め込ま
れる。First Embodiment: In this embodiment, as shown in FIGS. 1A and 1B, the entire semiconductor chip 11 is embedded in a concave portion 20a provided along the thickness direction of the base 20. One or a plurality of the semiconductor chips 11 are buried on the base 20 in an appropriate number according to the capacity of the intended use.

【００１４】また、前記半導体チップ１１上にチップ電
極１４が形成されるとともに、基体１２の表面の一端側
には所定数の外部取り出し電極１８が形成されている。
そして、各電極１４，１８を除く表面に絶縁膜１９が形
成されるとともに、各電極１４，１８間は、例えばフォ
トリソグラフ技術等の従来の半導体技術により、導体配
線パターン１７で接続されている。A chip electrode 14 is formed on the semiconductor chip 11, and a predetermined number of external extraction electrodes 18 are formed on one end of the surface of the base 12.
An insulating film 19 is formed on the surface excluding the electrodes 14 and 18, and the electrodes 14 and 18 are connected by a conductor wiring pattern 17 by a conventional semiconductor technology such as a photolithographic technology.

【００１５】このように構成された本実施例の半導体装
置にあっては、基体２０の厚み方向に沿って半導体チッ
プ１１が埋め込まれているため、半導体チップ１１上に
形成されたチップ電極１４と、基体２０の表面とを略面
一とすることができ、従って、全体の厚みを半導体チッ
プ１１の厚み分程度に薄くでき、実験によると１ｍｍの
極薄の基板とすることができた。In the semiconductor device of the present embodiment thus configured, the semiconductor chip 11 is buried along the thickness direction of the base 20, so that the chip electrode 14 formed on the semiconductor chip 11 The surface of the base 20 can be made substantially flush with the surface of the substrate 20, so that the overall thickness can be reduced to about the thickness of the semiconductor chip 11, and according to experiments, an extremely thin substrate of 1 mm could be obtained.

【００１６】また、導体配線パターン１７，電極１４，
１８及び絶縁膜１９は、半導体技術で通常用いられる方
法と同様に、蒸着，ＣＶＤ，メッキ等によって基体２０
及び半導体チップ１１の上面に付着させ、フォトリソグ
ラフ技術によってパターンを形成することで形成するこ
とができるので、品質のばらつきや歩留りが改善されか
つ生産効率も向上する。The conductor wiring pattern 17, electrode 14,
The base film 20 and the insulating film 19 are formed by vapor deposition, CVD, plating, or the like in the same manner as a method generally used in semiconductor technology.
In addition, since it can be formed by attaching it to the upper surface of the semiconductor chip 11 and forming a pattern by a photolithographic technique, quality variation and yield are improved, and production efficiency is improved.

【００１７】なお、基体２０は、半導体チップ１１の保
持固定、並びに保護、及び全体の剛性確保の役目も果た
す。The base 20 also functions to hold and fix the semiconductor chip 11, protect the semiconductor chip 11, and secure the overall rigidity.

【００１８】第２実施例：この例は、図２に示される如
くに、基板２１の上面に従来技術と同様に半導体チップ
１１をダイボンドし、半導体チップ１１のチップ電極１
４面と同じ高さとなるように充填材２２を適当な方法で
形成した後、絶縁膜１９，導体配線パターン１７，外部
取り出し電極１８を形成した構成となっている。Second Embodiment: In this embodiment, as shown in FIG. 2, a semiconductor chip 11 is die-bonded to an upper surface of a substrate 21 in the same manner as in the prior art, and a chip electrode 1 of the semiconductor chip 11 is formed.
After a filler 22 is formed by an appropriate method so as to have the same height as the four surfaces, an insulating film 19, a conductor wiring pattern 17, and an external extraction electrode 18 are formed.

【００１９】この例では、基板２１と充填材２２との複
合体が第１実施例の基体２０に相当することになり、上
述と同様な作用効果が得られる。In this example, the composite of the substrate 21 and the filler 22 corresponds to the base 20 of the first embodiment, and the same operation and effect as described above can be obtained.

【００２０】第３実施例：この例は、図３に示される如
くに、セラミックや樹脂の固体の基体２０に半導体チッ
プ１１を搭載するための凹部２０ａを設け、その凹部２
０ａに半導体チップ１１をダイボンデンドし、半導体チ
ップ１１と基体２０との隙間を埋めて半導体チップ１１
を保持し、かつ半導体チップ１１の電極１４の上面と基
体２０及び充填材２２の上面が面一となるようになした
後、絶縁膜１９，導体配線パターン１７，外部取り出し
電極１８を形成した構成となっている。Third Embodiment: In this embodiment, as shown in FIG. 3, a concave portion 20a for mounting the semiconductor chip 11 on a ceramic or resin solid base 20 is provided.
The semiconductor chip 11 is die-bonded to the semiconductor chip 11a to fill the gap between the semiconductor chip 11 and the base 20.
And the upper surface of the electrode 14 of the semiconductor chip 11 is made flush with the upper surfaces of the base 20 and the filler 22. Then, the insulating film 19, the conductor wiring pattern 17, and the external extraction electrode 18 are formed. It has become.

【００２１】この例でも、基板２１と充填材２２との複
合体が第１実施例の基体１２に相当することになり、上
述と同様な作用効果が得られる。Also in this example, the composite of the substrate 21 and the filler 22 corresponds to the base 12 of the first embodiment, and the same operation and effect as described above can be obtained.

【００２２】第４実施例：この例は、図４に示される如
くに、基体２０の半導体チップ１１を搭載する部分に基
体２０の厚み方向に貫通する孔２０ｂを穿設し、充填材
２２で半導体チップ１１を保持し、かつ半導体チップ１
１の電極１４の上面と基体２０及び充填材２２の上面が
面一となるようになした後、絶縁膜１９，導体配線パタ
ーン１７，外部取り出し電極１８を形成した構成となっ
ている。Fourth Embodiment: In this embodiment, as shown in FIG. 4, a hole 20b penetrating in a thickness direction of the base 20 is formed in a portion of the base 20 on which the semiconductor chip 11 is mounted, and a filler 22 is used. Holding the semiconductor chip 11 and the semiconductor chip 1
After the upper surface of the first electrode 14 is flush with the upper surfaces of the base 20 and the filler 22, the insulating film 19, the conductor wiring pattern 17, and the external extraction electrode 18 are formed.

【００２３】この例でも、基板２１と充填材２２との複
合体が第１実施例の基体１２に相当することになり、上
述と同様な作用効果が得られる。Also in this example, the composite of the substrate 21 and the filler 22 corresponds to the base 12 of the first embodiment, and the same operation and effect as described above can be obtained.

【００２４】第５実施例：この例は、図５に示される如
くに、上述の実施例１〜４によって提供される半導体装
置の保護、または械的強度を補強すべく、半導体装置の
外周に保護体２４を設けた構成となっている。なお、符
号２６は保護体２４と基体上面層との間に介装された絶
縁保護膜である。Fifth Embodiment: As shown in FIG. 5, this embodiment is applied to the outer periphery of a semiconductor device in order to protect the semiconductor device provided by the above-described first to fourth embodiments or to reinforce mechanical strength. The configuration is such that a protection body 24 is provided. Reference numeral 26 denotes an insulating protective film interposed between the protective body 24 and the upper surface layer of the base.

【００２５】第６実施例：この例は、図６及び図７に示
される如くに、半導体チップ１１の他に、例えば抵抗等
のそれ以外のチップ部品２３を同様な態様で搭載した構
成となっている。なお、符号２４はチップ部品２３の電
極である。Sixth Embodiment: In this embodiment, as shown in FIGS. 6 and 7, in addition to the semiconductor chip 11, other chip components 23 such as a resistor are mounted in a similar manner. ing. Reference numeral 24 denotes an electrode of the chip component 23.

【００２６】この第６実施例は、半導体チップ１１及
び、例えば抵抗等のそれ以外のチップ部品２３を、半導
体技術で通常用いられる方法と同様に、蒸着，ＣＶＤ，
メッキ等によって製造し、導体配線パターン１７，電極
１４，１８及び絶縁膜１９を、フォトリソグラフ技術に
よってパターンを形成することにより、半導体装置を得
られるので、画期的な技術を提供できるものとなる。In the sixth embodiment, the semiconductor chip 11 and other chip components 23 such as resistors are deposited, vapor-deposited, CVD-processed, and the like in the same manner as that usually used in semiconductor technology.
A semiconductor device can be obtained by forming the conductor wiring pattern 17, the electrodes 14, 18 and the insulating film 19 by photolithographic technology, by manufacturing by plating or the like, so that an epoch-making technology can be provided. .

【００２７】なお、以上の各実施例において、導体配線
パターン１７を形成するチップ電極１４面と基体２０の
上面、又は充填材１７の上面は完全に面一でなくともよ
く、配線電極用の導体膜を切れ目なく連続して付着でき
る程度の小さな段差や、うねりを持ってもよい。仮に、
段差等が配線電極用の導体膜を切れ目なく連続して付着
できない程大きい場合には導体配線パターン１７に段差
での不連続を生じさせないように、図９に示される如く
に、段差部にテーパー部２５を設けることによって半導
体チップ１１の電極１４面と基体２０の上面は必ずしも
面一でなくともよい。In each of the above embodiments, the surface of the chip electrode 14 forming the conductive wiring pattern 17 and the upper surface of the base 20 or the upper surface of the filler 17 may not be completely flush. The film may have a step or undulation that is small enough to allow the film to be continuously attached without breaks. what if,
If the step or the like is so large that the conductor film for the wiring electrode cannot be adhered continuously without a break, the stepped portion is tapered as shown in FIG. 9 so as to prevent discontinuity at the step in the conductor wiring pattern 17. By providing the part 25, the surface of the electrode 14 of the semiconductor chip 11 and the upper surface of the base 20 do not necessarily have to be flush.

【００２８】すなわち、本発明の目的とする全体の薄型
化の一手段として、半導体チップ１１を埋め込む点での
いろいろな最良の手段は、本発明の趣旨に包括されるも
のである。That is, as one means for reducing the overall thickness of the present invention, various best means for embedding the semiconductor chip 11 are included in the spirit of the present invention.

【００２９】[0029]

【考案の効果】以上の説明から明らかな如く、本発明に
係る半導体装置によれば、基体の厚み方向に沿って半導
体チップが埋め込まれた構造とされるため、半導体チッ
プ上に形成されるチップ電極と基体の表面とを略面一と
することができ、全体の厚みを半導体チップの厚み分程
度に薄くすることが可能となる。また、導体配線パター
ン，電極及び絶縁膜は、半導体技術等で通常用いられる
方法と同様に蒸着，ＣＶＤ，メッキ等によって、基体及
び半導体チップの上面に付着させ、フォトリソグラフ技
術によってパターンを形成することで形成することがで
きるので、品質のばらつきや歩留りを改善でき、かつ生
産効率を向上させることができる。As is apparent from the above description, the semiconductor device according to the present invention has a structure in which the semiconductor chip is embedded along the thickness direction of the base, so that the chip formed on the semiconductor chip is formed. The electrode and the surface of the base can be substantially flush with each other, and the overall thickness can be reduced to about the thickness of the semiconductor chip. The conductor wiring pattern, electrodes and insulating film are attached to the upper surface of the base and the semiconductor chip by vapor deposition, CVD, plating, etc. in the same manner as the method usually used in semiconductor technology and the like, and the pattern is formed by photolithographic technology. Therefore, quality variation and yield can be improved, and production efficiency can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係る半導体装置の第１実施例の平面
図、及び断面図。FIG. 1 is a plan view and a cross-sectional view of a first embodiment of a semiconductor device according to the present invention.

【図２】第２実施例の断面図。FIG. 2 is a sectional view of a second embodiment.

【図３】第３実施例の断面図。FIG. 3 is a sectional view of a third embodiment.

【図４】第４実施例の断面図。FIG. 4 is a sectional view of a fourth embodiment.

【図５】第５実施例の断面図。FIG. 5 is a sectional view of a fifth embodiment.

【図６】第６実施例の断面図。FIG. 6 is a sectional view of a sixth embodiment.

【図７】第７実施例の断面図。FIG. 7 is a sectional view of a seventh embodiment.

【図８】変形例の断面図。FIG. 8 is a sectional view of a modification.

【図９】従来の半導体装置の説明に供される図。FIG. 9 is a diagram provided for describing a conventional semiconductor device.

【図１０】他の従来の半導体装置の説明に供される図。FIG. 10 is a diagram which is used for describing another conventional semiconductor device.

フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 321 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60 321

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 外部取り出し電極が形成された基体の表
面とチップ電極が形成された半導体チップの表面とを略
同一面になるように、基体の厚み方向に沿って一つもし
くは複数の半導体チップを埋め込み、前記埋め込まれた
状態で、前記基体の外部取り出し電極及び半導体チップ
のチップ電極を除いてそれぞれの表面上に選択的に絶縁
膜を形成し、前記絶縁膜上に前記基体の外部取り出し電
極部と半導体チップのチップ電極とを接続する導体パタ
ーンを形成したことを特徴とする半導体装置の製造方
法。 1. A surface of a substrate on which an external extraction electrode is formed.
Surface and the surface of the semiconductor chip on which the chip electrodes are formed
If there is one along the thickness direction of the substrate,
Embedded in a plurality of semiconductor chips,
In the state, the external extraction electrode of the base and the semiconductor chip
Selectively insulated on each surface except for the tip electrode
Forming a film on the insulating film;
Conductor pattern for connecting the pole part and the chip electrode of the semiconductor chip
Of manufacturing a semiconductor device, characterized by forming a pattern.
Law. 【請求項２】 請求項１において、前記半導体チップと
前記基体間に充填材を介在させたことを特徴とする半導
体装置の製造方法。 2. The semiconductor device according to claim 1, wherein
A semiconductor wherein a filler is interposed between the substrates.
Manufacturing method of body device.
JP3056244A 1991-01-31 1991-01-31 Method for manufacturing semiconductor device Expired - Fee Related JP3041994B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3056244A JP3041994B2 (en) 1991-01-31 1991-01-31 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3056244A JP3041994B2 (en) 1991-01-31 1991-01-31 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05136214A JPH05136214A (en) 1993-06-01
JP3041994B2 true JP3041994B2 (en) 2000-05-15

Family

ID=13021680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3056244A Expired - Fee Related JP3041994B2 (en) 1991-01-31 1991-01-31 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3041994B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4561870B2 (en) 2008-05-14 2010-10-13 株式会社デンソー Electronic device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH05136214A (en) 1993-06-01

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