JP2674271B2 - N-series matching circuit for time division data - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an N-series coincidence circuit for time division data, and more particularly to an N-series coincidence protection circuit for protecting data during data transmission.

2. Description of the Related Art As shown in FIG. 2, a conventional N-series matching circuit inputs a time-division input signal to perform serial / parallel conversion.
Input the P conversion circuit 9 and the parallel input signal that is the output of the S / P conversion circuit 9, count up when the parallel input signal is "1", clear when the parallel input signal is "0", and the value is N ( When n is a positive integer, 1 counter 10 that outputs a control signal (m is a positive integer) is counted up when the parallel input signal is "0", and when the parallel input signal is "1". Cleared and the value is N
And 0 counters 11 that output a control signal when
Holds "1" when a control signal is input from the counter 10,
When the control signal is output from the 0 counter 11, “0” is held and output, and the number m of state holding circuits 12 and the number m of outputs of the state holding circuit are parallel / serial converted, and N consecutive match result signals are output. And a P / S conversion circuit 13 for outputting as.

However, in the conventional N-series coincidence circuit, when the number of time divisions m is large, there is a problem that only m sets of counters are required and the amount of hardware increases.

The present invention has been made to solve the above problems inherent in the prior art, and therefore the object of the present invention is to provide a novel N-type time-division data that enables a significant reduction in the amount of hardware. It is to provide a continuous coincidence circuit.

Means for Solving the Problems In order to achieve the above object, an N-sequence matching circuit for time-division data according to the present invention delays a time-division input signal by m bits and outputs an input signal before time division. And an AND circuit of the time-division input signal and the pre-time-division input signal, a NOR circuit of the time-division input signal and the pre-time-division input signal, an N consecutive coincidence state signal, and the output of the AND circuit and the NOR circuit. A selection circuit for selectively outputting the output signal of the NOR circuit when the output signal of the AND circuit is "1" when the continuous coincidence state signal is "0", and when the output signal of this selection circuit is "1""1" is added to the count input signal, and when the selection circuit output signal is "0", 0 is output as the count output signal, and when the count output signal is N, the state conversion signal is output. Count circuit that sets all count output signals to "0", and status An EX-OR circuit that changes the state of the N-series coincidence state signal by the conversion signal and outputs it as an N-series coincidence result signal, and a count value delay circuit that delays each bit of the count output signal by m bits to obtain an input signal for counting When,
A state delay circuit for obtaining a count input signal by delaying the N consecutive match result signals by m bits.

Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Referring to FIG. 1, reference numeral 1 is an input signal delay circuit, which delays a time-division input signal by m bits to obtain a pre-time-division input signal which is a signal one cycle before.

Reference numeral 2 is an AND circuit for the pre-time division input signal and the time division input signal, which outputs "1" when "1" is generated for two consecutive cycles.

Reference numeral 3 is a NOR circuit for pre-time-division input signals and time-division input signals, which outputs "1" when it is "0" for two consecutive cycles.

Reference numeral 4 denotes a selection circuit, which selects the output signal of the AND circuit 2 when the N consecutive coincidence state signal is "0",
It is monitored whether "1" continues, and whether the "0" continues by selecting the output signal of the NOR circuit 3 when the N-consecution coincidence state signal is "1".

Reference numeral 5 denotes an adder, which is incremented each time "1" is input from the selection circuit 4 and cleared when "0" is input, and is used to change the N-consecutive coincidence state when the result becomes N. Output a control signal.

Reference numeral 6 denotes an EX-OR circuit, which inverts the state when the signal from the adder (counter circuit) 5 is "1" and outputs N.
It is a continuous match result signal.

A state delay circuit 7 delays the N consecutive coincidence result signals by m bits to hold a value for one period.

A counter value delay circuit 8 holds the addition result for one cycle.

EFFECTS OF THE INVENTION As described above, according to the present invention, since time-division data is processed as it is in time-division, the effect of reducing the amount of internal hardware can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
The figure is a block diagram of the prior art. 1 ... Input signal delay circuit, 2 ... AND circuit, 3 ... NOR circuit, 4 ... Selection circuit, 5 ... Counter circuit, 6 ... EX-
OR circuit, 7 ... State delay circuit, 8 ... Counter value delay circuit, 9 ... S / P conversion circuit, 10 ... 1 counter, 11 ... 0
Counter, 12 ... State holding circuit, 13 ... P / S conversion circuit

Claims (1)

(57) [Claims] 1. An input for outputting a pre-time-division input signal, which is a time-division signal one cycle before, by delaying a time-division input signal consisting of m bits and having a value of "1" or "0" by m bits. A signal delay circuit, an AND circuit of the time division input signal and the pre-time division input signal, a NOR circuit of the time division input signal and the pre-time division input signal, and N consecutive time division input signals at the time of N coincidence. A match state signal, the output of the AND circuit and the output of the NOR circuit are input, and when the N consecutive match state signal is "0", the output signal of the AND circuit is selectively output, and the N consecutive match state signal is " A selection circuit that selectively outputs the output signal of the NOR circuit when 1 ", an output signal of the selection circuit, and a count input signal that is a binary value composed of L (L = ≧ log ₂ N) bits are input,
When the selection circuit output signal is "1", "1" is added to the count input signal, and when the selection circuit output signal is "0", "0" is output as the count output signal. A count circuit that outputs a state conversion signal (= "1") and a count output signal is all "0" when the binary value of the output signal becomes N, and the state of the N consecutive coincidence state signal by the state conversion signal. And an EX-OR circuit for outputting as N consecutive match result signal, a state delay circuit for obtaining N consecutive match state signal by delaying the N consecutive match result signal by m bits, and each bit of the count output signal And a count value delay circuit that obtains a count input signal by delaying by m bits.