SU754414A1 - Number -pulse multiplying device - Google Patents

Description

The invention relates to digital signal processing and computing and can be used to multiply

sat submitted unitary Ko ^e house in applications of statistical information processing and digital signal filtering.

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Known multiplying devices that contain the subtraction and summation circuits, to which the frequency pulse buses, the quad, the oscillator and the 15 control device are connected via the coincidence circuits, the outputs of which are connected to the control inputs of the quad, counter, trigger and AND, OR, counting input the first discharge of the counter through the OR circuit and the AND circuit is connected to the generator output and the first input of the summation circuit, the second discharge counter input of this counter is connected to the second output of the summation circuit, and the output through the trigger 25 the ger is connected to the control unit, the output of the subtraction circuit is connected directly to the control input of the summation circuit and through the OR circuit to the quad input [1]. thirty

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Known multiplying devices implement the multiplication procedure according to the expression

.. ^: (X + Y> - (X - Υ) ²

x ' ^γ --ΐ

perform heterogeneous operations on the input signals: summation, subtraction, squaring, division, therefore, are characterized by bulkiness. Such devices also have low speed, due to the work on two cycles.

In the first cycle, over the time interval of the interaction of signals, their characteristic is averaged in the second, after this time, the product is calculated in a quadrator. The presence of delay elements in the quad of the multiplying device also significantly reduces its potential speed.

The closest in technical essence to the proposed device contains a counter, the counting input of which is connected to the input bus through a delay element, and its outputs are bitwise connected via keys to the drive inputs, the control input of keys with

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It is single with the input bus, and the drive input is connected to the counting input of the register counter £ 2 ^.

The disadvantage of the device is its limited capabilities, since it can functionally perform the operation of multiplying only “Two identical ⁵ numbers by squaring the number of input pulses.

The device is also characterized by low performance, due to the presence of a delay element, which requires a double operation of the summation operation in the accumulator on the time interval of one input pulse.

The aim of the invention 15 is to expand the functionality of the device due to the multiplication of unequal.

The goal is achieved by the fact that the number-pulse multiplying device that has a counter, the first group of elements AND, the multiplier contains an adder, the second group of elements AND, a group of elements OR, the source of a logical unit, and the discharge outputs of the counter are connected to the first inputs of the elements .

And the first group, the second inputs of which are connected to the transfer output of the adder, and the first inputs of the elements AND the second group, the second inputs of which are connected to the output of the sum of the adder, the outputs of the elements And the first and second groups are connected to the first and second inputs of the elements OR of the output associated with the corresponding inputs of the drive, the first input of the first element And the second group is connected to the source of the logical unit, and the first and second inputs of the adder are the inputs of the device.

The drawing shows a diagram of a multiplying device. The multiplying device consists of the counter 1, the elements OR 2, the accumulator 3, the adder 4 and the input busbars 5 and 6, the first and the second. groups of elements And 7, 8. 45

The inputs of the adder 4, implemented, for example, in the form of a one-bit binary adder, are the inputs of the device and connected to the corresponding input buses 5 and 6, the first building of the output of the adder 4 is connected to the counting input of the counter 1 and the first control input of the keys 2, the second output is connected to the second control input keys. The first element And 8 is connected to the source of logical unit 9.

The multiplying device operates as follows.

In the initial state, the counter 1 and the drive 3 are set to zero and, for example, contain 000000 and 0000000, respectively.

The second pulses, representing the multipliers, arrive at the corresponding inputs of device 5 and 6 simultaneously.

With the arrival of the first pair of pulses with the potential "1" from the first output of the adder 4, the keys 2 are opened and the counter code is shifted by one digit to the input of the drive 3. Simultaneously, the indicated potential is "1" in the form of information. units through the first digit of the keys 2 is fed to the input of the first 'bit of the drive 3. As a result, the drive code 3 is changed to 0000001.

On the front of the potential drop "1" to "0", one is added to counter 1 and its state changes to 000001.

Upon receipt of the second pair of pulses at the input of the device with the potential "1" of the first output of the adder 4 as described above, the total code formed by the counter code 1 and the information unit on the first key category equal to 0000011 is added to the contents of the drive 3. As a result, the drive 3 will change its state to 0000100.

Upon receipt of subsequent pairs of pulses at the device input, the number of 'which will be equal to the smaller and multiplied numbers, counter 1 will register this number of received pulses in the form of a code, and drive 3 will be the square of the received number of pairs of pulses.

Upon receipt of each subsequent pulse to the input of the device, the number of which is equal to the absolute difference between the values of the multiplied numbers by the potential "1", the elements And 8 and will open from the second output of the adder 4. each time, the code of the number accumulated in counter 1 will be added to the contents of drive 3 each time.

. As a result, at the end of the number of interactions of input pulses in the counter-register 1 there will be the code of one of the factors (smaller in absolute value), and in drive 3, the code of the product of numbers represented by the input pulses.

For example, let the numbers multiply

5 and 8. Then the change in the state of the drive of the multiplying device will occur according to the binary code table.

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room input momentum X Υ condition register counter 1 ... - ... ι. The code entering the drive input Drive Status 0 0 0 000000 0000000 0000000 one one one 000001 0000001 0000001 2 one one 000010 0000011 0000100 3 one one 000011 0000101 0001001 four one one 000100 0000111 0010000 five one one 000101 0001001 0011001 6 0 one 000101 0000101 0011110 7 0 one 000101 0100101 0100011 eight 0 one 000101 0000101 0101000 9 0 . 0 000101 0000000 0101000

Considering that the response time of keys 2 is almost an order of magnitude shorter than the response time of the elements of the '30 1 / Implemented by 0 = or 1K = triggers trigger, the switch off of the keys 2 occurs faster than the state of the counter 1 changes, therefore the contention of elements in the proposed multiplier 35 are missing.

The efficiency of the device is also preserved when the pulse repetition rate changes in a wide range of frequencies that do not exceed the maximum-d. but valid for the specific type of elements used in the device.

Claims (1)

Claim 45 A number-pulse multiplying device containing a counter, the first group of elements is And, a multiplier, characterized in that, in order to expand the functional possibilities by multiplying unequal numbers, it contains an adder, the second a group of elements and, a group of elements OR, a source of a logical unit, the bit outputs of the counter are connected to the first inputs of elements AND of the first group, the second inputs of which are connected to the transfer output of the adder, and to the first inputs of elements AND of the second group, the second inputs of which are connected to the output the sum of the adder, the outputs of the elements of the first and second groups are connected to the first and second inputs of the elements OR of the group, the outputs of which are connected to the corresponding inputs of the drive, the first input of the first (-element AND the second group of ene to a source logic of unity, and the first and second inputs of the adder device is input.