SU433498A1 - MULTITITLE] 1'NOE DEVICE - Google Patents

Description

Isoretation refers to computing and can be used in measuring and computing devices to process frequency signals. Multiplier devices are known that solve the problem of obtaining the product of two pulse frequency signals. However, in these devices, the factors, presented in the frequency-pulse form, are processed separately, which leads to a distortion of the result of multiplication by changing the frequencies of the interceptors during their processing. In order to increase the accuracy and reliability of the result of multiplying two frequency-pulse sequences, a counting trigger trigger AND, OR is entered into the device; the | first digit of which is used by the OR through the OR circuit and AND is connected to the output of the generator and the first output of the summation circuit the counter is connected to the second output of the summation circuit, and the output through the trigger is connected to the control device. The output of the subtraction circuit is connected directly to the control input of the circuit AND of the summation circuit and through the OR circuit to the quad input. The drawing shows a diagram of the device. It consists of a summation circuit of I pulse frequency signals containing I / I 2 and 3 circuits, trigger 4, delay element 5 and Mi 6, subtracting circuits 7 pulse frequency signals containing AND 8, - II circuits, trigger 12, IM circuit 13; quad 14, consisting of counters 1o and I6j

trigger 17, circuits And 18. delay elements 19 and circuits And 20.

In addition, the device contains a counter 21, a trigger 22, circuits AND 23-25, Schemes MI 26 and 27. A clock pulse generator 2b and a control device 29. At the inputs 30 and 31, multipliers are received in the form of pulse sequences X Pt (t) and F 9 (t).

x

The device works as follows. The impulse signals of the multipliers through the MI 6, C-IU 3 and MI 26 circuit are fed to the input of the counter 21. When the multiplier pulses coincide, the signal from the And 2 scoop, which sets the trigger 4 to 0, appears, preliminarily sets the trigger I. The trigger closes the IZ, 8 and 9 circuits. At the same time, the signal from the trigger through the element behind the holder holds the unit in the second digit of counter 21, which corresponds to two pulses, and sets trigger 4 again to I. Thus, in counter 21 code (x + y).

At the same time, the input signals are fed to circuits AND 8 and 9. The operation of the subtraction circuit is to eliminate in the subtractive sequences coinciding and alternating pulses. If the pulses coincide, their passage is prohibited by the trigger 4. The pulse passed through the AND 8 circuit sets trigger 12 to the position in which the AND 10 circuit opens and the II II circuit closes. If the next pulse is in accordance with the output of the AND 8 circuit, then it will pass to the output through the S1I 13 circuit. When the next pulse appears at the output of the AND 9 circuit, it will set the trigger 12 to a position in which the AND II circuit will open and it will not pass to the output, thus eliminating alternating pulses. At the output of the MI 13 circuit, a pulse sequence (x - y) is formed. The output signal from the subtraction circuit is applied to the inhibitory input of the circuit AND 3, therefore in the counter 21 during the averaging time determined by the control unit, the code (x + y) - (x - y) is generated. For this same verse, a code (x - y) - I will be generated in counter 15. This happens only 498 in a blowing way.

The trigger 17 is preset to the position and closes the AND 18 switch. The first impulse

from the output, the MI circuit 27 sets the trigger 17 to position I and does not pass to the input of the counter 15, the trigger 17 is, as it were, the first discharge of the counter 15. All subsequent pulses enter the counter 15 into two pulses, as they arrive at the second bit d.

This ends the first cycle of operation of the device, during which the control device closes the AND 23 and 20 circuits.

When the averaging time elapses, neither the control device closes the AND 24 and 25 circuits and opens the AND 26, 27, 20 circuits, and the counter code 21 is reversed by a command from the control device. In the second cycle, the result of the conversion is generated in the quad counter 16.

Quad works as follows. In the counter 15 odd numbers (2 / 7-1) are formed, where

/ 7 - the number of pulses received per squares). The counter code 15 is transmitted through the circuits by signals from the delay elements IV, to counter 16, in which odd numbers are added. Since the trigger 17 is constantly in position I, for the first discharge of the counter 16 the pulse is directly input. The code 1 + 3 + 5 + ... + + (2 "- I) -l is formed in the counter.

The pulses C of the generator 28 through cxewQT And 23 of the IL11 circuit 26, 27 are fed to the counter 21 and 15. Through (x + y) - (x - y) the meter 21, the counter 21 overflows and sets the trigger 22 to the position I, which is through the control device; will set the circuit to its original state.

During this time, (x + y) - (x - y) pulses will be added to the quadrant and a code (2 (x + y) –I) will be generated in counter 15. Since the first cycle of the And 20 circuit is closed, the total code in the counter 16 will be defined by

 - / I + 2 (x + y) -lJ (x + y)

22

. (x + y)

the sum (x + y) of the first odd numbers;

S -G1 + 2 (xy) -17 (xy) J p- -

 2

2 (xy) - the sum (xy) of the first

odd numbers.

Thus, N | g (x + y) - (xy) 4 xy.

The result of the conversion is reduced from counter 16, starting with the third bit, which results in dividing the result by 4,

 INVENTOR

A multiplying device containing subtraction and summation circuits to which the pulse-frequency signal buses, a quad, a generator and a control device whose outputs are connected to quad-control inputs are connected via the matchpad circuits, in order to improve the multiplication accuracy of the frequency-pulse signals, A counter, a trigger and an AND, SHS circuit, a counter input of the first digit of the counter are entered through the OR circuit and AND circuit connected to the generator output and the first output of the summation circuit, the second count input The bit of this counter is connected to the second output of the summation circuit, and the output via a trigger is connected to the control device, the output of the subtraction circuit is connected directly to the control input of the circuit 1 and the circuit and via the OR circuit to the quad input.