SU1471315A1 - Bi-pulse signal receiver - Google Patents

Abstract

The invention relates to communication technology and can be used in data transmission equipment and in telegraph information transmission nodes. The purpose of the invention is to improve noise immunity when exposed to the total type of interference "crushing" and "dominance". The device contains a comparison unit 1, an input matching unit 2, an amplifier-limiter 3, a shift register 5, a frequency divider (DF) 6. In order to achieve the goal, an inverter 4, DF 7, RS-flip-flop 8, an element of OR-NOT 9 is entered. , 7 consists of binary counters and a majority block. The bi-pulse signal converted in nodes 2 and 3 is fed in direct and inverse views to the inputs of DC 6 and 7, where it is integrated. This ensures the stability of receiving parcels with strong edge crushing. The work of the shift register 5 and block 1 is based on the St. bi-pulse signal, which consists in the fact that if one modulator two modulo two apply the original bi-pulse signal, and the other signal, but delayed by the time of two bi-pulse pulses , then the output will receive a signal corresponding to the inverse of the original information. 1 hp f-ly, 3 ill.

Description

The invention relates to a communication technique and can be used in data transmission equipment and in information transmission units of telegraph units.

The purpose of the invention is to improve the noise immunity when exposed to the total form of crushing interference and dominance.

Fig. 1 shows a structural electrical circuit of the device proposed; Fig 2 is a frequency divider circuit; PhiZoZ - timing charts

The device contains .block 1, input matching unit 2, amplifier-limiter 3, inverter 4, shift register 5, dividers .6 and 7 frequencies, RS-flip-flop 8 and element ORINE 9. Dividers 6 and 7 frequencies consist of binary counters 10 and P and majority block 12,

The device works as follows.

A bi-pulse bi-pulse signal arriving at the input of the device passes an amplifier-limiter 3 through the input matching unit 2, the output of which produces a single-pole bi-pulse signal, which is fed to the control inputs of the frequency divider 7 and through the inverter 4 to the input of the divider 6. Due to this, the input information sequence directly and inversely controls the operation of two dividers 6 and 7, and when the operation of one frequency divider is allowed, the operation of the other is blocked and vice versa.

Consider the work of a separate frequency divider when submitting information to its input presented in a bi-pulse code

Reference clock frequency

,

It is sent to the C-code of the binary counter 10, to the V-input of which a bi-pulse input signal is applied, the zero level of which is valid for a specific frequency divider. The number of bits of a binary counter is 10. equal to three, which corresponds to the ratio of the manipulation channel in the channel to the frequency of the reference oscillator equal to 1/16 (the number of quantization of the elementary

links - 16).

at the initial moment of time, -.counts are not 10 and AND are in zero soy

ten

 five

-20 35

45

50 s-55

- -.

then nii. The presence of a logical unit during the first five cycles at the control input of the frequency divider blocks the operation of the binary counter 10, and consequently, the entire node. The appearance of a logical zero is gated by the reference frequency clock at the C input of the counter 10, which causes its first bit to be switched to one. The short-term occurrence of a logical unit at the control input does not affect the operation of the circuit, but the new zero appearance is again gated with a clock pulse through the C input of counter 10 and ensures the appearance of the unit on the second bit and zeroing of the first one. Further operation of the counter 10 corresponds to the function of the digital integrator, the state of the bits of which is determined by the sug-1march duration against the background of the interference of the actual value of the received parcel. The number of bits of the counter, 10 (p), is chosen in such a way that its overflow occurs when more than half of the sending time is detected, i.e. the presence of interference in the received signal does not affect the correct operation of the frequency divider, provided that the total duration in the interval of analysis of the current value of the parcel is at least half of its duration and not more than one and a half of its duration. The fact of the overflow of the counter 10 is detected by the counter 11, which is reset to its initial state upon completion of the parcel, when the presence of logical units on the first and second inputs of the majority block 12 causes the unit to appear at its output and the counter 11. integration) is provided by the R input of the counter 10.

If, in the proposed device, the information signal acts on the frequency divider at the installation input, then in the known one - at the control input. The presence of sufficiently intensive crushing in the sum with the distortions of the type of prevalence can lead to the fact that the divisor simply does not have enough of the net interval of the received one to register it. At the same time, the integrator needs only a total compliance of the adopted one with the established criterion (in

314

In the nominal case, the fact of receiving a parcel means that more than half of it is received. From this it follows that the frequency dividers 6 and 7 of the device function in such a way that the appearance of one pulse at their outputs means that the corresponding parcel has been registered.

Fig. 3 shows the initial information at the transmitter input (not shown) of the following form: ... 10010 .. FIG. 8 shows a bi-pulse signal at the output of the transmitter corresponding to the initial information, and in Fig. 3, the same signal after passing through the channel. transmissions and necessary level conversions, i.e. output amplifier limit 3.

As can be seen from FIG. III, the original signal was subjected to the combined effect of distortions of the type of crushing and predominance, which led to the most dangerous situation for the known device. The signal, shown in FIG. 3c, passed through the inverter 4, goes to the control The input of the frequency divider 6, which, due to the presence of the inverter 4 at the input, works as the true unit level of the package. The presence of crushing in the received signal leads to an offset to the right of the output pulse of the divider 6 (Fig. 3g), since the overflow of the counter 10 occurs somewhat later. The appearance of the zero level at the control input of the divider 6 ensures the reset of counter 11 and, accordingly, the zero appearance at the output of the divider 6. Similarly, the appearance of the second premise is fulfilled, when the presence of even more intense interference leads to a three-quarter offset of the output divider. the duration of the parcel. Since the next premise is also single, the setting of the output counter does not occur, and the cut of the output pulse is also shifted. This leads to an offset and the next impulse.

which disappears when the level of the information signal changes, i.e. when the parcel is zero.

Similarly, the divider 6 fulfills the appearance of the following single parcels, and the divisor 7 processes the zero parcels, which form the output and the lines strobe each parcel (FIG. 10). You seem to be

five

0 t

3

5 0 5

five

0

0

15

the output pulse at the output of the divider 6 ensures the reset of the divider 7, and vice versa, the pulse at the output of the divider 7 resets the divider 6. By switching on the dividers, their mutual signal synchronization is reached, when the boundary of the sending of one, for example, unit level determines the beginning of the sending of another zero

level g

The signals from the outputs of dividers 6 and 7 are fed to the inputs of the element OR-NOT 9, the output of which is the form signal (), which is a clock signal: .1 of the shift register 5. The D-input of the shift register receives a signal From the trigger of RS-flip-flop 8, which is a restored one, i.e. interference free transmitter output. In this case there may be inconsistencies in the duration of the original and recovered parcels, which is caused by the fact that integrators do not eliminate distortions of the predominant type parcels, however, the reconstructed parcels are free from crushing, and this makes it possible to confidently gate them formed at the output of element 2 9 tact1-; and.

The operation of the shift register 5 and block 1 is similar to the operation of the corresponding blocks of the known device and is based on the bi-impulse signal properties, which consists in the following: if one modulator arm is modulator, then two give the original bi-pulse signal, and the other the same signal, but delayed by the time of following two bi-pulse packages, then a signal corresponding to the inverse of the initial information will be received at the output of the adder. In this connection, block 1 can be executed as an EXCLUSIVE OR element with an inverter at the output, and the shift register 5 is a normal sequential shift register, the first and third ratios of which {its discharge) are its most important outputs. The timing diagrams of the first, second, and third bits of the shift register 5 correspond to the diagrams shown in FIG. 3, and on the output of the device, to the diagram on

fig.Zk

Claims (2)

1. A device for receiving bi-pulse signals containing input co5. 14 a read unit, a limiting amplifier, a first frequency divider, a shift register, the outputs of which are connected to the first and second inputs of a comparator unit, characterized in that, in order to improve noise immunity under the influence of the aggregate type of crushing interference and dominance, an inverter is introduced; frequency divider, RS-trigger and the element OR-NOT, the output of which is connected to the clock input of the shift register, the information input of which is connected to the output of the RS-trigger, the R-input of which is connected to the code of the second frequency divider, the input input of the OR-NOT element and the installation input of the first frequency divider, the output of which is connected to the S input of the RS flip-flop, the second input of the OR-NOT element, and the installation input of the second frequency divider, the clock input of which is combined with the clock input of the first frequency divider and is the clock input of the device, the output of the input matching unit is connected to the input usi56 limiter, the output of which is connected to the control input of the second frequency divider and through the inverter to the control code of the first frequency divider. 2. The device according to claim 1, characterized in that the first and The second frequency dividers contain the first and second binary counters and the majority block, the output of which is connected to the R input of the second binary counter, the output of which is the output of the frequency divider and connected to the first input of the majority block, the second input of which is connected to the initial setting bus, C -input of the second binary counter connected to the output of the first binary counter, the V input of which is the control input of the first frequency divider and connected to the third input of the majority unit, the R input of the first the binary counter is the setup input of the frequency divider, and the C input is the clock input. V -