SU898505A1 - Information shifting device - Google Patents

Description

(54) DEVICE FOR SHIFT INFORMATION

Claims (2)

The invention otnh: eks to the number of techniques and can be used in the shapers commands of computing systems, pulse selectors and other similar schemes of pulse and computing equipment. A device for shifting information is known, based on the schemes of shift registers. The required number of bits of the shift register is determined by three constant clock frequency, the required delay time, ft. The drawback of the device is large hardware costs, if necessary; receive a delay for a large number of clock periods. Reducing the amount of equipment can be obtained by building a device for shifting information on the basis of the counter. The closest to the proposed technical entity is a device for shifting information, which consists of a series of bits connected in series through informative inputs and outputs, each of which contains a series-connected memory cell, an AND element and a counter, the output of which is connected to a reset input memory cells of this bit and, information. the input (platoon input of the memory cell) of the next bit, the second inputs of the elements AND of all bits are connected to the output of the clock generator. When a pulse of delayed memory pulse arrives at the information input, it goes to the state where the errvian potential arrives from the output of the memory cell to the input of the element I. At the same time, the clock pulses from the generator pass through the AND element to the input of the counter operating in the usual counting mode. After counting a given number of pulses equal to the counter capacity, the counting signal of a given number, coming from the counter output to the second input of the memory cell, resets the memory cell to the state that prohibits the passage of clock pulses through the AND element, and simultaneously opens whose memory of the next bit Yes. This time the row begins to work, the rotor is the sequence of operations described for the previous bit. The total time of the information shift in the known device is equal to the sum of the shift times of all the bits, and the time of the shift of the discharge is equal to the product of the repetition period of the clock pulses by the narrowness of the bit 2. The disadvantage of the known device is the loss of information about the duration of the input pulse occurring the reason that the memory cell is triggered by the front of the input pulse and does not respond to its duration. The purpose of the invention is to increase the reliability of the device. The goal is achieved by haem, that in a device for shifting information, containing a clock pulse generator, a memory cell, each of which consists of a storage element, an element AND, and a lock, the output of which is connected to the first input of the memory element, the output of the memory element of the pbdk luchen to the first input element And, the output of which is connected to the input. the counter, the second input of the element I is connected to the output of the clock pulse generator; a reversible counter is entered; a decoder, an RS trigger and an element NOT whose input is connected to the first input of the device and to the input of the reversing counter; the second input of the rev counter has been connected to the generator output. pulses, the output of the reversible counter is connected to the input of the decoder, the output of which is connected to the first input of the HS trigger, the second input of the PS trigger is connected to the output of the counter of the first memory cell, the third inputs of the reversible counter and RS griggers are connected to the input of a subsequent memory location. The drawing shows a functional diagram of the proposed device. The circuit contains a generator of I clock pulses, a reversible counter 2, memory cells 3 (only the first memory cell consisting of a storage element, 4, element 5 and counter 6 is shown in the drawing), an RS flip-flop 7, a cipher 8 and element NOT 9 The device operates as follows. A positive pulse arriving at the input (ix1) of the first cell 3 enables the direct counting of the clock pulses of the generator I to counter 2 and, having passed the HE element 9, switches element 4 to a state where the clock pulses are allowed to pass from the generator I to the counting the input of counter 6 through element 5, counter 2 counts in the forward direction only within the duration of the input pulse, with the end of the input pulse, the permit potential from the control input (input 2) is directly counted and counter 2 is decelerated. After counting a predetermined number of pulses of counters 6, its output signal converts element 4 to a state, requesting the passage of pulses of a clock frequency of generator I through element 5, and simultaneously sets the 1 5 trigger to the state of a logical unit. In this case, a trigger potential is applied from the trigger output to the countdown control input of the reversible counter 2. Reversible counter 2 counts in the reverse direction the number of pulses recorded in it when the input pulse of the bits is applied at the beginning of the operating cycle. The zero state of the reversible counter 2 is registered by the decoder 8, the output of which causes the 1 5 trigger 7 to the logical zero state. Cell 3 of the memory comes to its original state and is ready to receive the next input pulse. A positive polarity impulse comes from the output of 1 5-trigger 7 to the input of the memory stick, allowing the direct count to reversing counter 2 and transferring element 4 to the state allowing the passage of pulses of the ator I to the counting input of counter 6. Described the duty cycle of the first memory cell is repeated in the second and subsequent memory cells of the device. Since the PZ-flip-flop 7 remains in a single state during the countdown time interval recorded in the reversing counter 2 of the number of pulses, the duration of the output pulse of memory cell 3, with an accuracy of the repetition period of the clock pulses, is equal to the duration of the input pulse. Moreover, when several memory cells are connected in series, an error does not accumulate in the reproduction of the duration of the input pulse at the output, since the output pulse of the first memory cell of the hard disk is occupied by the front R of the front of the clock pulse, and its duration is equal to an integer number of clock pulse repetition periods. If a pulse is delayed, it is equal to an integer number of periods of repetition of clock pulses and phased relative to the clock edge (which almost always occurs in practical devices, the pulse is reproduced at the output of the device without distorting the An duration, it is necessary to fulfill the conditions for undistorted pulse transmission through the shift register. Benefits of the proposed device are determined by combining the positive characteristics in it as a known device (reducing the volume of tours for a given delay time) and devices for delaying shift registers (storing information about the length of the delayed signal). Due to this, the proposed device can be used in blocks of digital delay of pulses i instead of shift registers; the amount of equipment while maintaining a predetermined delay time, i.e., the device has a wider field of application compared with the known device. The invention of the device for shifting the information, containing the generator of the clock pulse of the cell PACKET, each of which consists of a storage element, the element AND, and a counter, the output of which is connected to the first input of the storage element, the output of the memory element AND connected to the first input of the element AND which is connected to the input of the counter, the second input of the element I is connected to the output of the clock pulse generator, characterized in that, in order to increase the reliability of the device, a reversible counter is inserted into it, the decrypt RATOR, RS-trigger and the element NOT, whose input is connected to the first input of the device and to the input of the reversible counter, the second input of the reversible counter is connected to the output of the ge-. clock pulse, the output of the reversible counter is connected to the input of the decoder, the output of which is connected to the nepBbDvi input of the RS flip-flop, the second input of the RS flip-flop is connected to the output of the counter of the first memory cell, the third inputs of the reversible counter to the 5 $ -trigger are connected to the input of the last tsey cell memory. Sources of information taken into account during the examination I. USSR author's certificate No. 586499, cl. G 11 C 19 / OO, 1977 2. USSR author's certificate number 423176, cl. G II C 19 / OO, 1974 (prototype).