JP2656642B2 - Selector circuit - Google Patents
Selector circuitInfo
- Publication number
- JP2656642B2 JP2656642B2 JP2005076A JP507690A JP2656642B2 JP 2656642 B2 JP2656642 B2 JP 2656642B2 JP 2005076 A JP2005076 A JP 2005076A JP 507690 A JP507690 A JP 507690A JP 2656642 B2 JP2656642 B2 JP 2656642B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- terminal
- logical value
- selector circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路に関し、特に、半導体集積
回路により形成されたセレクタ回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a selector circuit formed by a semiconductor integrated circuit.
従来の技術 従来の半導体集積回路におけるセレクタ回路として
は、第４図に示すように、２入力NOR8の第１の入力を入
力端子16に、第２の入力を入力端子14に接続し、２入力
NOR9の第１の入力を入力端子15に、第２の入力をインバ
ータ７の出力に接続し、インバータ７の入力を入力端子
14に接続し、２入力NOR10の第１の入力を２入力NOR8の
出力に、第２の入力を２入力NOR9の出力に接続し、２入
力NOR10の出力を出力端子22に接続し、入力端子14を制
御することにより入力端子15及び16のデータを選択する
ことができる回路構成となっていた。2. Description of the Related Art As a selector circuit in a conventional semiconductor integrated circuit, as shown in FIG. 4, a first input of a two-input NOR 8 is connected to an input terminal 16, a second input is connected to an input terminal 14, and
Connect the first input of NOR9 to input terminal 15, the second input to the output of inverter 7, and connect the input of inverter 7 to the input terminal.
14, the first input of the two-input NOR10 is connected to the output of the two-input NOR8, the second input is connected to the output of the two-input NOR9, the output of the two-input NOR10 is connected to the output terminal 22, By controlling the circuit 14, the data of the input terminals 15 and 16 can be selected.
すなわち、入力端子14が論理値“0"のとき２入力NOR8
の出力は入力端子16のデータの反転となり、２入力NOR9
の出力は論理値“0"となる。よって２入力NOR10の出力
は２入力NOR8の出力の反転となり、出力端子22には入力
端子16のデータが得られる。入力端子14が論理値“1"の
ときには出力端子22に入力端子15のデータが得られる。That is, when the input terminal 14 has the logical value "0", the two-input NOR8
Output becomes the inversion of the data of the input terminal 16 and the 2-input NOR9
Has a logical value "0". Therefore, the output of the two-input NOR 10 is the inverse of the output of the two-input NOR 8, and the data of the input terminal 16 is obtained at the output terminal 22. When the logical value of the input terminal 14 is “1”, the data of the input terminal 15 is obtained at the output terminal 22.
第５図は第４図に示されたセレクタ回路の動作を示す
波形図であり、第５図において入力信号Ａ′、Ｂ′は第
４図の入力端子15、16の入力信号にそれぞれ対応し、入
力信号Ｓ′は第４図の入力端子14の入力信号に対応す
る。FIG. 5 is a waveform diagram showing the operation of the selector circuit shown in FIG. 4. In FIG. 5, input signals A 'and B' correspond to the input signals of input terminals 15 and 16 in FIG. , Input signal S 'corresponds to the input signal at input terminal 14 in FIG.
今入力信号Ａ′、Ｂ′が共に論理値“0"で、制御信号
Ｓ′が論理値“0"から“1"に変化すると、第４図の２入
力NOR9の出力は、２入力NOR8の出力よりインバータ７の
遅延分だけ遅れて変化する。このために２入力NOR10の
出力は、第５図の出力信号Ｙ′に示すように、インバー
タ７の遅延時間分だけ論理値“1"になる。Now, when the input signals A 'and B' are both at the logical value "0" and the control signal S 'changes from the logical value "0" to "1", the output of the two-input NOR9 of FIG. It changes with a delay of the inverter 7 from the output. For this reason, the output of the two-input NOR 10 becomes a logical value "1" for the delay time of the inverter 7, as shown by the output signal Y 'in FIG.
このように２つの入力信号が共に論理値“0"で変化し
ていないにもかかわらず、制御信号の変化によってセレ
クタ回路の出力にグリッチノイズが発生する。As described above, the glitch noise is generated at the output of the selector circuit due to the change of the control signal even though the two input signals are not changed at the logical value “0”.
発明が解決しようとする課題 上述した従来のセレクタ回路は、制御信号の切り替え
時にグリッチノイズが発生するために、セレクタ回路の
出力をＤ型フリップフロップ回路のクロック入力やセッ
ト．リセット入力に接続した場合には、Ｄ型フリップフ
ロップが誤動作すると言う欠点がある。Problems to be Solved by the Invention In the above-described conventional selector circuit, since glitch noise is generated when the control signal is switched, the output of the selector circuit is input to the clock input of the D-type flip-flop circuit or the set. When connected to the reset input, there is a disadvantage that the D-type flip-flop malfunctions.
本発明は従来の上記実情に鑑みてなされたものであ
り、従って本発明の目的は、従来の技術に内在する上記
欠点を解消することを可能とした新規なセレクタ回路を
提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional circumstances, and it is therefore an object of the present invention to provide a novel selector circuit which can eliminate the above-mentioned disadvantages inherent in the prior art.
課題を解決するための手段 上記目的を達成する為に、本発明に係るセレクタ回路
は、第１の入力端子をインバータの入力と第１の２入力
NORの第１の入力に接続し、前記インバータの出力を第
２の２入力NORの第１の入力に接続し、前記第１の２入
力NORの出力を前記第２の２入力NORの第２の入力と第３
の２入力NORの第１の入力に接続し、前記第２の２入力N
ORの出力を前記第１の２入力NORの第２の入力と第４の
２入力NORの第１の入力に接続し、第２の入力端子を前
記第３の２入力NORの第２の入力に接続し、第３の入力
端子を前記第４の２入力NORの第２の入力に接続し、前
記第３の２入力NORの出力を第５の２入力NORの第１の入
力に接続し、前記第４の２入力NORの出力を前記第５の
２入力NORの第２の入力に接続し、該第５の２入力NORの
出力を出力端子に接続して構成される。Means for Solving the Problems To achieve the above object, a selector circuit according to the present invention comprises a first input terminal connected to an input of an inverter and a first two inputs.
A first input of a NOR, an output of the inverter is connected to a first input of a second two-input NOR, and an output of the first two-input NOR is a second output of the second two-input NOR. Input and the third
Connected to a first input of a two-input NOR of the second
An output of the OR is connected to a second input of the first two-input NOR and a first input of a fourth two-input NOR, and a second input terminal is connected to a second input of the third two-input NOR. And the third input terminal is connected to the second input of the fourth two-input NOR, and the output of the third two-input NOR is connected to the first input of the fifth two-input NOR. , The output of the fourth two-input NOR is connected to the second input of the fifth two-input NOR, and the output of the fifth two-input NOR is connected to an output terminal.
実施例 次に、本発明をその好ましい一実施例について図面を
参照して具体的に説明する。Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.
第１図は本発明によるセレクタ回路の一実施例を示す
回路図であり、第２図は第１図の回路における波形の説
明図である。FIG. 1 is a circuit diagram showing an embodiment of a selector circuit according to the present invention, and FIG. 2 is an explanatory diagram of waveforms in the circuit of FIG.
第１図を参照するに、本発明の一実施例は、第１の入
力端子11をインバータ１の入力と２入力NOR2の第１の入
力に接続し、インバータ１の出力を２入力NOR3の第１の
入力に接続し、２入力NOR2の出力を２入力NOR3の第２の
入力と２入力NOR4の第１の入力に接続し、２入力NOR3の
出力を２入力NOR2の第２の入力と２入力NOR5の第１の入
力に接続し、第２の入力端子12を２入力NOR4の第２の入
力に接続し、第３の入力端子13を２入力NOR5の第２の入
力に接続し、２入力NOR4の出力を２入力NOR6の第１の入
力に接続し、２入力NOR5の出力を２入力NOR6の第２の入
力に接続し、２入力NOR6の出力を出力端子21に接続して
構成されている。Referring to FIG. 1, in one embodiment of the present invention, the first input terminal 11 is connected to the input of the inverter 1 and the first input of the two-input NOR2, and the output of the inverter 1 is connected to the second input of the NOR3. One input is connected to the input of the two-input NOR2, the output of the two-input NOR3 is connected to the second input of the two-input NOR3, and the output of the two-input NOR3 is connected to the second input of the two-input NOR2. Connecting the first input of the input NOR5, the second input terminal 12 to the second input of the two-input NOR4, the third input terminal 13 to the second input of the two-input NOR5, The output of the input NOR4 is connected to the first input of the two-input NOR6, the output of the two-input NOR5 is connected to the second input of the two-input NOR6, and the output of the two-input NOR6 is connected to the output terminal 21. ing.
入力端子11が論理値“1"のとき２入力NOR2の出力は論
値値“0"となり、２入力NOR3の出力は論理値“1"とな
る。従って、２入力NOR4の出力は入力端子12のデータの
反転となり、又、２入力NOR5の出力は論理値“0"となる
ために、２入力NOR6の出力は２入力NOR4の出力の反転と
なり、出力端子21には入力端子12のデータが得られる。
入力端子11が論理値“0"の時には出力端子21に入力端子
13のデータが得られる。When the input terminal 11 has the logical value "1", the output of the two-input NOR2 becomes the logical value "0", and the output of the two-input NOR3 becomes the logical value "1". Therefore, the output of the two-input NOR4 becomes the inversion of the data of the input terminal 12, and the output of the two-input NOR5 becomes the logical value "0", so that the output of the two-input NOR6 becomes the inversion of the output of the two-input NOR4. The data of the input terminal 12 is obtained at the output terminal 21.
When the input terminal 11 has the logical value "0", the input terminal is connected to the output terminal 21.
13 data are obtained.
第２図は本発明のセレクタ回路の動作を示す波形図で
あり、第２図において、入力信号Ａ、Ｂ、Ｓは第１図の
入力端子12、13、11の入力信号にそれぞれ対応し、信号
AS、BSは第１図の２入力NOR2及び２入力NOR3の出力信号
にそれぞれ対応する。また、信号Ｙは第１図の出力端子
21の出力信号に対応している。FIG. 2 is a waveform diagram showing the operation of the selector circuit of the present invention. In FIG. 2, input signals A, B, and S correspond to input signals of input terminals 12, 13, and 11 in FIG. signal
AS and BS correspond to the output signals of the two-input NOR2 and two-input NOR3 of FIG. 1, respectively. The signal Y is the output terminal of FIG.
It corresponds to 21 output signals.
いま制御信号Ｓが論理値“1"から“0"に変化すると、
信号BSは論理値“1"から“0"に変化し、信号ASは２入力
NOR2の遅延分だけ遅れて論理値“0"から“1"に変化す
る。従って、信号ASと信号BSは２入力NOR2の遅延時間分
だけ論理値“0"が重なる。又、制御信号Ｓが論理値“0"
から“1"に変化すると、信号ASと信号BSは２入力NOR3の
遅延時間分だけ論理値“0"が重なる。Now, when the control signal S changes from the logical value “1” to “0”,
The signal BS changes from the logical value “1” to “0”, and the signal AS has two inputs.
The logical value changes from “0” to “1” with a delay of NOR2 delay. Therefore, the logical value “0” of the signal AS and the signal BS overlaps by the delay time of the two inputs NOR2. Also, the control signal S has a logical value “0”.
From "1" to "1", the logical values "0" of the signal AS and the signal BS overlap by the delay time of the two inputs NOR3.
第３図は制御信号Ｓの論理値を“1"から“0"に変化し
た場合と“0"から“1"に変化した場合の出力信号Ｙの真
理値表であり、Ａの論理値及びＢの論理値はこれ以外の
組合せは取りえない。制御信号Ｓの論理値が“1"から
“0"に変化した場合、出力信号Ｙは、Ａのデータ→Ａ・
Ｂのデータ→Ｂのデータの順番で出力される。又、制御
信号Ｓの論理値が“0"から“1"に変化した場合には、出
力信号Ｙは、Ｂのデータ→Ａ・Ｂのデータ→Ａのデータ
の順番で出力される。従って、第３図の真理値表からも
明らかなように出力信号Ｙには、制御信号Ｓが変化して
もグリッチノイズが発生しない。FIG. 3 is a truth table of the output signal Y when the logical value of the control signal S changes from "1" to "0" and when the logical value of the control signal S changes from "0" to "1". The logical value of B cannot take any other combination. When the logical value of the control signal S changes from “1” to “0”, the output signal Y becomes A data → A ·
The data is output in the order of B data → B data. When the logical value of the control signal S changes from "0" to "1", the output signal Y is output in the order of B data → AB data → A data. Therefore, as is clear from the truth table of FIG. 3, the output signal Y does not generate glitch noise even when the control signal S changes.
発明の効果 以上説明したように、本発明によれば、セレクタ回路
の制御信号回路にＲ−Ｓフリップフロップを付加するこ
とによって、セレクタ回路の制御信号の切り替え時に発
生していたグリッチノイズを防ぐことができるという効
果が得られる。As described above, according to the present invention, glitch noise generated when switching the control signal of the selector circuit is prevented by adding the RS flip-flop to the control signal circuit of the selector circuit. Is obtained.
第１図は本発明に係るセレクタ回路の一実施例を示す回
路構成図、第２図は第１図の回路における波形の説明
図、第３図は第１図における真理値表の説明図、第４図
は従来の技術によるセレクタ回路の構成例を示す回路
図、第５図は第４図の回路における波形の説明図であ
る。 １、７……インバータ、２、３、４、５、６、８、９、
10……２入力NOR、11、12、13、14、15、16……入力端
子、21、22……出力端子FIG. 1 is a circuit diagram showing an embodiment of a selector circuit according to the present invention, FIG. 2 is an explanatory diagram of waveforms in the circuit of FIG. 1, FIG. 3 is an explanatory diagram of a truth table in FIG. FIG. 4 is a circuit diagram showing a configuration example of a conventional selector circuit, and FIG. 5 is an explanatory diagram of waveforms in the circuit of FIG. 1, 7,..., Inverters, 2, 3, 4, 5, 6, 8, 9,
10 ... 2 input NOR, 11, 12, 13, 14, 15, 16 ... input terminal, 21, 22 ... output terminal
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−224413（ＪＰ，Ａ) 特開 平２−193412（ＪＰ，Ａ) 実開 平２−1922（ＪＰ，Ｕ) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-224413 (JP, A) JP-A-2-193412 (JP, A) JP-A-2-1922 (JP, U)
Claims (1)
の２入力NORの第１の入力に接続し、前記インバータの
出力を第２の２入力NORの第１の入力に接続し、前記第
１の２入力NORの出力を前記第２の２入力NORの第２の入
力と第３の２入力NORの第１の入力に接続し、前記第２
の２入力NORの出力を前記第１の２入力NORの第２の入力
と第４の２入力NORの第１の入力に接続し、第２の入力
端子を前記第３の２入力NORの第２の入力に接続し、第
３の入力端子を前記第４の２入力NORの第２の入力に接
続し、前記第３の２入力NORの出力を第５の２入力NORの
第１の入力に接続し、前記第４の２入力NORの出力を前
記第５の２入力NORの第２の入力に接続し、該第５の２
入力NORの出力を出力端子に接続した事を特徴とするセ
レクタ回路。A first input terminal is connected to an input of an inverter and a first input terminal.
Connected to a first input of a two-input NOR, an output of the inverter is connected to a first input of a second two-input NOR, and an output of the first two-input NOR is connected to the second two-input NOR. A second input of the second NOR and a first input of a third two-input NOR,
Is connected to the second input of the first two-input NOR and the first input of the fourth two-input NOR, and the second input terminal is connected to the third input of the third two-input NOR. And the third input terminal is connected to the second input of the fourth two-input NOR, and the output of the third two-input NOR is connected to the first input of the fifth two-input NOR. And the output of the fourth two-input NOR is connected to the second input of the fifth two-input NOR.
A selector circuit wherein the output of an input NOR is connected to an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005076A JP2656642B2 (en) | 1990-01-12 | 1990-01-12 | Selector circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005076A JP2656642B2 (en) | 1990-01-12 | 1990-01-12 | Selector circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03209913A JPH03209913A (en) | 1991-09-12 |
| JP2656642B2 true JP2656642B2 (en) | 1997-09-24 |
Family
ID=11601300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005076A Expired - Lifetime JP2656642B2 (en) | 1990-01-12 | 1990-01-12 | Selector circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2656642B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02224413A (en) * | 1989-02-27 | 1990-09-06 | Nec Corp | 2-1 selector circuit |
-
1990
- 1990-01-12 JP JP2005076A patent/JP2656642B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03209913A (en) | 1991-09-12 |
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