JPH0468915A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To improve the degree of freedom in a logic design and to optimize a timing design by providing a logic circuit subjected to switching control with a 1st input signal and outputting a 2nd logic signal in response to a 2nd input signal and a 1st logic signal to a 2nd node on this flip-flop circuit. CONSTITUTION:With a reset signal R inputted to a reset terminal 1 going to logic '1', outputs of NOR gates 21, 31 and 11 go respectively to zero, an output signal Q is stable to be logic '0' and an inverse output signal Q is stable to be logic '1' respectively and the output is latched by a latch section 10. The output signal Q and the inverse output signal Q are independent of the logic level of the reset signal R. Moreover, a 1st logic signal S1 outputted to a node N3 is changed in a complementary relation in a prescribed timing in response to the logic level of a set signal S. Thus, the degree of freedom in the logic design and the timing design are optimized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is applicable to flip-flop circuits in digital logic circuits, especially those that have an input inhibit mode such as a reset set (hereinafter referred to as R3) flip-flop circuit. The present invention relates to a circuit configuration of a flip-flop circuit having the present invention.

(Prior Art) Conventionally, there has been a technology in this field as shown in FIG. 2, for example. The ellipse and formation will be explained below using diagrams.

FIG. 2 is a circuit diagram of a conventional RS flip-flop circuit.

This RS flip-flop circuit is built into an integrated circuit or the like together with other circuits, and has a reset terminal 1 that inputs a reset signal R, a set terminal 2 that inputs a set signal S, and an output that outputs an output signal Q. terminal 3,
and an inverted output terminal 4 for outputting an inverted output terminal for the output signal Q, and a latch section 10 connected between them.

The latch unit 10 includes negative sum gates (hereinafter referred to as NOR gates) 11 and 12. NOR gate 11
The input side is connected to the reset terminal 1 via the node N1, and is also connected to the inverting output terminal 4, and the output side is connected to the output terminal 3. The NOR gate 12 has an input side connected to the set terminal 2 via the node N2, an output terminal 3, and an output side connected to the inverting output terminal 4.

Next, the operation of this RS flip-flop 1 circuit will be explained with reference to Table 1. Note that Table 1 is a truth table for the RS flip-flop 1 circuit shown in FIG.

Table 1 As can be seen from Table 1, in this circuit, when the set signal S is at a high level (hereinafter referred to as "1"), the output signal Q is "
1” and is set, and the reset signal R becomes “’1”.
At this time, the output signal Q becomes "0" and is reset. Furthermore, when both the set signal S and the reset signal R are set to "0", the output of the output signal Q remains unchanged.

However, both the set signal S and the reset signal R are “
A state of 1'' is an input prohibition mode, and such an input would make the circuit unstable, so such an input is not allowed.

(Problem M to be solved by the invention) However, in the flip-flop circuit with the above configuration,
Since it is necessary to avoid the input prohibition mode, it is necessary to implement a logic design that prevents the output that would cause the input prohibition mode to occur in the circuit etc. in the previous stage to which the reset terminal 1 and the set terminal 2 are connected. This limits the degree of freedom in the logic design of integrated circuits. Furthermore, it has been difficult to optimize circuit timing design.

(Means for Solving the Problem) In order to solve the problem, the present invention has an input prohibition mode, and latches the signals input to the first and second nodes at a predetermined timing. In a flip-flop circuit having a latch section that outputs a result, a second input signal complementary to the second input signal is generated based on a first input signal and a second input signal supplied to the first node. 1
a timing adjustment unit that generates and holds a logic signal at a predetermined timing; and a second logic signal that is controlled to open and close by the first input signal and that corresponds to the second input signal and the first logic signal. and a logic circuit for outputting to the second node.

(Function) According to the present invention, since the flip-flop circuit is configured as described above, the timing adjustment section adjusts the second input signal based on the first input signal and the second input signal. A complementary first logic signal is generated and held at a predetermined timing, for example, when the logic level of the second input signal changes, a predetermined delay time has elapsed from the time when the logic level changes.

The logic circuit is controlled to open and close based on the first input signal, and for example, when it is in a closed state, it outputs a signal at a predetermined logic level to the second node, and when it is in an open state, it outputs a signal at a predetermined logic level to the second node. When the logic levels of the input signal and the first logic signal are in a complementary relationship, the signal at the predetermined logic level is sent to the second node by either the second input signal or the first logic signal. Output to.

On the other hand, when the logic circuit is open and the logic levels of the second input signal and the first logic signal are the same, the logic circuit has a logic level complementary to the predetermined logic level. 2 logic signals are output. Here, the coincidence of the logic levels of the second input signal and the first logic signal is determined by the generation of the first logic signal being performed with a predetermined time lag from the time point at which the logic level of the second input signal changes. It is realized in order to be realized. Therefore, the second input signal and the second logic signal have a complementary relationship at a predetermined timing, so that the output of the logic circuit to the second node is changed from the second logic signal to the predetermined one again. Return to the logic level signal.

In this way, when the logic circuit is in a closed state, for example, the first input signal is supplied to the first node, and the signal at the predetermined logic level is input to the second node. , the latch section latches these inputs and outputs an output signal according to the latching result. At this time,
As the logic level of the second input signal changes, the logic level of the output signal of the latch section remains constant.

In addition, when the logic circuit is open, the first
When the input signal is input to the first node, when the second logic signal is output to the second node,
The second logic signal serves as a trigger, and the output signal is held with its logic level inverted by the latch section.

Therefore, the above problem can be solved.

(Example) FIG. 1 shows R379717 showing the first example of the present invention.
In Figure 0, which is a circuit configuration diagram of the 071 circuit, common elements with those in Figure 2 are given the same reference numerals.

This R379717071 circuit has a first circuit similar to that shown in FIG.
a reset terminal 1 to which a reset signal R is input, a set terminal 2 to which a set signal S, which is a second input signal, is input, an output terminal 3, an inverted output terminal 4, a latch unit 10, and nodes N1 and N2. In addition, it has a timing adjustment section 20 and a logic circuit 30, which are the characteristics of this embodiment.

The timing adjustment section 20 includes two NOR gates 21 and 22 with one output. The NOR gate 1 21 has one input side connected to the reset terminal 1 via the node N1, the other input side connected to the node N3, and the output side connected to one input side of the NOR gate 22. ing. Further, the other input side of the NOR gate 22 is connected to the set terminal 2, and the output side is connected to the node N3.

The logic circuit i30 is, for example, a NOR gate 3 with three inputs and one output.
It consists of 1. The input side of the NOR gate 31 is connected to the reset terminal 1, the set terminal 2, and the node N3, respectively, and the output side is connected to the node N2.

Next, the operation of this R379717071 circuit will be explained with reference to Table 2. Note that Table 2 is a truth table of the RS flip-flop 1 circuit shown in FIG.

However, * means don't care.

Table 2 When the reset signal R input to the reset terminal 1 is 1", the outputs of the NOR gates 21 and 31 and the NOR gate 11 are each "0", the output signal Q is "0", and the inverted output signal is is stabilized at 1'°, and this output is held by the latch section 10. The output signal Q and the inverted output signal at this time do not depend on the logic level of the set signal R.

Furthermore, the first logic signal S1 output to the node N3 is
Depending on the logic level of the set signal S, the relationship changes to a complementary one at a predetermined timing.

Next, from this state, when the reset signal R is set to "O" and the set signal S is changed from "1" to "0", the logic signal S1 is "°0" when the set signal S is "°1". Therefore, the logic signal S2 of 1" from the output 1 law of the NOR gate 31
is output, and the inverted output signal that is the output of the NOR gate 12 becomes "○P", and by passing through the bus in the latch section 10, the output signal Q becomes "P1". During this time N
The flip-flop composed of OR gates 21 and 22 operates, and the logic signal S1 becomes "1", so that the NOR
Gate 31 is made inactive. This NOR gate 31 is
The inactive state is maintained until the reset signal R becomes "1".

In this manner, the R879717071 circuit shown in FIG. 1 is set by the falling edge of the set signal S, and is preferentially reset when the reset signal R becomes "1".

In this first embodiment, by giving priority to the reset signal R and making the set signal S an edge trigger type in the RS flip-flop shown in FIG. 1, it is possible to eliminate the input inhibit mode and to design accurate timing. This has the advantage of increasing the degree of freedom in logic design and optimizing timing design.

FIG. 3 shows R879717 showing a second embodiment of the present invention.
In Figure 0, which is a circuit configuration diagram of the 071 circuit, common elements with those in Figure 1 are given the same reference numerals.

This R879717071 circuit is the RS of the first embodiment.
It has the same configuration as the flip-flop 1 circuit, but differs from it in that the positions of the reset terminal 1 and set terminal 2 are exchanged, and the positions of the output terminal 3 and the inverted output terminal 4 are exchanged. be.

The second embodiment operates in substantially the same manner as the first embodiment as shown in Table 3.

Note that Table 3 is a truth table for the RS flip-flop 1 circuit shown in FIG. That is, the flip-flop circuit in FIG.
The set signal S, which is the first input signal, has priority, and the reset signal R, which is the second input signal, is of an edge trigger type.

Table 3 This second embodiment also provides substantially the same functions and effects as the first embodiment.

FIG. 4 is a circuit configuration diagram of an RS flip-flop 1 circuit showing a third embodiment of the present invention. In the figure, common elements with those in FIG. 1 are given the same reference numerals.

This R879717071 circuit replaces the latch section 10 with NOR gates 11 and 12 in the RS flip-flop 1 circuit shown in FIG.
The timing adjustment section 20 is constructed with NAND gates 23.24 instead of the NOR gates 21.22, and the logic circuit 30 is constructed with NAND gates 32 instead of the NOR gates 31. It is composed of

This third embodiment provides substantially the same functions and effects as those of the first embodiment.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(I>Each R8797170 in the first, second, and third embodiments
The circuit configuration of the 71 circuit can be modified. For example, the latch section 10, the timing adjustment section 20, and the logic circuit 3
0 may have other configurations for its constituent elements such as logic gates. Further, in accordance with changes in the configuration, timing settings of the logic levels of the reset signal R, set signal S, logic signals Sl, S2, etc. can be changed as appropriate.

For example, it may be reset or set by the rising edge of the reset signal R or the set signal S, which is the second input signal.

(II) In the first, second and third embodiments, the present invention is applied to R8
Although the case where the present invention is applied to the 79717071 circuit has been described, the present invention can be widely applied to flip-flop circuits having an input prohibition mode other than R, S flip-flop circuits.

(Effects of the Invention) As described in detail above, according to the present invention, the flip-flop circuit is configured by providing the timing adjustment section and the logic circuit in addition to the latch section, so that the first input signal can be prioritized and the second input signal can be edge-triggered, making it possible to eliminate the input inhibit mode and perform accurate timing design, thereby increasing the degree of freedom in logic design and optimizing timing design.

[Brief explanation of the drawing]

FIG. 1 shows an RS flip-flop 1 according to a first embodiment of the present invention.
2 is a circuit configuration diagram of a conventional RS flip-flop circuit, FIG. 3 is a circuit configuration diagram of an RS flip-flop circuit according to a second embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional RS flip-flop circuit. FIG. 3 is a circuit configuration diagram of an RS flip-flop circuit showing a third embodiment of the present invention. 10... Latch part, 11.12, 21.22.31.
・・NOR gate, 13, 14.23, 24.32・・
・NAND gate, 20...timing adjustment section, 30
...logic circuit, R...reset signal, S...set signal, Q...output signal, mutually...inverted output signal mutually,
81°S2...Logic signal, Nl, N2. N3...Node.

Claims (1)

[Scope of Claims] A flip-flop circuit having an input prohibition mode and having a latch section that latches signals input to the first and second nodes at a predetermined timing and outputs the latched results, comprising: Timing for generating and holding a first logic signal complementary to the second input signal at a predetermined timing based on a first input signal and a second input signal supplied to one node; an adjustment unit; and a logic circuit that is controlled to open and close by the first input signal and outputs a second logic signal corresponding to the second input signal and the first logic signal to the second node. A flip-flop circuit characterized by: