JP2652229B2 - Multilayer circuit ceramic substrate - Google Patents
Multilayer circuit ceramic substrateInfo
- Publication number
- JP2652229B2 JP2652229B2 JP63331920A JP33192088A JP2652229B2 JP 2652229 B2 JP2652229 B2 JP 2652229B2 JP 63331920 A JP63331920 A JP 63331920A JP 33192088 A JP33192088 A JP 33192088A JP 2652229 B2 JP2652229 B2 JP 2652229B2
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- Prior art keywords
- dielectric constant
- glass
- layer
- substrate
- insulating layer
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Description
【発明の詳細な説明】 イ.発明の目的 産業上の利用分野 本発明は誘電率の高い誘電体層を内蔵した大容量コン
デンサを有する低温同時焼成の積層回路セラミック基板
に関する。DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-temperature co-fired multilayer circuit ceramic substrate having a large-capacity capacitor having a dielectric layer with a high dielectric constant.
従来の技術 近年電子機器あるいは電子装置などにおいて、IC、LS
Iを実装する回路基板への小型化要求が高まっている。
従来電子回路基板としては、セラミックを多層化し、そ
の各層に導体を配線し、各層間を接続するスルーホール
やビヤホールを有する多層回路セラミック基板が使用さ
れている。この回路基板において、コンデンサ部品は通
常チップコンデンサと呼ばれるコンデンサ素子を回路基
板の表面に、はんだ付けして使用されている。然しなが
ら回路基板の表面は、半導体素子や表面配線導体があ
り、さらにコンデンサ素子を搭載すると基板が大きくな
るため半導体IC等をより高集積に搭載するにはある程度
の限界がある。これ等の素子を基板内に内蔵化できれば
基板の小型化、集積化が可能となる。そこで内部に高誘
電率を有する誘電体層を高容量コンデンサとして内蔵
し、誘電体層以外の絶縁体層には、誘電率が15以下の低
誘電率材料を使用した積層基板が報告されている。2. Description of the Related Art In recent years, in electronic equipment or electronic devices, IC, LS
There is an increasing demand for miniaturization of circuit boards on which I is mounted.
2. Description of the Related Art Conventionally, as an electronic circuit board, a multilayer circuit ceramic board having a multilayer ceramic, wiring conductors in each layer, and having through holes and via holes connecting the respective layers has been used. In this circuit board, a capacitor component is generally used by soldering a capacitor element called a chip capacitor to the surface of the circuit board. However, the surface of the circuit board has semiconductor elements and surface wiring conductors, and the mounting of a capacitor element increases the size of the board. Therefore, there is a certain limit in mounting a semiconductor IC or the like with higher integration. If these elements can be built into the substrate, the substrate can be reduced in size and integrated. Therefore, it has been reported that a laminated substrate in which a dielectric layer having a high dielectric constant is built in as a high-capacitance capacitor and a low dielectric constant material having a dielectric constant of 15 or less is used as an insulating layer other than the dielectric layer. .
発明が解決しようとする課題 内蔵化した積層基板の誘電体材料は、一般に絶縁材料
と組成が異なり、鉛を含むペロブスカイトの構造のもの
が使用されている。組成の異なる2種類の誘電体材料を
同時焼成により積層した場合、熱膨張係数の相違により
生じる応力や、各材料が反応することにより界面に生じ
るポアが原因となってそりが発生する。このため信頼性
が著しく低下して実用的な積層基板を得ることはできな
かった。Problems to be Solved by the Invention The dielectric material of a built-in laminated substrate generally has a composition different from that of an insulating material, and has a perovskite structure containing lead. When two types of dielectric materials having different compositions are laminated by simultaneous firing, warpage occurs due to stress generated due to a difference in thermal expansion coefficient and pores generated at an interface due to reaction between the materials. For this reason, the reliability was remarkably reduced, and a practical laminated substrate could not be obtained.
また、内蔵化する高誘電率材料は組成によって固有の
温度特性を持っているので、多種類の温度特性の材料を
必要とする場合、それに応じて基本となる組成系を変更
したり、各種添加物を選択して対応している。その他絶
縁層との整合性も問題となり、結局、従来このような多
層基板は工程的、コスト面の不利は免れなかった。Also, since the high dielectric constant material to be built in has a specific temperature characteristic depending on the composition, if a material with various types of temperature characteristics is required, the basic composition system must be changed or various additives added. We choose thing and cope. In addition, compatibility with the insulating layer also becomes a problem, and in the end, such a multilayer substrate has been inevitably disadvantageous in terms of process and cost.
本発明は以上の問題点を解決し広範な温度特性に対応
できるコンデンサを内蔵した信頼性の高い積層基板を提
供するものである ロ。発明の構成 課題を解決するための手段 上記課題を解決するための手段としての本発明の請求
項1の積層回路セラミック基板は、内蔵または外表面に
酸化鉛を含むペロブスカイト系の誘電率が15を超える高
誘電体層と誘電率が15以下の低誘電率絶縁層を含み一体
的に800〜1100℃で低温同時焼成される基板において、
該高誘電体層と低誘電率絶縁層の間に緩衝電極を設け、
また該高誘電体層中に、該低誘電率絶縁層に含まれる同
一成分系のガラス成分を0.1〜1.0重量%添加したことを
特徴とする。The present invention solves the above problems and provides a highly reliable laminated substrate having a built-in capacitor capable of coping with a wide range of temperature characteristics. MEANS FOR SOLVING THE PROBLEMS The laminated circuit ceramic substrate according to claim 1 of the present invention as a means for solving the above-mentioned problem has a dielectric constant of 15 perovskite containing lead oxide on its internal or external surface. On a substrate that is simultaneously fired at a low temperature of 800 to 1100 ° C including a high dielectric layer and a low dielectric constant insulating layer having a dielectric constant of 15 or less,
Providing a buffer electrode between the high dielectric layer and the low dielectric constant insulating layer,
Further, the same dielectric glass component contained in the low dielectric constant insulating layer is added to the high dielectric layer in an amount of 0.1 to 1.0% by weight.
請求項2の積層回路セラミック基板は、前記請求項1
の発明において、前記ガラス成分が、CaO−Al2O3−SiO2
−B2O3系であることを特徴とする。The multilayer circuit ceramic substrate according to claim 2 is the above-described claim 1.
In the invention, the glass component, CaO-Al 2 O 3 -SiO 2
Characterized in that it is a -B 2 O 3 system.
作用 低誘電率のセラミック材料としては、800〜1100℃で
焼成可能なものを使用する。かかる材料としては、硼珪
酸ガラスやさらに数種類の酸化物(例えばMgO、CaO、Ba
O、Al2O3、PbO、K2O、Na2O、ZnO、Li2Oなど)を含むガ
ラスとアルミナ、石英などとの混合物を原料とするもの
が挙げられる。以上のほか800〜1100℃で焼成できるも
のであればよい。誘電率は15以下、好ましくは10以下の
ものがよい。Action As a low dielectric constant ceramic material, a material that can be fired at 800 to 1100 ° C. is used. Such materials include borosilicate glass and several more oxides (eg, MgO, CaO, Ba
As a raw material, a mixture of glass containing O, Al 2 O 3 , PbO, K 2 O, Na 2 O, ZnO, Li 2 O), alumina, quartz or the like can be used. In addition to the above, any material that can be fired at 800 to 1100 ° C may be used. The dielectric constant is 15 or less, preferably 10 or less.
高誘電率材料は、800〜1100℃で焼成可能な組成を使
用するが、同時焼成するので上記低誘電率材料の焼成温
度とほぼ一致するものを選定する必要がある。800〜110
0℃で焼成可能で誘電率が15を超える材料としては、Pb
(Fe1/3・Nb2/3)O3−(Fe1/2・W1/2)O3系に代表され
るPb系ペロブスカイト組成物が最も適している。これに
添加するガラスは前記の誘電率が15以下の低誘電率材料
中のガラスの成分系のものを用いる。As the high dielectric constant material, a composition that can be fired at 800 to 1100 ° C. is used, but since it is fired simultaneously, it is necessary to select a material that substantially matches the firing temperature of the low dielectric constant material. 800-110
Materials that can be fired at 0 ° C and have a dielectric constant of more than 15 include Pb
A Pb-based perovskite composition represented by (Fe 1/3 .Nb 2/3 ) O 3- (Fe 1/2 .W 1/2 ) O 3 is most suitable. As the glass to be added to this, a glass based on a low dielectric constant material having a dielectric constant of 15 or less is used.
第1図は、低温同時焼成基板中の高誘電体層の誘電率
と温度に対するガラス添加量の関係を示した。本来内層
コンデンサーの有するεr(誘電率)は、3000程度であ
るが、ガラス添加量を0.2、0.4、0.6重量%と増加させ
るに従い室温付近(約25℃)のキュリー点におけるεr
の値は、漸次減少していく。これに伴いεrの温度特性
は漸次平坦化して、ガラスがシフターとして作用してい
るのが判る。FIG. 1 shows the relationship between the dielectric constant of a high dielectric layer in a low-temperature co-fired substrate and the amount of glass added to temperature. Although the ε r (dielectric constant) of the inner layer capacitor is about 3000, the ε r at the Curie point near room temperature (about 25 ° C.) as the glass addition amount increases to 0.2, 0.4, and 0.6% by weight.
Is gradually decreasing. As a result, the temperature characteristic of ε r is gradually flattened, and it can be seen that the glass acts as a shifter.
第2図は、誘電損失(tanδ)と温度に対するガラス
添加量の関係を示した。ガラス添加量を増加すると室温
以上でtanδが劣化しているのが判る。好ましい誘電損
失は、室温で2%以下であるが、ガラスを1.0重量%添
加した材料は、25℃でtanδが約1.7%とガラス無添加の
ものに比べ約1.5%も劣化している。この結果よりガラ
ス添加量を1重量%を上限とした。また第1表は、基板
面積40×40mmの高誘電体層へのガラス添加量と基板の反
り量の関係を示した。ガラスの添加の増加に従い反り量
が緩和されていくのが判る。特に0.1重量%以上のガラ
ス添加は、反り量が無添加に比べ1/5以下に抑えられ顕
著に効果が現れているので、本発明のガラスの添加量の
下限を0.1重量%とした。FIG. 2 shows the relationship between the dielectric loss (tan δ) and the amount of glass added to the temperature. It can be seen that when the glass addition amount is increased, tan δ deteriorates at room temperature or higher. The preferable dielectric loss is 2% or less at room temperature, but the material added with 1.0% by weight of glass has a tan δ of about 1.7% at 25 ° C., which is about 1.5% deteriorated compared to the material without glass added. Based on this result, the upper limit of the glass addition amount was 1% by weight. Table 1 shows the relationship between the amount of glass added to the high dielectric layer having a substrate area of 40 × 40 mm and the amount of warpage of the substrate. It can be seen that the amount of warpage is reduced as the glass addition increases. In particular, when glass is added in an amount of 0.1% by weight or more, the amount of warpage is suppressed to 1/5 or less as compared with the case where no glass is added, so that a remarkable effect is exhibited.
以上述べた高誘電率材料と低誘電率材料は、ガラスの
成分系同一のため整合性がよく工程面、コスト面で有利
である。即ち焼成の際、誘電体材料に生じた液相は相互
反応をより円滑に行ない、これに伴って拡散したガラス
が誘電体基板をより均一に濡らし、熱膨張係数の相違か
ら発生する応力緩和する。 Since the high dielectric constant material and the low dielectric constant material described above have the same component system of glass, they have good compatibility and are advantageous in terms of process and cost. That is, during firing, the liquid phase generated in the dielectric material performs an interaction more smoothly, and accordingly, the diffused glass wets the dielectric substrate more uniformly, thereby relaxing the stress generated due to the difference in the coefficient of thermal expansion. .
ところで、表1に示すように、高誘電体層中に、該低
誘電率絶縁層に含まれる同一成分系のガラス成分を0.1
〜1.0重量%添加した場合であっても、完全な反りを防
止することができない。また、この高誘電体層と低誘電
率絶縁層では、ガラス成分の添加率が異なるため、該ガ
ラス成分が多い低誘電率絶縁層から該ガラス成分の少な
い高誘電体層に、該ガラス成分が移行し、誘電率が低下
する。しかし、本発明においては、該高誘電体層と低誘
電率絶縁層の間に緩衝電極を設けていることにより、反
りの発生をいっそう軽減することができ、また該緩衝電
極によって、ガラス成分の移行を軽減し、誘電率の低下
を防止できる。As shown in Table 1, the same component glass component contained in the low dielectric constant insulating layer was added to the high dielectric layer in an amount of 0.1%.
Even in the case of adding about 1.0% by weight, complete warpage cannot be prevented. Further, since the addition rate of the glass component is different between the high dielectric layer and the low dielectric constant insulating layer, the glass component is changed from the low dielectric constant insulating layer having a large amount of the glass component to the high dielectric layer having a small glass component. The transition occurs and the dielectric constant decreases. However, in the present invention, by providing a buffer electrode between the high dielectric layer and the low dielectric constant insulating layer, the occurrence of warpage can be further reduced. Migration can be reduced, and a decrease in dielectric constant can be prevented.
従って、高誘電体層と低誘電率絶縁層の熱膨張係数の
相違に起因する基板の反り、および誘電率の低下が抑え
られ、信頼性の高い基板を得ることができる。Therefore, the warpage of the substrate and the decrease in the dielectric constant caused by the difference in the thermal expansion coefficient between the high dielectric layer and the low dielectric constant insulating layer are suppressed, and a highly reliable substrate can be obtained.
実施例 低誘電率材料として、1450℃で溶融し、水中急冷して
作製したCaO18.2% Al2O318.2%、SiO254.5%、B2O39.1
%の組成を持つ平均粒径3〜3.5μmのガラス粉末60%
と、平均粒径1.2μmのアルミナ粉末40%の混合物に、
トルエンの溶剤、アクリル樹脂のバインダーとDOP可塑
剤を加え十分に混練して粘度2,000〜40,000CPSのスラリ
ーを作成した。さらに通常のドクターブレード法を用い
てこれを厚さ0.4mmの第3図に示す低誘電率グリーンシ
ート1を作成した。Example As a low dielectric constant material, CaO 18.2% Al 2 O 3 18.2%, SiO 2 54.5%, B 2 O 3 9.1 produced by melting at 1450 ° C. and quenching in water
60% glass powder with an average particle size of 3 to 3.5 μm
And a mixture of 40% alumina powder with an average particle size of 1.2 μm,
A toluene solvent, an acrylic resin binder, and a DOP plasticizer were added and sufficiently kneaded to prepare a slurry having a viscosity of 2,000 to 40,000 CPS. Further, a low dielectric constant green sheet 1 having a thickness of 0.4 mm as shown in FIG. 3 was prepared by using a usual doctor blade method.
このグリーンシートを900℃で焼成した基板の特性は
誘電率εr=7.8、嵩比重=2.9、熱膨張係数5.3×10-6/
℃、抗析強度=2400kg/cm2であった。The characteristics of the substrate obtained by firing this green sheet at 900 ° C. are as follows: dielectric constant ε r = 7.8, bulk specific gravity = 2.9, thermal expansion coefficient 5.3 × 10 −6 /
° C., precipitation strength = 2400 kg / cm 2 .
さらに、このグリーンシートを60mm角に切断した後、
0.3mmφスルーホール3を形成し、Ag90%、Pd10%の混
合粉末にエチルセルローズの有機バインダーとテレピネ
オール溶剤を加えて作成した導体材料ペースト4をスル
ーホール3に充填して同時導体ペーストを使用して配線
パターン6を印刷した。Furthermore, after cutting this green sheet into 60 mm square,
A through hole 3 is formed by forming a through hole 3 having a diameter of 0.3 mm, and a conductive material paste 4 prepared by adding an organic binder of ethyl cellulose and a terpineol solvent to a mixed powder of Ag 90% and Pd 10% is used. The wiring pattern 6 was printed.
高誘電率材料は、PbO、Fe2O3、Nb2O5、WO3、ZnOを所
定量秤量した後湿式粉砕し乾燥する。乾燥原料を850℃
で仮焼し、これに上記低誘電体材料で使用したガラス粉
末を所定量秤量し、添加する。湿式粉砕した後乾燥し
た。低誘電体グリーンシートと同様にしてドクターブレ
ード法を用いて100μm厚の高誘電率グリーンシート
5、9を作製した。このグリーンシートを40mm角に切断
した後、両面の相対する位置に前記導体ペースト4を使
用して8mm角の電極6を第3図に示した構造になるよう
にスクリーン印刷した。低誘電率グリーンシート1と高
誘電率グリーンシート5、9を積層後、100℃、100kg/c
m2で熱圧着した。また、図3に示すように、高誘電体層
9と低誘電率絶縁層1との間には、緩衝電極8が設けて
ある。緩衝電極8は、高誘電体層9の低誘電率絶縁層1
側表面を覆うように形成してある。通常の電気式バッチ
炉を使用して900℃、30分間酸化雰囲気焼成した。得ら
れた高誘電率材料の誘電率はεr=5000at 1KHz(25
℃)であった。High dielectric constant material, PbO, Fe 2 O 3, Nb 2 O 5, WO 3, is ZnO was wet pulverized by a predetermined amount weighed dry. 850 ° C for dry ingredients
Then, a predetermined amount of the glass powder used for the low dielectric material is weighed and added thereto. After wet pulverization, it was dried. High-dielectric-constant green sheets 5 and 9 having a thickness of 100 μm were prepared by the doctor blade method in the same manner as the low-dielectric green sheets. After this green sheet was cut into a 40 mm square, an 8 mm square electrode 6 was screen-printed using the conductive paste 4 at opposite positions on both sides so as to have the structure shown in FIG. After laminating low dielectric constant green sheet 1 and high dielectric constant green sheets 5 and 9, 100 ℃, 100kg / c
and thermo-compression bonding in m 2. Further, as shown in FIG. 3, a buffer electrode 8 is provided between the high dielectric layer 9 and the low dielectric constant insulating layer 1. The buffer electrode 8 is formed of the low dielectric constant insulating layer 1 of the high dielectric layer 9.
It is formed so as to cover the side surface. Firing in an oxidizing atmosphere was performed at 900 ° C. for 30 minutes using a normal electric batch furnace. The dielectric constant of the obtained high dielectric constant material is ε r = 5000 at 1 KHz (25
° C).
本実施例では高誘電率層をグリーンシート法によって
形成したが、スクリーン印刷等の誘電ペーストを印刷す
る方法によっても高誘電率層を形成することができる。In this embodiment, the high dielectric constant layer is formed by the green sheet method, but the high dielectric constant layer can be formed by a method of printing a dielectric paste such as screen printing.
比較例 実施例1と同様の構造を持ちガラス無添加の高誘電率
材料を使用して積層セラミック基板を作製した。得られ
た基板は熱膨張係数が異なるため生じる応力によって反
りの発生が見られた。Comparative Example A multilayer ceramic substrate having the same structure as in Example 1 and using a glass-free high dielectric constant material was produced. The resulting substrates were warped due to stress generated due to different thermal expansion coefficients.
ハ.発明の効果 以上の説明より明らかなように、本発明の積層回路セ
ラミック基板によれば、高誘電体層中に、該低誘電率絶
縁層に含まれる同一成分系のガラス成分を0.1〜1.0重量
%添加して両層の整合性を良好にし、また両層間に緩衝
電極を設けているので、両層の熱膨張係数の相違による
基板の反りを抑えることができ、また該緩衝電極によっ
て、前記低誘電率絶縁層から高誘電体層へのガラス成分
の移行を防止できるので、基板の誘電率の低下を防止で
きるという効果を有する。C. As is clear from the above description, according to the multilayer circuit ceramic substrate of the present invention, the same component glass component contained in the low dielectric constant insulating layer is contained in the high dielectric layer in an amount of 0.1 to 1.0% by weight. % To improve the consistency between the two layers, and since the buffer electrode is provided between the two layers, the warpage of the substrate due to the difference in the thermal expansion coefficient between the two layers can be suppressed. Since the migration of the glass component from the low dielectric constant insulating layer to the high dielectric layer can be prevented, a reduction in the dielectric constant of the substrate can be prevented.
このように、本発明の積層回路セラミック基板は、温
度特性を広範に制御でき併せて基板の反りを緩和でき、
しかも誘電率の低下を防止できるので、従来のものに比
べて信頼性の遥かに高い基板が得られその効果は極めて
大である。As described above, the multilayer circuit ceramic substrate of the present invention can control the temperature characteristics in a wide range and can reduce the warpage of the substrate.
Moreover, since a decrease in the dielectric constant can be prevented, a substrate having much higher reliability than that of the conventional substrate can be obtained, and the effect is extremely large.
第1図は、誘電率と温度に対する高誘電体層中へのガラ
スの添加量の関係を示す。 第2図は、誘電損失と温度に対する高誘電体層中へのガ
ラス添加量の関係を示す。 第3図は、本発明の焼成前の積層セラミック基板の断面
図を示す。 1……低誘電率グリーンシート、2……配線パターン、
3……スルーホール、4……導体ペースト、5及び9…
…高誘電率グリーンシート、6……内部電極、7……抵
抗体、8……緩衝電極FIG. 1 shows the relationship between the dielectric constant and the amount of glass added to the high dielectric layer with respect to temperature. FIG. 2 shows the relationship between the dielectric loss and the amount of glass added to the high dielectric layer with respect to temperature. FIG. 3 is a cross-sectional view of a multilayer ceramic substrate before firing according to the present invention. 1 ... low dielectric constant green sheet, 2 ... wiring pattern,
3 ... through-hole, 4 ... conductor paste, 5 and 9 ...
… High dielectric constant green sheet, 6… internal electrode, 7… resistor, 8… buffer electrode
Claims (2)
カイト系の誘電率が15を超える高誘電体層と誘電率が15
以下の低誘電率絶縁層を含み一体的に800〜1100℃で低
温同時焼成される基板において、該高誘電体層と低誘電
率絶縁層の間に緩衝電極を設け、また該高誘電体層中
に、該低誘電率絶縁層に含まれる同一成分系のガラス成
分を0.1〜1.0重量%添加したことを特徴とする積層回路
セラミック基板。1. A high-permittivity layer having a dielectric constant of more than 15 of a perovskite-based material containing lead oxide on a built-in or outer surface thereof and having a dielectric constant of 15 or more.
In a substrate including the following low dielectric constant insulating layer and co-fired at a low temperature at 800 to 1100 ° C. integrally, a buffer electrode is provided between the high dielectric layer and the low dielectric constant insulating layer, and the high dielectric layer A multilayer circuit ceramic substrate, wherein a glass component of the same component type contained in the low dielectric constant insulating layer is added in an amount of 0.1 to 1.0% by weight.
O3系である請求項1に記載の積層回路セラミック基板。2. The method according to claim 1, wherein said glass component is CaO--Al 2 O 3 --SiO 2 --B 2
The multilayer circuit ceramic substrate according to claim 1, which is an O 3 -based.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63331920A JP2652229B2 (en) | 1988-12-29 | 1988-12-29 | Multilayer circuit ceramic substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63331920A JP2652229B2 (en) | 1988-12-29 | 1988-12-29 | Multilayer circuit ceramic substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02178994A JPH02178994A (en) | 1990-07-11 |
JP2652229B2 true JP2652229B2 (en) | 1997-09-10 |
Family
ID=18249116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63331920A Expired - Lifetime JP2652229B2 (en) | 1988-12-29 | 1988-12-29 | Multilayer circuit ceramic substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2652229B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105916682B (en) | 2014-02-04 | 2018-06-22 | 日本碍子株式会社 | Laminated body, lamination device and their manufacturing method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5917227A (en) * | 1982-07-20 | 1984-01-28 | 日本電気株式会社 | Method of producing composite laminated ceramic part |
JPH0691322B2 (en) * | 1987-04-01 | 1994-11-14 | 松下電器産業株式会社 | Ceramic multilayer wiring board |
-
1988
- 1988-12-29 JP JP63331920A patent/JP2652229B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02178994A (en) | 1990-07-11 |
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