JP2632687B2 - Power semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] The present invention relates to an integrated power semiconductor device, and relates to an electrostatic induction control semiconductor element (static induction transistor or electrostatic induction thyristor) for high withstand voltage and driving of the semiconductor device. By integrating a low-voltage static induction transistor on the same semiconductor substrate as that of a conventional transistor, the switching speed can be remarkably increased as compared with the conventional one configured with bipolar transistors. is there.

[Industrial applications]

The present invention relates to a semiconductor integration technology, and more particularly to a power semiconductor device (power IC) incorporating a static induction transistor (hereinafter, referred to as SIT) or a static induction thyristor (hereinafter, referred to as SIThy). .

[Conventional technology]

As a conventional power IC, there is an IC configured with a bipolar transistor. As an example, a specific cross-sectional configuration is shown in FIG. 10, and a circuit configuration thereof is shown in a chain line in FIG.

In FIG. 10, an n ⁻ layer 2 is provided on an n ⁺ substrate 1 by epitaxial growth. On the other hand, a main high-voltage bipolar transistor (hereinafter referred to as BPT ₁ ) and a low voltage for driving the same are provided. Bipolar transistors (hereinafter referred to as BPT ₂ and BPT ₃ ) are built. BPT ₁ is, n ⁺ substrate 1, p region 3, n ⁺ region 4, respectively collector region, base region, np to the emitter region
It has an n-structure, and the n ⁻ layer 2 sandwiched between the n ⁺ substrate 1 and the p region 3 is thickened so that it can be used at a high voltage (between the collector and the emitter). Also, BPT ₂
And BPT ₃ are separated from each other by being formed in p-well regions 5 and 6, respectively.
N ⁺ regions 7,8 formed in 5,6, p regions 9,10, n ⁺ regions 11,1
It has an npn structure in which 2 is a collector region, a base region and an emitter region respectively. However, BPT ₂ and BPT
₃ represents n ⁻ regions 13 and 14 sandwiched between n ⁺ regions 7 and 8 and p regions 9 and 10
Is used for low voltage.

By appropriately forming an electrode 16 on the BPT ₁ , BPT ₂ , and BPT _{3 having the} above-described structure via an SiO ₂ film 15 having a contact hole formed therein, an IC circuit as shown in a dashed line in FIG. 11 is formed. Is obtained. When applying this to actual circuit, for example as shown in the figure, the collector C ₂ and BPT ₃ of BPT ₂
The Connect the power between the emitter E _3, the emitter E ₁ may be grounded further to connect the load L to the collector C ₁ side of the BPT _1. In this circuit, the BPT ₂ base B ₂ and BP
Respectively on the base B ₃ of T _3, by providing an electrical signal off, can the BPT ₁ of the main on, is turned off, thereby to drive the load L. Note that the above circuit operates even if BPT ₃ is omitted, but by connecting BPT ₃ , the main BPT ₁ can be turned off quickly.

[Problems to be solved by the invention]

Generally, bipolar transistors have low base sensitivity. Therefore, as described above, the bipolar transistor
Conventional power IC constructed in BPT ₁ ~BPT ₃ has a problem that the switching speed is low.

In view of the above problems, the present invention provides a power semiconductor device (power IC) capable of remarkably increasing a switching speed.
The purpose is to provide.

[Means for solving the problem]

The power semiconductor device of the present invention has a low-resistance (high-concentration) semiconductor substrate provided with a high-resistance (low-concentration) semiconductor layer on an upper surface. An electrostatic induction control semiconductor element (SIT or SIThy) for high withstand voltage is formed on this semiconductor substrate. In addition, at least one low-voltage SIT for driving the semiconductor element is formed in the well region in the semiconductor layer.

[Action]

In the present invention, SIT (SIThy) is used as described above. SIT (SIThy) has extremely high gate sensitivity as compared with a bipolar transistor, and storage time is essentially zero. Therefore, a circuit configured with such a SIT (SIThy) can perform a remarkably high-speed switching operation.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the present invention.

In the figure, a high-resistance n ⁻ layer is formed on a low-resistance n ⁺ substrate 21.
22 are epitaxially grown, in contrast to the main SIT for high pressure (hereinafter referred to as SIT ₁ ) and two SITs for driving the SIT for low voltage (hereinafter SIT ₂ and SIT _3).
) Is built.

In the region of SIT ₁ , a deep p ⁺ region 23 in the periphery of the n ⁻ layer 22 is diffused and formed, and n ⁺
The region 24 is formed by diffusion. Thereby, the n ⁺ substrate 21,
An n-channel SIT is formed using the p ⁺ region 23 and the n ⁺ region 24 as a drain region, a gate region, and a source region, respectively.
In this SIT ₁ , the n ⁻ layer 22 sandwiched between the n ⁺ substrate 21 and the p ⁺ region 23
By increasing the thickness, a high withstand voltage can be obtained between the drain and the source, and the peripheral portion of the p ⁺ region 23 is formed deep to form the guard ring 23a, thereby preventing a decrease in withstand voltage due to electric field concentration. it can.

On the other hand, in the left and right regions sandwiching SIT ₁ in the n ^- layer 22,
Well regions 25 and 26 are provided, in which S
IT ₂ and SIT ₃ are created and separated from each other. In the p well regions 25 and 26, via the n ⁺ regions 27 and 28 of the buried structure,
n ^- regions 29, 30 are provided, in which p ⁺ regions 31, 32 and n ⁺
Regions 33 and 34 are formed by diffusion. This gives n ⁺ region 2
Two SITs are constituted by a drain region, a gate region, and a source region, respectively, with 7, 28, p ⁺ regions 31, 32, and n ⁺ regions 33, 34. In these SIT ₂ and SIT ₃ , the n ⁺ regions 27, 28 and p ⁺
The thickness of the n ⁺ region 29 sandwiched between the regions 31 and 32 is thin, and thus can be used for low voltage.

On the SIT ₁ , SIT ₂ and SIT ₃ having the above configuration, an electrode 36 such as Al is interposed via a SiO ₂ film 35 having a contact hole formed therein.
There by being arranged appropriately, the SIT ₁ p ⁺ region of the (gate region) 23 and SIT ₂ n ⁺ region (source region) 33 and SIT ₃ n ⁺
The region (drain region) 28 is connected to each other. As a result, an IC circuit as shown in the alternate long and short dash line in FIG. 2 is obtained. When applying this to actual circuit, for example as shown in the figure, and connect the power between the source S ₃ of the drain D ₂ and SIT ₃ of SIT _2, additionally to the drain D ₁ side of the SIT ₁ it may be grounded source S ₁ while connecting the load L.

The circuit operation of FIG. 2 will be described with reference to FIG.
Suppose now that SIT ₁ is off. Here, when an ON signal is applied to the gate G ₂ of SIT ₂ as shown in FIG.
SIT ₂ turns on, and accordingly, the potential of the gate G ₁ of SIT ₁ becomes the third
SIT ₁ is turned on because it rises as shown in FIG. Thus, the drain D ₁ is grounded as a third diagram (d),
A current flows through the load L. To keep SIT ₁ on, keep SIT ₂ on for that time. Next, the gate of SIT ₂
Turn-on signal has been added to G _2, the addition of this off signal, as shown in the gate G ₃ of SIT ₃ in FIG. 3 (b) At the same time, since the SIT ₃ is turned SIT ₂ is turned off, potential of SIT ₁ gate G ₁ is lowered as FIG. 3 (c), SIT ₁ is turned off. Thus, increases the potential of the drain D ₁ again as in the third diagram (d), the current flowing through the load L is stopped.

Next, a brief description will be given of a manufacturing method for obtaining the configuration shown in the first appendix.

First, an n ⁻ substrate is formed on an n ⁺ substrate 21 made of silicon single crystal or the like.
The lower layer portion of n ⁻ layer 22 is formed by performing epitaxial growth of. On the other hand, by applying p ⁺ diffusion, p
It forms the bottom of the well region 25, subjected to 6 ⁺ diffusion for the further n ⁺ region over the 27, 28. By performing n ⁻ epitaxial growth from above, an upper layer portion of n ⁻ layer 22 and n ⁻ regions 29 and 30 are formed (however, at this point, n ⁻
Layer 22 and n ^- regions 29, 30 are not separated from each other). At this time, the n ⁺ region 2 of the buried structure is formed by auto doping.
7,28 is obtained.

Next, by performing deep p ⁺ diffusion on the n ⁻ layer 22 and the n ⁻ regions 29 and 30, the periphery (guard ring) of the p ⁺ region 23 is
23a) and the peripheral portions of the p-well regions 25 and 26 are simultaneously formed (at this point, the n ⁻ layer 22 and the n ⁻ regions 29 and 30 are separated from each other). Furthermore, for the n ⁻ regions 29 and 30, the embedded n ⁺ region 2
Perform deep n ⁺ diffusion to reach 7,28. Then n ^- layer
22 and the n ^- to regions 29 and 30 is subjected to a p ⁺ diffusion p ⁺ region 23
And p ⁺ regions 31 and 32 are simultaneously formed, and then n ⁺ diffusion is performed to simultaneously form n ⁺ regions 24 and n ⁺ regions 33 and 34.

When the structure of the semiconductor is obtained as described above, the SiO ₂ film 35 used as the mask for n ⁺ diffusion is left on the upper surface as it is, and a contact hole for forming an electrode is formed in the SiO ₂ film 35. Thereafter, a metal film such as Al is deposited on the SiO ₂ film 35, and the electrode 36 is formed by patterning the metal film. Finally, the entire surface is covered with a passivation film or the like except for a predetermined bonding pad region on the electrode 36.

As described above, all three SITs have n channels,
These respective gate regions and source regions can be formed at the same time, resulting in a very simple manufacturing process.

In this embodiment, as described above, the main SIT ₁ and two SITs ₂ and ₃ for driving the main SIT ₁ are integrated. SITs generally have extremely high gate sensitivity compared to bipolar transistors, and storage time is essentially zero. Therefore, the circuit of the present embodiment configured with such an SIT can realize a remarkably high speed switching operation. For example, the switching speed can be improved by one to two digits compared to a conventional circuit including bipolar transistors. In the circuit of FIG. 2, even if SIT ₃ is not provided,
Although SIT ₁ operates, using SIT ₃ has the advantage that SIT ₁ can be turned off more quickly.

Next, FIG. 4 shows a sectional configuration of a second embodiment of the present invention.

In the present embodiment, the configuration of SIT ₁ and SIT ₂ is the same as that of FIG. 1, but a p-channel SIT is used as SIT ₃ . This SIT ₃ has p ^- region 41 in p-well region 26.
And the n ⁺ region 42 and the p ⁺ region 43 are diffused and formed therein. The drain region, the gate region, and the source region are formed from the p well region 26, the n ⁺ region 42, and the p ⁺ region 43, respectively. The p ⁺ region (source region) 43 is
It is connected to the p ⁺ region (gate region) 23 of the T _1.

With the above configuration, the IC as shown in the dashed line in FIG.
A circuit is obtained. According to the present embodiment, n-channel SIT ₂
By using the SIT ₃ and the p-channel SIT ₃ , the lines of the input signals to the gates G ₂ and G ₃ can be unified as shown in FIG. In the circuit of FIG. 5, one was applied to the gate G ₃ of the gate G ₂ and SIT ₃ of SIT _2, in accordance with the OFF signal (Figure 6 (a)), the potential of the gate G ₁ of SIT ₁ moves up and down (FIG. 6 (b)), whereby SIT ₁ is turned on and off (FIG. 6 (c)).

Since this embodiment is also all composed of SITs, high-speed operation becomes possible as in the first embodiment. Moreover,
Since the input line can be unified, the input circuit can be simplified.

Next, FIG. 7 shows a sectional configuration of a third embodiment of the present invention.

In this embodiment, SIThy ₁ is formed in place of SIT 1 in FIG. ₁ , and a p ⁺ substrate 51 is used instead of the n ⁺ substrate 21. Other configurations are the same. In this case, the p ⁺ substrate
51, the p ⁺ region 23, and the n ⁺ region 24 become the anode region, the gate region, and the cathode region of SIThy ₁ , respectively.

With the above configuration, the IC as shown in the dashed line in FIG.
A circuit is obtained. In such a circuit, by adding to the gate G ₂ of the SIT ₂ ON signal (FIG. 9 (a)) the trigger signal is input to the gate G ₁ of SIThy ₁ (Figure 9 (c)), This turns on SIThy ₁ (FIG. 9 (d)). On the other hand, the addition of ON signal to the gate G ₃ of SIT ₃ (FIG. 9 (b)), is input quench signal to the gate G ₁ of the SIThy (FIG. 9 (c)), thereby SIThy ₁ is turned off (FIG. 9 (d)).

According to the present embodiment, by using SIThy ₁ as the main element, the pulse width of the ON signal can be shortened as shown in FIG.
y ₁ keeps on. In addition, SIThy has a current capacity per area of at least twice that of SIT. From these, compared with the first and second embodiments using the SIT _1, it requires less power consumption. Further, since SIThy also has extremely high gate sensitivity like SIT, high-speed operation becomes possible as in the above-described embodiment. In addition, by using the p-channel SIT ₃ as shown in FIG. 4, the input line can be similarly unified.

In each of the above embodiments, SIT ₂ and SIT ₃ are used as normal SITs that are turned on and off by electric signals, but are used as phototransistors that are turned on and off by optical signals instead of such electric signals. You may. In this case, the electrodes must be
If it is made of an opaque substance such as Al,
Alternatively, a transparent conductive material such as SnO ₂ is used for the electrode. The timing of the input signal is the same as that of the electric signal described above. If an optical signal is input in this manner, the input circuit and the drive circuit are electrically separated, which is advantageous in terms of noise resistance and surge resistance. Further, since the optical sensitivity of the SIT is higher than that of the bipolar transistor by three orders of magnitude or more, the SIT can be operated with an extremely small optical signal.

In each of the above embodiments, the n-type and the p-type may be formed in exactly the opposite manner.

〔The invention's effect〕

As described above, according to the power semiconductor device of the present invention, extremely high-speed switching operation can be realized by using SIT (SIThy) having extremely high gate sensitivity as compared with the bipolar transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a circuit configuration of the first embodiment, and FIGS. 3 (a) to 3 (d) show operations in the circuit of FIG. FIG. 4 is a cross-sectional configuration diagram of a second embodiment of the present invention, FIG. 5 is a circuit diagram showing a circuit configuration of the second embodiment, and FIGS. 6 (a) to (c) are diagrams of FIG. 5 is a time chart showing the operation of the circuit shown in FIG. 5, FIG. 7 is a cross-sectional configuration diagram of a third embodiment of the present invention, FIG. 8 is a circuit diagram showing a circuit configuration of the third embodiment, and FIG. To (d) are time charts showing the operation of the circuit of FIG. 8, FIG. 10 is a cross-sectional configuration diagram of a conventional power semiconductor device (power IC), and FIG. 11 is a circuit diagram showing the circuit configuration of the conventional device. FIG. 21 ... n ⁺ substrate (drain region), 22 ... n ^- layer, 23 ... p ⁺ region (gate region), 24 ... n ⁺ region (source region, cathode region), 25, 26 ... p well Region, 27,28 ... n ⁺ region (drain region), 29,30 ... n ^- region, 31,32 ... P ⁺ region (gate region), 33,34 ... n ⁺ region (source region), 35: SiO ₂ film, 36: Electrode, 41: P ^- region, 42: n ⁺ region (gate region), 43: P ⁺ region (source region), 51: P ⁺ region (anode region) ), SIT ₁ , SIT ₂ , SIT ₃ …… Electrostatic induction transistor, SIThy ₁ …… Electrostatic induction thyristor.

Claims (8)

(57) [Claims] 1. A low-resistance semiconductor substrate having a high-resistance semiconductor layer on an upper surface thereof has a guard ring in which an upper surface and a lower surface of the semiconductor substrate are used as main electrodes and a gate region is formed deep in the substrate. At least one low voltage electrostatic induction transistor for forming a vertical electrostatic induction control semiconductor element for high withstand voltage and for driving the semiconductor element in a well region provided in the semiconductor layer A power semiconductor device characterized by comprising: 2. The power semiconductor device according to claim 1, wherein said semiconductor layer is an epitaxial layer. 3. The semiconductor device according to claim 2, wherein the static induction control transistor is turned on by the two transistors.
3. The power semiconductor device according to claim 1, wherein the power semiconductor device is turned off. 4. The device according to claim 3, wherein said two static induction transistors have channels of the same conductivity type as each other and have separate input lines from each other.
Item 7. A power semiconductor device according to Item 1. 5. The power semiconductor device according to claim 3, wherein said two static induction transistors have channels of different conductivity types and have input lines unified with each other. 6. The power semiconductor device according to claim 1, wherein said electrostatic induction transistor is a phototransistor which is turned on / off by an optical signal. 7. The semiconductor device according to claim 1, wherein said electrostatic induction control semiconductor device is an electrostatic induction transistor.
Item 7. A power semiconductor device according to any one of Items 6 to 6. 8. The power semiconductor device according to claim 1, wherein said electrostatic induction control semiconductor element is an electrostatic induction thyristor.