JP3278534B2 - MOS gate type power semiconductor device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS gate type power semiconductor device in which a main current is controlled by a MOS structure, and a driving device therefor.
On how to move .

[0002]

2. Description of the Related Art There are a voltage control type and a current drive type for a gate drive in a power device having a high withstand voltage and a large current. The former is more preferable. This is because the voltage control type can perform gate drive with a smaller current than the current drive type.

FIG. 29 is a sectional view showing the element structure of a conventional MOS gate thyristor. In this thyristor, a p-type base layer 702 is formed on the surface of a high-resistance first conductivity type base layer 701, and an n-type emitter layer 703 is selectively formed in the p-type base layer 702. On the back surface of the n-type base layer 701, a high-concentration p-type emitter layer 704 is formed. A cathode electrode 7055 is provided on the n-type emitter layer 703, and an anode electrode 706 is provided on the p-type emitter layer 704.

The n-type emitter layer 7 in the p-type base layer 702
03 at a predetermined distance from the n-type drain layer 707.
Are formed. On the p-type base layer 702 between the n-type drain layer 707 and the n-type emitter layer 703, a gate electrode 710 is provided via a gate insulating film 709. The gate electrode 710 is for turning off, and an n-channel MOSFET having the n-type emitter layer 703 as a source is configured. Note that the drain electrode 708 in contact with the n-type drain layer 707 is also in contact with the p-type base layer 702, and the p-type base layer 702 and the n-type drain layer 707 are short-circuited by the drain electrode 708.

Although a gate electrode for turn-on is not shown in the drawing, it is formed, for example, in the periphery of a p-type base layer 702 which is selectively diffused and formed, with a MOS structure as in the case of turn-off.

In order to turn off the MOS gate thyristor having such a structure, a positive voltage is applied to the gate electrode 710 with respect to the cathode. As a result, an n-channel is formed below the gate electrode 710 and the p-type base layer 70 is formed.
2, a part of the hole current directly flowing into the n-type emitter layer 703 from the drain electrode 7
08, passes through the n-type drain layer 707, passes through the n-channel below the gate electrode 710, and bypasses from the n-type emitter layer 703 to the cathode electrode 705. Eventually, the bypass of the hole current will cause n
The injection of electrons from the p-type base layer 702 from the p-type emitter layer 703 stops, and the thyristor turns off.

However, the conventional MOS gate type thyristor has a problem that a sufficient turn-off capability cannot be obtained. This is due to the resistance of the hole current bypass path indicated by the broken line in FIG.

That is, the resistance of the hole current bypass path mainly depends on the lateral resistance of the p-type base layer 702 and the MOS resistance.
This is the on-resistance of the n-channel below the gate electrode 710. When the voltage drop determined by these resistances and the bypass current becomes equal to or higher than the built-in voltage of the n-type emitter layer 703 and the p-type base layer 702, the n-type emitter layer 703 Electron injection will not stop. Therefore, when the anode current (main current) becomes large, it becomes impossible to turn off.

FIG. 59 is a sectional view showing a structure of a conventional MOS gate type power semiconductor device (MCT). (IE
DM89, p. 297-300, "Design As
figures of MOS Controlled T
Hyster element "), 100 in the figure
Reference numeral 1 denotes a high-concentration p-type emitter layer, which is in contact with the p-type emitter layer 1001 and has a low-concentration n-type base layer 100.
2 are formed. On the surface of the n-type base layer 1002, a p-type base layer 1003 is selectively formed.
A high concentration n-type emitter layer 1004 is selectively diffused on the surface of the mold base layer 1003.

An anode electrode 1005 is provided on the p-type emitter layer 1001, and a cathode electrode 1006 is provided on the n-type emitter layer 1004.

A high-concentration p-type source layer 1007 is selectively formed on the surface of n-type emitter layer 1004, and p-type base layer 1003 in a region sandwiched between p-type source layer 1007 and n-type base layer 1002. And n-type emitter layer 1
On 004, a gate electrode 1013 is formed via a gate insulating film 1012, and a turn-off p-channel MISFET having the region CH1 as a channel region is formed.

The p-type source layer 1007 is a cathode electrode 10
06 is short-circuited with the n-emitter layer 1004.
In addition, the gate electrode 1013 is an n-type emitter layer 1004
And a gate electrode of a turn-on n-channel MISFET composed of the p-type base layer 1003 and the n-type base layer 1002.

The operation of this device (MCT) is as follows.

At turn-on, a positive voltage is applied to the gate electrode 1013 with respect to the cathode. As a result, the channel region CH2 below the gate electrode 1013 becomes conductive, and the n-type emitter layer 1004 moves from the n-type base layer 100
Electrons are injected into 2 to turn on the device.

On the other hand, at the time of turn-off, the gate electrode 101
3, a negative voltage is applied. Thereby, the gate electrode 1
The channel region CH1 below the channel region 013 becomes conductive, and part of the hole current flowing directly from the p-type base layer 1003 to the n-type emitter layer 1004 is changed to the p-type source layer 1007.
From the cathode electrode 1006.
By the hole current bypass, electron injection from the n-type emitter layer 1004 to the p-type base layer 1003 eventually stops, and the device is turned off.

However, such a conventional MCT has a problem that a sufficient turn-off capability cannot be obtained.

This is based on the following reasons.

The turn-off capability of the n-type emitter layer 100
4 and the pn of the emitter junction composed of the p-type base layer 1003
It largely depends on the junction potential (built-in voltage). Therefore, at the time of turn-off, the n-type emitter layer 10
When the voltage drop due to the hole bypass current immediately below the voltage V.04 exceeds the emitter junction potential of 0.7 V (in the case of silicon), n
Electron injection from the mold emitter layer 1004 does not stop and remains in a latch-up state, making gate control impossible and leading to destruction.

Here, assuming that the proportional coefficient is α, the resistance of the hole current bypass path is Rp, and the base-cathode breakdown voltage is V _BK , the maximum turn-off current I _TGQM of the _device is I _TGQM = α (V _BK / _{rp) (1) V BK =} V J = 0.7 (V) becomes (2).

Here, the hole current bypass path Rp is mainly a lateral resistance of the p-type base layer 1003 and a channel resistance immediately below the insulated gate electrode 1013. By reducing these resistances, the I _TGQM can be improved. It is possible to plan.

However, since their resistance depends on the width of the n-type emitter layer 1004 and the width of the gate electrode 1013, miniaturization of the structure is indispensable, but it is extremely difficult. Therefore, sufficient turn-off capability has not been obtained with the conventional MCT.

[0022]

As described above, the conventional M
In the OS gate type thyristor, when the main current becomes large, there is a problem that the voltage drop caused by the bypass path resistance and the bypass current makes it impossible to stop the electron injection from the n-type emitter layer and to make it impossible to turn off.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a MOS gate type power semiconductor device having a superior turn-off capability and a drive device therefor.
It is to provide a moving method .

[0024]

To achieve the above object, a MOS gate type power semiconductor device of the present invention (Claim 1) is in direct or indirect contact with the surface of a first conductivity type base layer. A second conductivity type emitter layer, a second conductivity type base layer selectively formed on the surface of the n base layer opposite to the second conductivity type emitter layer, and a second conductivity type base layer on the surface of the second conductivity type base layer. A first conductivity type emitter layer selectively formed, a first conductivity type source layer selectively formed on a surface of the second conductivity type base layer, the first conductivity type emitter layer, and the first conductivity type; A first conductivity type drain layer selectively formed on a surface of the second conductivity type base layer between the first conductivity type base layer and the first conductivity type base layer and the first conductivity type emitter layer; Over the second conductivity type base layer via a first gate insulating film. And a second gate insulating film interposed between the first gate electrode and the second conductive type base layer sandwiched between the first conductive type drain layer and the first conductive type source layer. The second gate electrode and the second
A first main electrode provided on the conductive type emitter layer; a second main electrode provided on the first conductive type emitter layer; and a second main electrode provided on the second conductive type base layer and the first conductive type drain layer. And a source electrode provided on the first conductivity type source layer and connected to the second main electrode, wherein the first conductivity type emitter layer surrounds the first gate electrode. And the second main electrode is formed, and the first conductivity type drain layer and the drain electrode are formed so as to surround the first conductivity type emitter layer and the second main electrode. The second gate electrode is formed so as to surround a layer and the drain electrode, and the first conductivity type source layer and the source electrode are formed so as to surround the second gate electrode. And butterflies.

[0025] Another MOS gate type power semiconductor device of the present invention (claim 2) is a first conductivity type base layer and a first conductive type base layer.
Directly or indirectly against the surface of the conductive base layer, the first
A second conductivity type emitter layer provided with a main electrode of
The first conductivity type base layer opposite to the two conductivity type emitter layer
A second conductivity type base layer selectively formed on the surface of
Of the first conductive type selectively formed on the surface of the second conductive type base layer.
Conductive emitter layer and surface of first conductive emitter layer
Second conductive layer selectively formed on the substrate and provided with a source electrode
Source layer, the second conductive type source layer and the first conductive type.
The second conductivity type base layer sandwiched between the mold base layer and
On the first conductivity type emitter layer via a gate insulating film
A gate electrode provided and a first conductive type emitter layer.
A second electrode selectively formed on the surface and connected to the source electrode;
And a first conductive type resistance semiconductor layer provided with two main electrodes . Another MOS gate type power semiconductor device of the present invention (Claim 3) is that a first conductive type base layer and a surface of the first conductive type base layer are directly or interposed on the first conductive type base layer.
A second conductivity type emitter that is in direct contact with the first main electrode.
And the second conductive type emitter layer.
Second conductivity selectively formed on the surface of one conductivity type base layer
Selectively on the surface of the base layer and the second conductive type base layer.
And a first conductivity type emitter provided with a second main electrode.
Selectively on the surface of the first conductive type emitter layer.
And a source electrode connected to the second main electrode.
A second conductivity type source layer, and a second conductivity type source layer.
The second conductive layer sandwiched between a layer and the first conductive type base layer
A gate is formed on the base layer and the emitter layer of the first conductivity type.
A gate electrode provided through a gate insulating film;
A second conductive type half selectively formed on the surface of the conductive type base layer
A conductive layer, the second conductive type semiconductor layer,
A first contact electrode connected to the second main electrode;
A second conductive type semiconductor layer connected to the source electrode;
And a second contact electrode .

[0026]

According to the present invention (claim 1), at the time of turn-off, a voltage of a predetermined level is applied to the second gate electrode,
If a channel is formed on the surface of the second conductive type base layer below the second gate electrode, the carriers in the device having the same polarity as the majority carrier of the second conductive type emitter layer will be the first conductive type base layer and the second conductive type base layer. The gas is discharged out of the device through a bypass path including a two-conductivity type base layer, a drain electrode, a first conductivity type drain layer, the channel, the first conductivity type source layer, and a source electrode. Therefore, the lateral resistance of the second conductivity type base layer in the bypass path is reduced as compared with the related art.

Further, a MOS composed of a first conductivity type drain layer, a first conductivity type source layer, a second gate electrode 10 and the like.
Since the FET is formed so as to surround the first conductivity type emitter layer, its channel width becomes wider than before,
Channel resistance at turn-off is reduced.

Therefore, according to the present invention, the resistance of the bypass path and the channel resistance can be reduced, and the turn-off characteristics can be greatly improved.

According to the present invention (claim 2 ), the first
The first conductive type pseudo-resistive semiconductor layer formed on the surface of the conductive type emitter layer causes a resistor to be present between the first conductive type emitter layer and the second main electrode. The potential of the one conductivity type emitter layer increases.

As a result, at the time of turn-off, the lateral resistance of the second conductivity type base layer immediately below the first conductivity type emitter layer and
Even if the voltage drop due to the majority current of the same layer and the bypass current of the carrier having the same polarity exceeds the built-in voltage between the first conductivity type emitter layer and the second conductivity type base layer, the level of the level exceeding the built-in voltage is not exceeded. The injection of carriers having the same polarity as the majority carrier in the first conductivity type emitter layer can be stopped within the potential rise due to the first conductivity type pseudo-resistance semiconductor layer.

Therefore, according to the present invention, a sufficient turn-off capability can be obtained without miniaturizing the element.

According to the present invention (claim 3 ), the first
Carriers having the same polarity as the majority carrier of the second conductivity type emitter layer flow through the path of the conductivity type emitter layer, the second main electrode, the first contact electrode, and the second conductivity type semiconductor layer. The potential of the conductive type emitter layer increases.

Therefore, according to the present invention, as in the case of the present invention (claim 2 ), a sufficient turn-off capability can be obtained without miniaturizing the element.

[0034]

Embodiments will be described below with reference to the drawings.

FIG. 1 shows an MO according to a first embodiment of the present invention.
FIG. 2 is a plan view of the S-gate thyristor, and FIG.
It is A 'sectional drawing.

In the drawing, reference numeral 101 denotes a high-resistance n-type base layer. On the surface of the n-type base layer 101, a p-type base layer 102 is selectively formed. On the surface of the p-type base layer 102, a high-concentration n-type emitter layer 103 is selectively formed.

A gate electrode 124 is formed on the p-type base layer 102 between the n-type emitter layer 103 and the n-type base layer 101 with a gate insulating film 123 interposed therebetween. A turn-on MOSFET is formed by the n-type emitter layer 103 and the like.

On the surface of the p-type base layer 102, a high-concentration n-type drain layer 107 is selectively formed.
A drain electrode 108 is provided on the n-type drain layer 107.
7 and the p-type base layer 102. That is, the n-type drain layer 107 is
08 is short-circuited with the p-type base layer 102.

A high-concentration n-type source layer 111 is selectively formed on the surface of the p-type base layer 102 at a predetermined distance from the n-type drain layer 107. On the p-type base layer 2 between the n-type source layer 111 and the n-drain layer 107, the gate electrode 1
10 are provided.

The source electrode 112 provided on the n-type source layer 111 is formed integrally with the cathode electrode 105, that is, is electrically connected to the cathode electrode 105. The source electrode 112 is connected to the drain electrode 10
Like FIG. 8, the p-type base layer 102 is provided so as to be in contact with the p-type base layer 102 at the same time. Note that the source electrode 112 may be provided so as to contact only the n-type source layer 111.

The gate electrode 110 and the n-type drain layer 1
07, MO for turn-off by n-type source layer 111, etc.
An SFET is formed and this turn-off MOSFET
Has a structure surrounding the n-type emitter layer 103 as shown in FIG.

That is, n-type emitter layer 103 and cathode electrode 105 are formed so as to surround gate electrode 124, and n-type emitter layer 103 and cathode electrode 1 are formed.
The n-type drain layer 107 and the drain electrode 108 are formed so as to surround the n-type drain layer 107 and the gate electrode 11 so as to surround the n-type drain layer 107 and the drain electrode 108.
0 is formed, and an n-type source layer 111 and a source electrode 112 are formed so as to surround the gate electrode 110.

On the other hand, on the back surface of the n-type base layer 101, a high-concentration p-type emitter layer 104 is formed.
An anode electrode 106 is provided on the mold emitter layer 104. Note that instead of forming the p-type emitter layer 104 directly in contact with the n-type base layer 101, the n-type base layer 10
An n-type buffer layer may be provided between 1 and the p-type emitter layer 104, and the p-type emitter layer 104 in indirect contact with the n-type base layer 101 may be formed.

The MOS gate type thyristor of this embodiment is
By the gate driving method according to the time chart shown in FIG. 3, the turn-off current can be increased as compared with the conventional case.

[0045] That is, in order to turn-on MOSFET is in the ON state, after applying a positive voltage relative to the cathode to the gate electrode 124 (G1), relative to the cathode to the gate electrode 110 (G2) after a time Delta] t ₁ Apply a positive voltage. Note that a positive voltage may be applied to the gate electrode 124 of the turn-on MOSFET from turn-on to turn-off.

In FIG. 2, the electron current when the gate electrode 110 is turned on is shown by a solid line, and the bypass path of the hole current is shown by a broken line. As shown in the figure, the hole current is sucked into the drain electrode 108 in the immediate vicinity of the n-type emitter layer 103, and is discharged from the source electrode 112 to the outside of the device through the n-channel below the gate electrode 110.

Since the path of such a current is the same as that of the IGBT, after a positive voltage is applied to the gate electrode 110, after a certain time (after Δt ₂ ), the turn-on MOS transistor is turned on.
When the FET is turned off, the injection of electrons is stopped and the device is turned off.

According to such a gate driving method, the flow of the electron current at the time of turn-off can be made uniform, so that the turn-off current is reduced due to the reduction of the conduction region of the electron current as compared with the conventional gate driving method. Is much less.

Further, in the case of the MOS gate type thyristor of this embodiment, unlike the conventional case of FIG. 29, the lateral resistance of the p-type base layer 102 of the off MOSFET is provided in the bypass path of the hole current. Do not fit.

Further, the turn-off MOSFET is n
Since it is formed so as to surround the mold emitter layer 103, the channel width becomes larger than before, and the channel resistance at the time of turn-off becomes sufficiently small.

Therefore, according to the present embodiment, it is possible to obtain a larger turn-off current than in the prior art.

FIG. 4 shows the n-type source layer 111 of this embodiment.
4A and 4B are a plan view and a cross-sectional view illustrating the relationship between the source electrode 112 and the p-type base layer 102, respectively. As shown in FIG. 4, the source electrode 112 has a p-type base layer 102 in all regions.
(N-type source layer 111).

The n-type source layer 111, the source electrode 112,
The relationship with the p-type base layer 102 may be as follows. That is, as shown in FIG.
2 may be short-circuited to the p-type base layer 1022 only in a part of the region. In FIG. 5, the cross-sectional view taken along the line AA ′ is the same as that in FIG.

As described above, the operation of the MOS gate thyristor of the present invention is the same even if the source electrode is completely or partially short-circuited to the p-type base layer.

This embodiment may be modified as follows. That is, as shown in FIG. 1, in the present embodiment,
A drain electrode 108 is disposed inside the source electrode 112, and the cathode electrode 11 is disposed inside the drain electrode 108.
5, but instead of the source electrode 112
And the cathode electrode 105 may be connected by two-layer Al, or a part of the drain electrode 108 may be cut and wired.

In the case where two gate electrodes are provided as in this embodiment, it is complicated to drive them separately. The following inventions that solve this point (second to fifth aspects)
Example).

First, the above problem will be described in more detail.

FIG. 30 is a sectional view showing the element structure of a conventional lateral MOS gate type thyristor.

In the figure, 801 is a silicon substrate, 802 is a silicon oxide film, 803 is an n-type base layer, 804 is a p-type base layer, 805 is an n-type buffer layer, 806 is a p-type emitter layer, and 807 is an n-type emitter. 819 denotes an n-type source layer, and 820 denotes an n-type drain layer.

The p-type emitter layer 806 has an anode electrode 8
14 is a cathode electrode 816 on the n-type emitter layer 807.
However, a drain electrode 815 connected to a cathode electrode 816 is provided on the n-type drain layer 820.

On the surfaces of n-type base layer 803 and n-type buffer layer 805, a field oxide film 809 is formed. The gate insulating film 8 is formed on the p-type base layer 804 sandwiched between the n-type base layer 803 and the n-type emitter layer 807.
A turn-on MOS gate electrode 811 is provided via the reference numeral 10.

The n-type drain layer 820 and the n-type source layer 81
9 on the p-type base layer 804 sandwiched between the turn-off MOS gate electrode 81 and the gate insulating film 812.
3 are provided. Also, the p-type base layer 804 is n
It is short-circuited by the mold source layer 819 and the floating electrode 818.

In the lateral MOS gate thyristor thus configured, the turn-on MOS gate electrode 8
When a positive voltage is applied to the n-type emitter layer 11, the n-type emitter layer 807 is short-circuited to the n-type base layer 803 via the n-channel formed on the surface of the p-type base layer 804 below the turn-on MOS gate electrode 811, Electrons are injected into the mold base layer 803. Then, a corresponding amount of holes is injected from the p-type emitter layer 806 into the n-type base layer 803, and as a result, the thyristor is turned on.

When the lateral MOS gate thyristor is turned off, it is turned off by a gate driving method according to a time chart relating to the gate voltage, the device current, and the device voltage as shown in FIG.

That is, after a positive voltage is applied to the turn-on MOS gate electrode 811 to turn it on, the time t
One hour later, a positive voltage is also applied to the turn-off MOS gate electrode 813. The turn-on MOS gate electrode 8
In step 11, a positive voltage may be kept applied from turn-on to turn-off.

In FIG. 30, an electron current when the turn-off MOS gate electrode 813 is turned on is indicated by a solid line, and a hole current bypass path is indicated by a broken line. The hole current in the n-type emitter layer 807 is sucked out from the floating electrode 818 as shown in FIG.
The light is discharged from the drain electrode 815 to the outside of the device through a channel below the OS gate electrode 813.

Such a current path is a so-called IG
It is the same as in the case of BT. Therefore, turn-off M
After applying a positive voltage to the OS gate electrode 813, after a certain time (after t2), the turn-on MOS gate electrode 81
When the applied voltage is reduced to 1, the injection of electrons stops and the element turns off.

However, the conventional lateral MOS gate type thyristor has a problem that two gate electrodes are required at the time of turn-off, and the control of the gate voltage becomes complicated.

Therefore, an invention which takes into account such circumstances and aims at obtaining a MOS gate type power semiconductor element which can be easily turned off will be described below.

The gist of the present invention is that a second conductive type emitter layer which is in direct or indirect contact with the first conductive type base layer, and a second conductive type selectively formed on the surface of the first conductive type base layer.
A conductive type base layer; a first conductive type emitter layer selectively formed on the surface of the second conductive type base layer; and a surface of the first conductive type emitter layer or the first conductive type base layer. A first gate is formed on a second conductivity type drain layer selectively formed on the surface and on the second conductivity type base layer sandwiched between the first conductivity type base layer and the first conductivity type emitter layer. A first gate electrode provided via an insulating film;
The first conductivity type emitter layer or the first conductivity type emitter layer sandwiched between the second conductivity type base layer and the second conductivity type drain layer.
A second gate electrode provided on the conductive type base layer via a second gate insulating film and connected to the first gate electrode; and a first gate electrode provided on the second conductive type emitter layer. And a second electrode provided on the first conductivity type emitter layer.
And a drain electrode provided on the second conductivity type drain layer and connected to the second main electrode, wherein the first conductivity type emitter layer and the second conductivity type base layer are provided. A first conductivity type channel MOSFET including the first conductivity type base layer, the first gate insulating film and the first gate electrode, and the second conductivity type drain layer, the first conductivity type base layer, or At least one of a second conductivity type channel MOSFET including the first conductivity type emitter layer, the second conductivity type base layer, the second gate insulating film, and the second gate electrode is a normally-on type, and The threshold voltage of the first conductivity type channel MOSFET is lower than that of the second conductivity type MOSFET.

According to such an invention, since the first gate electrode of the first conductivity type channel MOSFET and the second gate electrode of the first conductivity type channel MOSFET are connected, the gate electrode is substantially formed. It becomes one, and the on / off operation of the element becomes easy to control.

Specifically, in order to make the steady-state OFF state, a first voltage is applied to the first and second gate electrodes, and only the second conductivity type channel MOSFET is made conductive. In order to turn on, a second voltage is applied to the first and second gate electrodes, and only the first conductivity type channel MOSFET is turned on.

To turn off the semiconductor device, a third voltage is applied to the first and second gate electrodes, so that the first conductive type channel MOSFET and the second conductive type channel are also non-F.
After the ET is made conductive, a first voltage is applied to make only the second conductivity type channel MOSFET conductive.

FIG. 6 is a sectional view showing the structure of a lateral MOS gate thyristor according to a second embodiment of the present invention.

In the figure, reference numeral 201 denotes a silicon substrate, on which a silicon oxide film 2 is formed.
A high-resistance n-type base layer 203 is formed via the gate electrode 02, and a p-type base layer 204 and an n-type buffer layer 205 are selectively formed on the surface of the n-type base layer 203. The surface of the n-type buffer layer 205 has a high concentration of p
The mold emitter layer 206 is selectively formed. Also,
On the surface of the p-type base layer 204, a high-concentration n-type emitter layer 207 is selectively formed.
7, n-type base layer 203, p-type base layer 204 and p-type base layer
Type thyristor pn
A pn structure is configured.

An n which is a predetermined distance away from the p-type base layer 204
On the surface of the mold base layer 203, a p-type drain layer 208 is selectively formed. The first gate electrode 2 is formed on the p-type base layer 204 between the n-type base layer 203 and the n-type emitter layer 207 via the first gate insulating film 212.
13 are provided.

That is, the n-type base layer 203, the n-type emitter layer 207, the p-type base layer 204, the gate insulating film 21
2 and the gate electrode 213 form an n-type MOSFET.

On the n-type base layer 203 between the p-type base layer 204 and the p-type drain layer 208, a first gate electrode 213 is connected via a second gate insulating film 210. A second gate electrode 211 is provided.

That is, the p-type base layer 204, the p-type drain layer 208, the n-type base layer 203, the gate insulating film 21
0 and the gate electrode 211 constitute a p-type MOSFET.

Here, at least one of the n-type MOSFET and the p-type MOSFET is of a normally-on type, and the threshold voltage V _th1 of the n-type MOSFET is equal to the threshold voltage of the p-type MOSFET. It is lower than the voltage V _th2 .

The anode electrode 2 is formed on the p-type emitter layer 206.
14, a cathode electrode 216 is provided on the n-type emitter layer 207, and a drain electrode 215 connected to the cathode electrode is provided on the p-type drain layer 208. In the figure, reference numeral 205 denotes an n-type buffer layer. A p-type emitter layer 206 that directly contacts the n-type base layer 203 without providing the buffer layer 205
May be formed.

The lateral MOS constructed as described above will be described below.
A gate driving method of the gate type thyristor will be described with reference to a time chart of FIG.

First, in the steady off state, the n-type MOSFE
A voltage Va (first gate voltage) lower than the threshold voltage V _{th1 of} T is applied to the gate electrodes 211 and 213. As a result, the n-type MOSFET is off, and the p-type MOSFET is
Is turned on.

At the time of turn-on, the gate electrodes 211,
13, a voltage Vb (second gate voltage) higher than the threshold voltage V _th2 of the p-type MOSFET is applied. As a result, the n-type MOSFET is turned on and the p-type MOSFET is turned off.

At this time, as shown by the solid line in FIG. 6, electrons are injected from the cathode electrode 216 into the n-type base layer 203 through the n-type emitter layer 207 and the p-type base layer 204, and this electron injection is performed. As a result, holes are injected from the anode electrode 214, and as a result, a latch-up occurs between the n-type emitter layer 7 and the n-type base layer 3, and the element is turned on.

At the time of turn-off, first, the gate electrode 21
The voltage Vc between V _th1 and V _th2 (third
Gate voltage) to apply the n-type MOSFET and p
The type MOSFET is turned on. Thereby, electrons flow from the cathode electrode 216 to the n-type emitter layer 207, the p-type base layer 204, and the n-type base layer 203, and holes are generated.
6, the p-type base 204 layer, the p-channel below the gate electrode 211, and the p-type drain layer 20
8. As a result of flowing to the drain electrode 215, the latch-up state of the element is released.

Next, the voltage Va is applied to the gate electrodes 211 and 213.
Is applied again. As a result, the n-type MOSFET is turned off, injection of electrons is stopped, and holes are sucked out from the drain electrode 215. As a result, the element is turned off.

Thus, according to the present embodiment, the n-type MOSF
At least one of the ET and p-type MOSFETs is normally on, and the n-type MOSFET is
By making the threshold voltage V _{th1 of the} ET lower than the threshold voltage V _th2 of the p-type MOSFET, the same level of voltage can be applied to the gate electrodes 211 and 213 in any state of the device. In addition, the control of the gate voltage becomes easy.

FIG. 8 shows an MO according to a third embodiment of the present invention.
It is sectional drawing which shows the element structure of S gate type thyristor.
Note that, in the following drawings, the same reference numerals as those described above indicate the same or corresponding portions, and a detailed description thereof will be omitted.

This is an example in which the horizontal MOS gate thyristor shown in FIG. 6 is made vertical. By using the vertical type as described above, the withstand voltage can be improved. The driving method is the same as that of the second embodiment.

FIG. 9 shows an MO according to a fourth embodiment of the present invention.
It is sectional drawing which shows the element structure of S gate type thyristor.

The difference between the MOS gate thyristor of this embodiment and that of the third embodiment is that the p-type drain layer 208 on the surface of the n-type base layer 203 has the n-type emitter layer 2.
07 surface.

According to the present embodiment, the element area can be reduced as compared with the third embodiment. Further, the p-type drain layer 208 can be formed shallow, and the channel length can be shortened. The driving method is the same as that of the second embodiment.

FIG. 10 is a block diagram showing a fifth embodiment of the present invention.
It is sectional drawing which shows the element structure of OS gate type thyristor.

The difference between the MOS gate thyristor of this embodiment and that of the third embodiment is that the gate insulating film 210,
An n-type MOS including a gate electrode 211, an n-type base layer 203, a p-type base layer 204, and an n-type emitter layer 207
FET, gate insulating film 211, gate electrode 213, p
The structure is such that the p-type MOSFET including the type base layer 204, the n-type emitter layer 207, and the p-type drain layer 208 is adjacent to each other. With such a structure, the n-type MOSFET and the p-type MOSFET can be driven simultaneously. Also, at the time of turn-off, the p-type drain layer 2
08 and the n-type emitter layer 207 are short-circuited, and holes in the element can be discharged only from the cathode electrode 216, so that holes can be discharged smoothly. The driving method is the second
Is the same as that of the embodiment.

The general effects of the inventions according to the second to fifth embodiments are as follows.

That is, according to the present invention, since the first gate electrode of the first conductivity type channel MOSFET is connected to the second gate electrode of the first conductivity type channel MOSFET, the gate electrode is substantially formed. It becomes one, and the on / off operation of the element becomes easy to control.

By the way, when the MOSFET for turn-on and turn-off is provided as in the above embodiment, the degree of freedom of the design is low, so that the channel width Won is reduced to the channel width W.
In some cases, it may not be larger than off, and it may be difficult to reduce the channel resistance of the turn-off MOSFET. Hereinafter, the following inventions (sixth to thirty-second embodiments) solve such a problem.

First, the above problem will be described in more detail.

FIG. 32 is a sectional view showing the element structure of another conventional MOS gate type thyristor.

As shown, an n-type base layer 1002 is formed in contact with a p-type emitter layer 1001, and a p-type base layer 1003 and an n-type emitter layer 1004 are formed in the n-type base layer 1002 by diffusion. . An anode electrode 1006 is provided on the p-type emitter layer 1001, and a cathode electrode 1007 is provided on the n-type emitter layer 1004.

An n-type drain layer 1007 is selectively formed on the surface of p-type base layer 1003. On p-type base layer 1003 sandwiched between n-type drain layer 1007 and n-type emitter layer 1004, A first gate electrode 1010 is formed with a gate insulating film 1009 interposed therebetween.
N-channel MO for turn-off with 1 as a channel region
An SFET is configured. Further, the n-type drain layer 10
The drain electrode 1008 that contacts the transistor 07 also contacts the p-type base layer 1003 at the same time, and the p-type base layer 1003 and the n-type drain layer 1007 are short-circuited by the drain electrode 1008.

On the other hand, on a p-type base layer 1003 sandwiched between an n-type emitter layer 1004 and an n-type base layer 1002, a second gate electrode 1010 is formed via a gate insulating film 1009. A turn-on n-channel MOSFET having CH2 as a channel region is configured.

FIG. 33 is a plan view of the MOS gate type thyristor of FIG. The n-type emitter layer 1004 is divided into a plurality of parts and is patterned in a stripe shape.
Adjacent to one side of this n-type emitter layer 1004,
Turn-off n-type channel MOSFET composed of first gate electrode 100, p-type base layer 1003, n-type drain layer 1007 and n-type drain electrode 1008
Is formed, and the second gate electrode 1010, the p-type base layer 1003, and the n-type base layer 100
2 n-type channel MOSF for turn-on
ET is formed.

The operation of this device is as follows. That is, at the time of turn-on, a zero or negative voltage is applied to the first gate electrode 1010 with respect to the cathode, and a positive voltage is applied to the second MOS gate electrode 1011.
As a result, an n-channel is formed below the second gate electrode 1011 and electrons are injected from the n-type emitter layer 1004 to the n-type base layer 1002 as shown by a dashed line in FIG. 32, and the device is turned on.

On the other hand, at the time of turn-off, a positive voltage is applied to the first gate electrode 1010 with the second gate electrode 1011 set to zero or a negative bias. Thereby, the first
An n-channel is formed below the gate electrode 1010, and a part of the hole current flowing directly from the p-type base layer 1003 to the n-type emitter layer 1004 is drained from the drain electrode 1008 as shown by a broken line in FIG. After passing through the n-type drain layer 1007, the n
Through the channel, the n-type emitter layer 1004 is bypassed to the cathode electrode 1006. By the hole current bypass, electron injection from the n-type emitter layer 1004 to the p-type base layer 1003 eventually stops, and the device is turned off.

However, such a conventional MOS gate type thyristor has a problem that a sufficient turn-off capability cannot be obtained.

That is, as described above, the turn-off ability largely depends on the resistance of the hole current bypass path shown by the broken line in FIG. 32. The turn-off ability decreases as the resistance increases. Of the n-type emitter layer 100
When the voltage is higher than the built-in voltage between the P-type base layer 1003 and the p-type base layer 1003, electron injection from the n-type emitter layer 1003 does not stop.

Therefore, in order to realize a high turn-off capability, it is necessary to reduce the resistance of the hole current bypass path as much as possible. The resistance of the hole current bypass path is mainly the ON resistance of the n-channel below the MOS gate electrode 1010 and the lateral resistance of the p-type base layer 1003.

In the conventional structure shown in FIGS. 32 and 33, a turn-off MOSFET is formed on one side of the n-type emitter layer 1004 and a turn-on MOSFET is formed on the other side. ing.

That is, the channel width Woff of the turn-off MOSFET is equal to the channel width Won of the turn-on MOSFET. In other words, as the degree of freedom in designing the turn-off and turn-on MOSFETs (MOS structures) for controlling the anode current (main current) is low, the channel width Woff cannot be increased by the channel width Won, and the turn-off MOSFET However, there is a problem that it is difficult to reduce the channel resistance.

Further, as a result of the formation of the turn-off and turn-on MOSFETs as described above, a hole current is drawn only from one side of the p-type base layer 1003 under the n-type emitter layer 1004. Therefore, the hole extraction path becomes longer, and the p-type base layer 1
The extraction resistance of the hole current in 003 increases.

Therefore, an invention in consideration of such circumstances will be described below to obtain a MOS gate type power semiconductor element having a higher degree of freedom in designing a MOS structure for controlling a main current than before. The target invention will be described.

The gist of the present invention is that a first main electrode and a second main electrode provided on a first main surface and a second main surface of a semiconductor substrate, respectively, the first main electrode and the second main electrode are provided. And a plurality of MOS structures for controlling a main current flowing between the two main electrodes. At least two of the gate electrodes constituting the plurality of MOS structures are three-dimensionally arranged via an insulating film. In that they are arranged crossing each other.

According to such an invention, at least two of the gate electrodes constituting the plurality of MOS structures for controlling the main current are arranged so as to intersect three-dimensionally via the insulating film. Have been. For this reason, the arrangement pattern of the gate electrode, which was impossible in the past, becomes possible.
The degree of freedom in designing the S structure is increased.

FIG. 11 is a block diagram showing an M-mode according to a sixth embodiment of the present invention.
It is a top view of an OS gate type thyristor. FIG.
2, FIG. 13, FIG. 14, and FIG.
-A 'sectional view, BB' sectional view, CC 'sectional view, D-
It is D 'sectional drawing.

Parts corresponding to those of the conventional MOS gate type thyristor shown in FIGS. 32 and 33 are denoted by the same reference numerals except for the last three digits (for example, 10101 and 301 indicate the same p-type emitter layer. ), Detailed description is omitted.

The MOS gate thyristor of this embodiment is different from the conventional thyristor shown in FIGS. 32 and 33 in that an n-type emitter layer 304 is divided and arranged in a rectangular shape, and two opposing n-type emitter layers 204 A turn-off gate electrode 310 is formed along the long side, a turn-on gate electrode 311 is formed along the two short sides, and the two gate electrodes 310 and 311 form an insulating film 315 at the intersection. Intersect three-dimensionally. Thus, the channel CH1 of the turn-off MOSFET is formed on the long side, and the turn-on MOSFET is formed on the short side.
An ET channel CH2 is formed.

According to this embodiment, the n-type emitter layer 304
The channel CH1 of the turn-off MOSFET is formed so as to sandwich both ends of the turn-off MOSFET, so that the channel width of the turn-off MOSFET can be larger than that of the turn-on MOSFET.

As a result, the channel resistance of the turn-off MOSFET becomes lower than before, and the holes are drawn out of the p-type base layer 303 under the n-type emitter layer 304 in the short side direction of the n-type emitter layer 304. , The hole extraction path, that is, the lateral resistance of the p-type base layer 3 is reduced.

Therefore, according to the present embodiment, the voltage drop due to the hole current to be bypassed is sufficiently smaller than that of the prior art, so that a MOS gate thyristor having a high turn-off capability can be obtained.

FIG. 16 is a block diagram showing a seventh embodiment of the present invention.
It is a top view of an OS gate type thyristor. FIG.
7 and FIG. 18 are sectional views taken along line AA ′ of FIG.
It is -B 'sectional drawing. A cross-sectional view taken along the line CC ′ of FIG.
The cross-sectional views taken along the line DD ′ are the same as those in FIGS. 14 and 15, respectively.

In this embodiment, the drain electrode 308 is provided along one side of the n-type emitter layer 304 and at a position adjacent to the n-type emitter layer 304 in low resistance contact with the p-type base layer 303.
The n-type drain layer 307 is short-circuited to the p-type base layer 303 by the drain electrode 308. n-type drain layer 30
A turn-off gate electrode 310 is formed between the gate electrode 7 and the n-type emitter layer 304.

In the insulated gate type turn-off thyristor thus configured, the gate electrode 1
When a positive voltage is applied to the cathode at 0, the hole current is sucked out to the drain electrode 308 in the immediate vicinity of the n-type emitter layer 304 and the gate electrode 31
The light passes through the channel immediately below zero and is discharged from the n-type emitter layer 304 to the cathode electrode 306.

As described above, in this embodiment, since the lateral resistance of the p-type base layer 303 under the n-type drain layer 307 does not enter the hole current bypass path, the voltage drop due to the bypassed hole current is generated. And a MOS gate thyristor with higher turn-off capability can be obtained.

FIG. 19 and FIG. 20 are process sectional views showing a method of manufacturing the above-mentioned gate electrode which crosses three-dimensionally.

First, as shown in FIG. 19A, the surface of a high-resistance n-type base layer 302 is oxidized to form a gate insulating film 3.
09 is formed. Next, a gate electrode material such as polysilicon is deposited on the gate insulating film 309 by a CVD method, and the gate electrode material is patterned to form a gate electrode 311 for turn-on.

Next, as shown in FIG. 19B, after an interlayer insulating film 315 such as a polysilicon oxide film is formed on the surface of the gate electrode 311, the gate electrode 311 is used as a mask to form a p-type material such as B. A p-type base layer 303 is formed by ion implantation of a type impurity.

Next, as shown in FIG. 20A, after a gate electrode material such as polysilicon is deposited on the entire surface by the CVD method, the gate electrode material is patterned to form a turn-on gate electrode 310. .

Finally, as shown in FIG. 20B, using the gate electrodes 310 and 311 as a mask, an n-type impurity such as P is ion-implanted to form an n-type emitter layer 304 and an n-type drain layer 307. . At this time, the gate electrodes 310,
The resistances of 311 are sufficiently reduced by n-type impurities ion-implanted on their surfaces. Further, in the above-described CVD method, if a gate electrode material is deposited using a source gas containing impurities, a gate electrode with lower resistance can be formed.

The intersection of the gate electrodes may be modified as follows. That is, as shown in FIG. 21, the width of the gate electrode 310 for turning off at the intersection may be widened and a minute opening may be provided in a part thereof. Accordingly, in the above-described manufacturing method, when the n-type impurity is ion-implanted, the n-type impurity is also ion-implanted into the lower layer turn-on gate electrode 311 through the opening.
The gate electrode 311 in the lower layer of the three-dimensional intersection also has a sufficiently low resistance.

FIG. 22 is a block diagram showing an M-th embodiment according to the eighth embodiment of the present invention.
It is an equivalent circuit diagram of an OS gate type thyristor.

This MOS gate type thyristor has a p-type emitter layer 401, an n-type base layer 402, a p-type base layer 4
03, and an n-type emitter layer 404. An anode electrode 405 is provided on the p-type
4 has a thyristor structure in which a cathode electrode 406 is provided, in which a turn-off MOSFET having a gate electrode 413 and a turn-on MOSFET having a gate electrode 414 are added.

The MOS gate type thyristor of this embodiment is a conventional thyristor (IEDM 89, pp297-300 “Design Aspects of MO”).
S Controlled Thyristor Elements ")
Between the n-type emitter layer 404 and the cathode electrode 406,
Resistor 419 having a higher specific resistance than cathode electrode 406
Is provided.

Here, the maximum turn-off current I _{TGQM in} the case of the conventional structure without the resistor 419 is I _TGQM = _{αV BK} / R _P (1) where R _P is the resistance of the hole current bypass path shown by the broken line. _{) V BK = V J = 0.7} [V] becomes (2).

Here, α is a proportional coefficient, V _BK is a potential between the base and the cathode, and V _J is an emitter junction potential.

The resistance R _P of the hole current bypass path mainly depends on the lateral resistance of the p-type base layer 403 and the gate electrode 41.
The channel resistance is just below the third channel resistance. By reducing these resistances, the maximum turn-off current I _TGQM can be improved.

However, their resistance is the same as that of the n-type emitter layer 4.
Since it depends on the width of the gate electrode 04 and the width of the gate electrode 413, it is necessary to make the structure finer, but this is extremely difficult.
Therefore, in the case of the conventional structure, sufficient turn-off capability cannot be obtained.

[0139] On the other hand, in the present invention, when the anode current in the on state and I _A, the potential of the n-type emitter layer 404 is increased by _{V 0 = I A × R 0} .

As a result, the equation (2) becomes V _BK = V _J + V _0, and the maximum turn-off current I is obtained according to the relation of the equation (1).
_TGQM increases.

That is, at the time of turn-off, even if the voltage drop due to the hole bypass current immediately below the n-type emitter layer 404 exceeds 0.7 V (in the case of silicon), the emitter junction does not reach the forward bias state. n-type emitter layer 4
The injection of electrons from 04 stops, and the device turns off.

FIG. 23 is a sectional view showing a specific element structure. In the present embodiment, a resistor layer 419 having a higher specific resistance than the cathode electrode 406 is formed between the n-type emitter layer 404 and the cathode electrode 406. Resistor layer 4
19 includes, for example, a metal material, an extremely thin insulator material,
A semi-insulating material, a polysilicon film, a natural oxide film, or the like can be used. The p-type source layer 407 and the cathode electrode 40
Nothing is inserted between the gate electrode 6 and the p-type source layer 407 as in the related art.

FIG. 24 is a block diagram showing the M-th embodiment according to the ninth embodiment of the present invention.
It is sectional drawing which shows the element structure of OS gate type thyristor.

The difference between the MOS gate type thyristor of this embodiment and that of FIG.
Interlayer insulating film 406 provided with many minute openings 416
Has been used. Thereby, the n-type emitter layer 40
The same effect as in the case where resistor layer 419 is formed by slightly increasing the contact resistance between electrode 4 and cathode electrode 406 is obtained.

FIGS. 25 and 26 are sectional views showing the element structure of a MOS gate thyristor according to the tenth and eleventh embodiments of the present invention, respectively.

As shown in FIGS. 25 and 26, an n-type base layer 402 is formed in contact with p-type emitter layer 401, and p-type base layer 403 and n-type base layer 403 are formed in n-type base layer 402.
The mold emitter layer 404 is formed by diffusion.

The p-type emitter layer 401 has an anode electrode 4
The cathode electrode 406 is provided on the n-type emitter layer 404. Then, similarly to the case of FIGS. 23 and 24, the n-type emitter layer 404 and the cathode electrode 4
06, a resistor layer 419 having a higher specific resistance than the cathode electrode 406 or an interlayer insulating film 415 provided with a large number of minute openings is formed. In any case, the drain electrode 409 is provided at a position adjacent to the n-type emitter layer 404 and in low contact with the p-type base layer 403.

The n-type drain layer 408 is a drain electrode 40
9 is short-circuited with the p-type base layer 403. The n-type source layer 410 is separated from the n-type drain layer 408 by a predetermined distance.
Is formed between the n-type drain layer 408 and the n-type source layer 410.
Are formed. The source electrode 411 is formed integrally with the cathode electrode 406 and is electrically connected to the cathode electrode 406.

In the MOS gate type turn-off thyristors of these embodiments, at the time of turn-off, a positive voltage is applied to the turn-off insulated gate electrode 413 with respect to the cathode. The bypass path of the hole current at this time is indicated by a broken line. The hole current is, as shown, the n-type emitter layer 404.
, And is discharged from the source electrode 411 to the outside of the device through the channel CH1 immediately below the turn-off gate electrode 413.

FIG. 27 is a sectional view showing an element structure of a MOS gate type thyristor according to a twelfth embodiment of the present invention.

In this embodiment, the element shown in FIG. 23 is used as a unit element, and a number of the unit elements are formed on the same substrate to constitute one element. This is an example in which a layer 420 is used. The specific resistance of the temperature-dependent resistor layer 420 increases instantaneously as the temperature rises.

If a large number of conventional structures having no temperature-dependent resistor layer 420 are formed in parallel in this way, a unit having a delayed turn-off due to a slight difference in turn-off time between individual unit elements at the time of turn-off. A problem arises in that the entire current flowing through the element is concentrated on the element, leading to destruction.

On the other hand, in the case of this embodiment, the temperature-dependent resistor layer 420 allows the current to concentrate on one unit element due to variations in the characteristics of each unit element at the time of turn-off. The resistance of the temperature-dependent resistor layer 420 instantaneously increases due to the rise in temperature, and the turn-off capability of the unit element is improved by the mechanism described in FIG. The current is distributed and the entire device is turned off. As the temperature-dependent resistor layer 420, for example, hydrogen-doped graphite or the like can be used.

FIG. 28 is a sectional view showing an element structure of a MOS gate thyristor according to a thirteenth embodiment of the present invention.

In this embodiment, the n-type base layer 402 is formed in contact with the p-type emitter layer 401, and the p-type base layer 403 and the n-type emitter layer 404 are formed in the n-type base layer 402 by diffusion. ing. p-type emitter layer 40
1 is provided with an anode electrode 6, and the n-type emitter layer 404 is provided with a cathode electrode 406.

An n-type drain layer 408 is formed on the surface of p-type base layer 403 at a predetermined distance from n-type emitter layer 404. This n-type drain layer 408 and first n-type emitter layer 404 are formed. A first gate electrode 413 is disposed on the p-type base layer 403 with a gate insulating film 412 interposed therebetween, and a turn-off n-channel MOSFET having CH1 as a channel region is formed.

The drain electrode 409 in contact with the n-type drain layer 408 also contacts the p-type base layer 403 at the same time, and the p-type base layer 403 and the n-type drain layer 40
8 is short-circuited by the drain electrode 409.

On the other hand, at a position opposite to the n-type drain layer 408, a second n-type emitter layer 421 is formed at a predetermined distance from the first n-type emitter layer 404.
N-type emitter layer 421 and first n-type emitter layer 404
A third n-type emitter layer 422 having a lower concentration than the first and second n-type emitter layers is formed between the first and second n-type emitter layers. The gate insulating film 41 is formed on the third n-type emitter layer 422.
2, a third insulated gate electrode 423 is provided.

The operation of the MOS gate thyristor thus configured is as follows.

That is, in the ON state, zero to negative voltage is applied to the first gate electrode 413 with respect to the cathode, and zero to positive voltage is applied to the third gate electrode 423, and To the third n-type emitter layer 40
From the entirety of 4,421,422, electrons are p-type base layer 403
Injected into.

To turn off, a negative voltage is applied to the first gate electrode 413 with respect to the cathode, and a negative voltage is applied to the third gate electrode 423.

As a result, the hole current flowing from the p-type base layer 403 to the n-type emitter layers 404, 421, 422 is changed to the drain electrode 409, the n-type drain layer 408, the first
The channel CH <b> 1 immediately below the gate electrode 413 passes through the first n-type emitter layer 404 to the cathode electrode 407.

At this time, the third n-type emitter layer 423 immediately below the third gate electrode 423 is depleted near the surface, and
Since the resistance from the first n-type emitter layer 404 to the second n-type emitter layer 421 increases, the mechanism described with reference to FIG. 22 operates in the second n-type emitter layer 421 to improve the turn-off capability. .

Since the different gate electrodes are arranged three-dimensionally crossing each other with an insulating film interposed therebetween, the arrangement pattern of the gate electrodes, which was impossible in the past, becomes possible, and the degree of freedom in designing the MOS structure is increased. Get higher.

FIG. 34 is a sectional view showing an element structure of a MOS gate thyristor (MCT) according to a fourteenth embodiment of the present invention (claim 2 ).

In the figure, reference numeral 901 denotes a high-concentration p-type emitter layer, and a low-concentration n-type base layer 902 is formed in contact with the p-type emitter layer 901. A p-type base layer 903 is selectively formed on the surface of the n-type base layer 902 by diffusion. A high-concentration n-type emitter layer 904 is formed on the surface of the p-type base layer 903 by diffusion. .

High-concentration p-type source layer 907 is selectively formed on the surface of n-type emitter layer 904, and p-type base layer 903 in a region sandwiched between p-type source layer 907 and n-type base layer 902 is formed. A gate electrode 913 is formed over the n-type emitter layer 904 via a gate insulating film 912.

Further, on the surface of n-type emitter layer 904, a low-concentration n-type pseudo-resistance semiconductor layer 916 which does not exist in the conventional MCT shown in FIG. 59 is selectively formed. Is provided with a cathode electrode 906. The cathode electrode 906 is not in contact with the p-type source layer 907, unlike the conventional MCT shown in FIG. Therefore, a source electrode 911 is separately provided in the p-type source layer 907. An anode electrode 905 is provided on the p-type emitter layer 901.

In the case of this embodiment, the n-type pseudo-resistance semiconductor layer 9
16 functions as the resistor 419 of the MOS gate type thyristor shown in FIG. 22 (eighth embodiment), so that the same effect as in the eighth embodiment can be obtained.

That is, since a resistor is formed by the n-type pseudo-resistance semiconductor layer 916 between the n-type emitter layer 904 and the cathode electrode 906, the potential of the n-type emitter layer 904 in the ON state slightly increases, As a result, at the time of turn-off, a voltage drop due to a hole bypass current flowing through the p-type base layer 903 immediately below the n-type emitter layer 904 causes the built-in voltage between the n-type emitter layer 904 and the p-type base layer 903 to be zero. Even if the voltage exceeds 0.7 V (in the case of silicon), the level exceeding the voltage exceeds that of the n-type pseudo-resistance semiconductor layer 91.
If the potential rise is within the potential rise due to 6, the electron injection can be stopped and the device can be turned off.

In other words, V _BK in the equation (1) increases and the maximum cutoff current I _TGQM increases, so that a larger current can flow.

Therefore, according to the present embodiment, a sufficient turn-off capability can be obtained without miniaturizing the element.

In the case where the structure shown in FIG. 34 is a unit structure and a plurality of elements are arranged on the same substrate to form one element, a slight difference in turn-off time between individual unit elements at the time of turn-off causes There is a risk that the entire current will concentrate on the unit element whose turn-off is delayed, leading to destruction. However, in the case of the present embodiment, a potential difference is caused by the n-type pseudo low semiconductor layer 916, and the current can be suppressed and the current density can be averaged. Operation is obtained.

FIG. 35 is a sectional view showing an element structure of a MOS gate type power semiconductor device (IGTT) according to a fifteenth embodiment of the present invention. In the elements of the drawings below, the portions corresponding to the elements of the above-mentioned drawings are denoted by the same reference numerals as those of the above-mentioned drawings, and detailed description will be omitted.

In this embodiment, an n-type base layer 902 is formed in contact with the p-type emitter layer 901, and a p-type base layer 903 is formed on the surface of the n-type base layer 902, and Is formed by selectively diffusing an n-type emitter layer 904. An anode electrode 905 is formed on the p-type emitter layer 901.

As in the case of the MOS gate type power semiconductor device of FIG. 34, an n-type pseudo-resistance semiconductor layer 916 provided with a cathode electrode 906 is connected in series between the cathode electrode 906 and the n-type emitter layer 904. It is connected to the.

A high-concentration n-type drain layer 908 is selectively formed on the surface of p-type base layer 903.
The drain electrode 909 is provided on the mold drain layer 908. This drain electrode 909 is an n-type drain layer 90
At the same time, the p-type base layer 903 is also in contact with the p-type base layer 903, thereby short-circuiting the n-type drain layer 908 and the p-type base layer 903.

An n-type source layer 910 is formed on the surface of the p-type base layer at a predetermined distance from n-type drain layer 908, and a p-type base layer between n-type source layer 910 and n-type drain layer 908 is formed. A gate insulating film 912 is formed over the gate insulating film 903.
, A turn-off gate electrode 914 is formed. Further, the source electrode 91 is provided on the n-type source layer 910.
1 is provided, and the source electrode 911 is electrically connected to the cathode electrode 906.

In the MOS gate type power thyristor of this embodiment, a positive voltage is applied to the gate electrode 914 with respect to the cathode electrode 906 at the time of turning off. At this time, the hole current is sucked into the drain electrode 909 immediately near the n-type emitter layer 904, passes through the n-channel immediately below the gate electrode 914, and passes from the source electrode 911 to the cathode 906.

In this embodiment also, FIG. 34 (14th embodiment)
As in the case of the MOS gate type power thyristor described above, the n-type pseudo-resistance semiconductor 916 allows a larger amount of current to flow than in the past, and the current concentration hardly occurs even when a plurality of currents are arranged on the same substrate. Stable operation becomes possible.

FIG. 36 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to a sixteenth embodiment of the present invention (claim 3 ).

The MOS gate type power semiconductor device of this embodiment is different from that of FIG. 34 (the fourteenth embodiment) in that
A high-concentration p-type semiconductor layer 917 is used instead of the n-type pseudo-resistance semiconductor layer 916.

That is, a p-type semiconductor layer 917 is selectively formed on the surface of the n-type base layer 902 by diffusion, and the first contact electrode 919,
A second contact electrode 918 is provided.

As a result, holes are generated in the n-type emitter layer 90.
4, cathode electrode 906, first contact electrode 91
9, p-type semiconductor layer 917, second contact electrode 91
8. The current flows between the cathode and the n-type emitter layer 940 through the path of the cathode. At this time, the holes are p
When flowing through the p-type semiconductor layer 917,
Causes a voltage drop due to the diffusion resistance of the n-type emitter layer 90.
4, the potential of the n-type emitter layer 904 rises as in the case where the n-type pseudo-resistance semiconductor layer 916 is provided. Therefore, effects similar to those of the fourteenth embodiment can be obtained.

FIG. 37 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to a seventeenth embodiment of the present invention.

This embodiment is an example in which the method of the sixteenth embodiment in FIG. 36 is applied to the fifteenth embodiment in FIG.
The n-type pseudo-resistance semiconductor layer 916 of FIG. 5 utilizes the diffusion resistance of a high-concentration p-type semiconductor layer 917.

FIG. 38 is a sectional view showing an element structure of a MOS gate type power semiconductor device according to an eighteenth embodiment of the present invention.

In this embodiment, the diffusion resistance of the p-type semiconductor layer 920 is used similarly to the p-type semiconductor layer 917 of the MOS gate type power semiconductor device shown in FIG. 36, and the first contact electrode 919 and the second N between the contact electrode 918
The resistance between the electrodes is set to a desired value by diffusing the mold semiconductor layer 921.

FIG. 39 is a sectional view showing the device structure of a MOS gate type power semiconductor device according to the nineteenth embodiment of the present invention.

Also in this embodiment, a p-type semiconductor layer 920 is used in place of the n-type pseudo-resistance semiconductor of FIG. 35, and the diffusion resistance of the p-type semiconductor layer 920 becomes a predetermined value by the n-type semiconductor layer 921. Like that.

FIG. 40 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to the twentieth embodiment of the present invention.

This embodiment uses the diffusion resistance of the n-type semiconductor layer 921 diffused in the p-type semiconductor layer 920 instead of the n-type pseudo-resistance semiconductor layer 916 of FIG.

As compared with the eighteenth embodiment of FIG. 38, the n-type semiconductor layer has an advantage that the diffusion resistance can be smaller than that of the p-type semiconductor layer.

In this embodiment, the p-type semiconductor layer 920
And the n-type semiconductor layer 921 are connected to the second contact electrode 91.
8 is short-circuited. This is because the p-type semiconductor layer 920 and n
If the type semiconductor layer 921 is not short-circuited, the thyristor operation starts immediately below the n-type semiconductor layer 921, and the thyristor does not turn off.

FIG. 41 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to a twenty-first embodiment of the present invention.

This embodiment is an example in which the method of the twentieth embodiment of FIG. 40 is applied to the nineteenth embodiment of FIG. 39, and utilizes the diffusion resistance of the n-type semiconductor layer 921.

FIG. 42 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to a twenty-second embodiment of the present invention.

The MOS gate type power semiconductor device of this embodiment is different from that of the twentieth embodiment shown in FIG. 40 in that a p-type semiconductor layer 917 is formed between an electrode 918 and a second electrode 919 between the first electrode 918 and the second electrode 919. The diffusion resistance is formed on the surface of the mold semiconductor layer 921 so that a desired resistance value can be obtained.

FIG. 43 is a sectional view showing an element structure having a structure according to the twenty-third embodiment of the present invention. Also in this embodiment, n
The diffusion resistance of the semiconductor layer 921 is controlled by the p-type high-concentration layer 917 to replace the n-type pseudo-resistance semiconductor layer 916 in FIG.

FIG. 44 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to a twenty-fourth embodiment of the present invention.

In this embodiment, a thick insulating film (for example, an oxide film) 923 is formed on the surface of the n-type base layer 902, and a resistor thin film 922 (for example, a polysilicon layer) is formed thereon. A first electrode 919 and a second electrode 918 are provided for the first electrode 919 and the second electrode 91.
In this example, the resistor thin film 922 is used in place of the n-type pseudo-resistance semiconductor 916 in FIG. 34 by connecting 8 to the cathode electrode 906 and the source electrode 911, respectively.

FIG. 45 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to a twenty-fifth embodiment of the present invention.

This embodiment is an example in which the method of the twenty-fourth embodiment in FIG. 44 is applied to the fifteenth embodiment in FIG.
5 in place of the n-type pseudo-resistive semiconductor 916,
22 resistors.

FIG. 46 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to the twenty-sixth embodiment of the present invention.

This embodiment is different from the sixteenth embodiment shown in FIG.
In this example, a diffusion resistance of a high-concentration p-type ring semiconductor layer (guard ring layer) 924 used for a junction termination portion for increasing a breakdown voltage is used instead of the type semiconductor layer 917.

In the figure, reference numeral 925 denotes a low-concentration p-type ring semiconductor layer (guard ring layer), and 926 denotes a high-concentration n-type stopper layer.

FIG. 47 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to a twenty-seventh embodiment of the present invention.

This embodiment is different from the seventeenth embodiment shown in FIG.
In this example, a diffusion resistance of a high-concentration p-type ring semiconductor layer (guard ring layer) 924 used for a junction termination portion for increasing a breakdown voltage is used instead of the type semiconductor layer 917.

FIG. 48 is a sectional view showing an element structure of a MOS gate type power semiconductor device according to a twenty-eighth embodiment of the present invention.

In this embodiment, a p-type source layer 907 and a p-type semiconductor layer 917 are formed in the n-type emitter layer 904 by diffusion, and the p-type source layer 907 and the p-type semiconductor layer 91 are diffused.
7, a second gate electrode 914 is formed on the n-type emitter layer 904. The p-type semiconductor layer 917 and the n-type base layer 904 are short-circuited by the cathode electrode 906.

In this embodiment, a negative voltage is always applied to the second gate electrode 914 with respect to the cathode (in this case, the source electrode 911), so that the p-type source layer 907 and the n-type base layer 9
04, p-channel MISF composed of p-type semiconductor layer 917
ET is kept conductive.

That is, in this embodiment, the channel resistance immediately below the second gate electrode 914 is changed to the n-type pseudo-resistance semiconductor layer 9.
16 is used.

FIG. 49 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to the twenty-ninth embodiment of the present invention.

This embodiment is an example in which the technique of the twenty-eighth embodiment of FIG. 48 is applied to the MOS gate type power semiconductor device 35 of the nineteenth embodiment of FIG.
4. The channel resistance of the n-channel MISFET composed of the p-type base layer and the n-type semiconductor layer 921 is reduced by
It is used as a 0, n-type semiconductor layer 921.

FIG. 50 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to the thirtieth embodiment of the present invention.

In this embodiment, in addition to the n-type emitter layer 904, an n-channel MISFET is formed in the same manner as in FIG.
This is an example of using as

That is, in this embodiment, the p-type semiconductor layer 920 in the MOS gate type power semiconductor device of FIG.
An n-channel MISFET is formed therein.

In this embodiment, a positive voltage is always applied to the second gate electrode 914 with respect to the cathode (in this case, the first electrode 918). The p-type semiconductor layer 920 and the n-type semiconductor layer 921 are short-circuited to prevent the thyristor operation of the mold layer 921 from becoming impossible to turn off.

FIG. 51 is a sectional view showing an element structure of a MOS gate type power semiconductor element according to a thirty-first embodiment of the present invention.

This embodiment is an example in which the method of the thirtieth embodiment shown in FIG. 50 is applied to the MOS gate type power semiconductor device shown in FIG. 39, and an n-type resistor formed in a p-type semiconductor layer 920 as a resistor. This utilizes the channel resistance of the channel MISFET.

FIG. 52 is a plan view of a MOS gate type power semiconductor device according to a thirty-second embodiment of the present invention. 53, FIG. 54, and FIG.
-A 'sectional drawing, BB sectional drawing, and CC' sectional drawing.

In this embodiment, basically, the element structure shown in the embodiment of FIG. 37 is used. Then, the second gate electrode 914 for turn-off is formed by a thick lead portion 91.
4a and a gate portion 914b of a MIS structure extending in a thin rectangular ring shape therefrom.

The cathode electrode 906 is connected to the source electrode 911 through the p-type semiconductor 917, and the drain electrode 909 for discharging holes passes over the second gate electrode 914a having a large width, and is formed in a rectangular ring shape. 2 and the source electrode 911 and the n-channel M
Connected by ISFET.

Further, as shown in FIG.
Reference numeral 11 denotes a cathode electrode 906 via a p-type semiconductor layer 917.
And the MIS for turn-off.
The potential of the p-type semiconductor layer 920 including the FET can be stabilized.

As can be seen from FIG. 54, the holes are
Drain is discharged from the drain electrode 909 through the n-type drain layer 908, the channel region immediately below the gate electrode 914b for turn-off, the n-type source layer 910, and the source electrode 911. The n-type drain layer 908 and the n-type source layer 910 are alternately arranged, and a repetitive structure provides a channel width of the MISFET required for discharging holes.

FIG. 55 shows a portion where a thick turn-off insulated gate electrode 914a is drawn out and a hole where a drain electrode 909 for discharging holes is drawn out.

The element is turned on by applying a positive voltage to the cathode electrode 906 to the turn-on gate electrode 913 and injecting electrons from the n-type emitter layer 904.

On the other hand, the turn-off is the second turn-off.
Of the gate electrode 914 (in this case, the source electrode 9
11) to apply a positive voltage to the n-type drain layer 90
9, the channel region of the n-channel MISFET including the p-type layer 920 and the n-type source layer 910 is made conductive, and holes are discharged from the drain electrode 909 to the source electrode 911.

The structure of this embodiment is characterized in that the channel width of the turn-off MISFET can be made sufficiently larger than the width of the n-type emitter layer 904, and that the turn-off gate electrode 914a is extended to turn off. In this case, the channel resistance of the MISFET for turning off becomes small, and a larger current can be turned off, and the element area efficiency is increased because the source electrode 911 and the drain electrode 909 pass over the thick turn-off gate electrode 914a.

FIG. 56 is a cross-sectional view showing how to take the electrode when pressing the cathode electrode 906 of the AA 'cross-sectional view shown in FIG. 53. This shows a structure in which the cathode electrode 906 and the gate electrode 913 for turning on are covered with an insulating film 927 (for example, a polyimide film), and only the source electrode 911 is exposed.

FIG. 57 is a cross-sectional view showing another way of taking the electrode when the cathode electrode of the AA 'cross-sectional view shown in FIG. 53 is pressed. This shows a structure in which the pressure contact is made easier by leaving only the source electrode 911 and covering the other with the insulating film 927 and further arranging the pressure contact electrode 915 on the source electrode 911. .

FIG. 58 is a cross-sectional view showing how to take another electrode when the cathode electrode of the AA 'cross-sectional view shown in FIG. 53 is pressed. In this structure, the area of the insulating film 927 is made larger than that in FIG. 57 so that the press-contact electrode 915 does not overlap the turn-off gate electrode 914. In this case, the influence of the stress at the time of pressure contact on the gate electrode can be reduced.

The general effects of the inventions according to the sixth to eighth embodiments are as follows.

That is, according to the present invention, since different gate electrodes are three-dimensionally intersected with an insulating film interposed therebetween, the arrangement pattern of the gate electrodes, which was impossible in the past, becomes possible. The degree of freedom in designing the structure is increased.

The present invention is not limited to the embodiment described above. For example, in the above embodiment, the case where the p-type emitter layer and the n-type base layer are in direct contact with each other has been described. However, a buffer layer or the like is provided between these layers, and the p-type emitter layer and the n-type base layer are indirectly connected. The present invention is also effective when touching. Further, the above embodiments may be variously combined. In addition, various modifications can be made without departing from the scope of the present invention.

[0236]

As described in detail above, the present invention (claim 1)
According to this, the lateral resistance of the second conductivity type base layer in the bypass path and the channel resistance at the time of turn-off can be reduced, so that the turn-off characteristics can be greatly improved.

According to the present invention (claims 2 and 3 ),
Since there is a resistor between the first conductivity type emitter layer and the second main electrode, the potential of the first conductivity type emitter layer rises during the ON state, and as a result, the first conductivity type emitter layer is Even if the built-in voltage between the second conductive type base layer and the second conductive type base layer is exceeded,
Latch-up does not occur if the level of the excess exceeds the potential rise due to the resistor, so that a sufficient turn-off capability can be obtained without miniaturizing the element.

[Brief description of the drawings]

FIG. 1 is a plan view of a MOS gate thyristor according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1;

FIG. 3 is a time chart showing a gate driving method of the MOS gate type thyristor of the present invention.

FIG. 4 is a diagram showing a relationship among an n-type source layer, a source electrode, and a p-type base layer of the MOS gate thyristor in FIG. 1;

FIG. 5 is a diagram showing a relationship among an n-type source layer, a source electrode, and a p-type base layer according to a modification of the MOS gate thyristor of FIG. 1;

FIG. 6 is a sectional view showing an element structure of a lateral MOS gate thyristor according to a second embodiment of the present invention;

FIG. 7 is a time chart showing a gate driving method of the lateral MOS gate thyristor of FIG. 6;

FIG. 8 is a sectional view showing an element structure of a MOS gate thyristor according to a third embodiment of the present invention.

FIG. 9 is a sectional view showing an element structure of a MOS gate thyristor according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view showing an element structure of a MOS gate thyristor according to a fifth embodiment of the present invention.

FIG. 11 is a plan view of a MOS gate thyristor according to a sixth embodiment of the present invention.

FIG. 12 is a sectional view taken along line AA ′ of FIG. 11;

FIG. 13 is a sectional view taken along line BB ′ of FIG. 11;

FIG. 14 is a sectional view taken along the line CC ′ of FIG. 11;

FIG. 15 is a sectional view taken along the line DD ′ of FIG. 11;

FIG. 16 is a plan view of a MOS gate thyristor according to a seventh embodiment of the present invention.

FIG. 17 is a sectional view taken along line AA ′ of FIG. 16;

18 is a sectional view taken along the line BB 'of FIG.

FIG. 19 is a process cross-sectional view of a first half showing a method of manufacturing a gate electrode which crosses three-dimensionally;

FIG. 20 is a process sectional view of the latter half showing a method of manufacturing a gate electrode which crosses three-dimensionally;

FIG. 21 is a diagram showing a modification of an intersection of gate electrodes.

FIG. 22 is an equivalent circuit diagram of a MOS gate thyristor according to an eighth embodiment of the present invention.

FIG. 23 is a sectional view showing an element structure of a MOS gate thyristor according to an eighth embodiment of the present invention;

FIG. 24 is a sectional view showing an element structure of a MOS gate thyristor according to a ninth embodiment of the present invention;

FIG. 25 is a sectional view showing an element structure of a MOS gate thyristor according to a tenth embodiment of the present invention.

FIG. 26 is a sectional view showing an element structure of a MOS gate thyristor according to an eleventh embodiment of the present invention;

FIG. 27 is a sectional view showing an element structure of a MOS gate thyristor according to a twelfth embodiment of the present invention.

FIG. 28 is a sectional view showing an element structure of a MOS gate thyristor according to a twelfth embodiment of the present invention;

FIG. 29 is a sectional view showing the element structure of a conventional MOS gate thyristor.

FIG. 30 is a sectional view showing the element structure of a conventional horizontal insulated gate thyristor.

FIG. 31 is a time chart showing a gate driving method of the lateral MOS gate thyristor of FIG. 30;

FIG. 32 is a sectional view showing the element structure of another conventional insulated gate type turn-off thyristor.

FIG. 33 is a sectional view taken along line AA ′ of FIG. 32;

FIG. 34 is a sectional view showing an element structure of a MOS gate thyristor (MCT) according to a fourteenth embodiment of the present invention;

FIG. 35 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a fifteenth embodiment of the present invention;

FIG. 36 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a sixteenth embodiment of the present invention;

FIG. 37 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a seventeenth embodiment of the present invention.

FIG. 38 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to an eighteenth embodiment of the present invention;

FIG. 39 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a nineteenth embodiment of the present invention;

FIG. 40 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twentieth embodiment of the present invention;

FIG. 41 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-first embodiment of the present invention;

FIG. 42 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-second embodiment of the present invention;

FIG. 43 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-third embodiment of the present invention;

FIG. 44 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-fourth embodiment of the present invention;

FIG. 45 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-fifth embodiment of the present invention;

FIG. 46 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-sixth embodiment of the present invention;

FIG. 47 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-seventh embodiment of the present invention.

FIG. 48 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-eighth embodiment of the present invention;

FIG. 49 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a twenty-ninth embodiment of the present invention;

FIG. 50 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a thirtieth embodiment of the present invention;

FIG. 51 is a sectional view showing an element structure of a MOS gate thyristor (IGTT) according to a thirty-first embodiment of the present invention;

FIG. 52 is a plan view of a MOS gate thyristor (IGTT) according to a thirty-second embodiment of the present invention.

FIG. 53 is a sectional view taken along line AA ′ of FIG. 53;

FIG. 54 is a sectional view taken along line BB ′ of FIG. 53;

FIG. 55 is a sectional view taken along the line CC ′ of FIG. 53;

FIG. 56 is a sectional view showing how to take an electrode when the cathode electrode of FIG. 53 is brought into pressure contact.

FIG. 57 is a cross-sectional view showing how to take another electrode when the cathode electrode of FIG. 53 is pressed.

FIG. 58 is a cross-sectional view showing how to take another electrode when the cathode electrode of FIG. 53 is pressed.

FIG. 59 shows a conventional MOS gate type power semiconductor device (M
Sectional view showing the element structure of (CT)

[Explanation of symbols]

101 ... n-type base layer (first conductivity type base layer) 102 ... p-type base layer (second conductivity type base layer) 103 ... n-type emitter layer (first conductivity type emitter layer) 104 ... p-type emitter layer (first 2 conductive type emitter layer 105 105 cathode electrode (second main electrode) 106 anode electrode (first main electrode) 107 n-type drain layer (first conductive type drain layer) 108 drain electrode 109 gate insulation Film (second gate insulating film) 110 gate electrode (second gate electrode) 111 n-type source layer (source layer of first conductivity type) 112 source electrode 123 gate insulating film (first gate insulating film) 124 ... gate electrode (first gate electrode) 203 ... n-type base layer (first conductivity type base layer) 204 ... p-type base layer (second conductivity type base layer) 206 ... p-type emitter layer (second conductivity type) Type Emi 207: n-type emitter layer (first conductivity type emitter layer) 208: p-type drain layer (second conductivity type drain layer) 210: gate insulating film (second gate insulating film) 211: second Gate electrode (second gate electrode) 212: first gate insulating film (first gate insulating film) 213: first gate electrode (first gate electrode) 214: anode electrode (first main electrode) 215 drain electrode 216 cathode electrode (second main electrode) 401 p-type emitter layer (first main surface) 402 n-type base layer 403 p-type base layer 404 n-type emitter layer (second 405: Anode electrode (first main electrode) 406: Cathode electrode (second main electrode) 901: p-type emitter layer (second conductivity type emitter layer) 902 ... n-type base layer (first conductivity type) Base layer) 903: p-type 904... N-type emitter layer (first conductive type emitter layer) 905... Anode electrode (first main electrode) 906... Cathode electrode (second main electrode) 916. Type pseudo-resistance semiconductor layer (first conductivity type pseudo-resistance semiconductor layer) 917 ... p-type semiconductor layer (second conductivity type semiconductor layer) 918 ... second contact electrode 919 ... first contact electrode

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Ichiro Omura 1 Toshiba-cho, Komukai, Koyuki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba R & D Center Co., Ltd. (56) References JP-A-6-125078 (JP, A) JP-A-5-283675 (JP, A) JP-A-7-183488 (JP, A) JP-A-62-76557 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29 / 749

Claims (5)

(57) [Claims] A second conductive type emitter layer which is in direct or indirect contact with the surface of the first conductive type base layer; and a surface of the first conductive type base layer opposite to the second conductive type emitter layer. A second conductivity type base layer formed selectively; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; and a second conductivity type base layer selectively formed on the surface of the second conductivity type base layer. A first conductivity type source layer formed, and a first conductivity type selectively formed on a surface of the second conductivity type base layer between the first conductivity type emitter layer and the first conductivity type source layer. A first layer provided on a second conductive type base layer interposed between the drain layer and the first conductive type base layer and the first conductive type emitter layer via a first gate insulating film; An electrode, sandwiched between the first conductivity type drain layer and the first conductivity type source layer A second gate electrode provided on the second conductive type base layer via a second gate insulating film, a first main electrode provided on the second conductive type emitter layer, A second main electrode provided on the conductive type emitter layer; a drain electrode provided on the second conductive type base layer and the first conductive type drain layer; A source electrode connected to a second main electrode, wherein the first conductivity type emitter layer and the second main electrode are formed so as to surround the first gate electrode; A first conductivity type drain layer and the drain electrode are formed so as to surround the type emitter layer and the second main electrode; and the second gate electrode is formed so as to surround the first conductivity type drain layer and the drain electrode. Formed And a first conductivity type source layer and the source electrode are formed so as to surround the second gate electrode. 2. A first conductivity type base layer, a second conductivity type emitter layer directly or indirectly in contact with the surface of the first conductivity type base layer, and provided with a first main electrode; A second conductive type base layer selectively formed on the surface of the first conductive type base layer opposite to the conductive type emitter layer; and a first conductive type base layer selectively formed on the surface of the second conductive type base layer. A conductive type emitter layer, a second conductive type source layer selectively formed on the surface of the first conductive type emitter layer and provided with a source electrode, a second conductive type source layer and the first conductive type base. A gate electrode provided via a gate insulating film on the second conductive type base layer and the first conductive type emitter layer sandwiched between the first conductive type emitter layer and a surface of the first conductive type emitter layer; Formed,
A first conductivity type resistive semiconductor layer provided with a second main electrode connected to the source electrode; and a MOS gate type power semiconductor element. 3. A first conductivity type base layer, a second conductivity type emitter layer directly or indirectly in contact with the surface of the first conductivity type base layer, and a second conductivity type emitter layer provided with a first main electrode. A second conductive type base layer selectively formed on the surface of the first conductive type base layer opposite to the conductive type emitter layer; and a second conductive type base layer selectively formed on the surface of the second conductive type base layer. A first conductivity type emitter layer provided with a main electrode of: and a first conductivity type emitter layer selectively formed on a surface of the first conductivity type emitter layer;
A second conductivity type source layer provided with a source electrode connected to the second main electrode; and the second conductivity type base layer sandwiched between the second conductivity type source layer and the first conductivity type base layer. A gate electrode provided on the first conductivity type emitter layer via a gate insulating film; a second conductivity type semiconductor layer selectively formed on a surface of the first conductivity type base layer; A first contact electrode provided on the two-conductivity-type semiconductor layer and connected to the second main electrode; and a second contact electrode provided on the second-conductivity-type semiconductor layer and connected to the source electrode A MOS gate type power semiconductor device, comprising: 4. A first conductivity type base layer, a second conductivity type emitter layer directly or indirectly in contact with the surface of the first conductivity type base layer, and the second conductivity type emitter layer opposite to the second conductivity type emitter layer. A second conductivity type base layer selectively formed on the surface of the one conductivity type base layer; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; A first main electrode provided on the first conductive type emitter layer, a second main electrode provided on the first conductive type emitter layer, and the first conductive type base layer and the first conductive type emitter layer. An n-type MOSFET driven by a first gate electrode provided on the second conductive type base layer with a first gate insulating film interposed therebetween, the first conductive type emitter layer and the second conductive type A first gate electrode that electrically shorts with the mold base layer; P-type MOS controlled by a short-circuited second gate electrode
A method for driving a MOS gate type power semiconductor device comprising: an FET, wherein at the time of steady OFF, the gate electrode turns off an n-type MOSFET and turns on a p-type MOSFET.
A second voltage that turns on the n-type MOSFET and turns off the p-type MOSFET at the time of turn-on, and turns on the n-type MOSFET at the time of turn-off. A third voltage between a first voltage and a second voltage for turning on a p-type MOSFET and applying the first voltage after a lapse of a predetermined time.
A method for driving a gate type power semiconductor device. 5. The semiconductor device according to claim 1, wherein the p-type MOSFET is formed in a second region formed in a surface region of the first conductivity type emitter layer.
A conductive type drain layer, a drain electrode connected to the second main electrode formed on the second conductive type drain layer, and a second conductive type drain layer and a second conductive type base layer. A p-type MO controlled by a second gate electrode formed on the first conductivity type emitter layer via a gate insulating film.
5. The MOS according to claim 4 , wherein the MOS is an SFET.
A method for driving a gate type power semiconductor device.