JP2630444B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Writing information by short-circuiting a junction, a so-called J-
PROM (junction shorting programmable read only
memory), a method for fabricating a semiconductor memory device, comprising the steps of:
By forming it in the araminate method, the transistor as a memory cell can be miniaturized, and the purpose of further increasing the integration of the J-PROM is to form a collector extraction layer and interlayer insulation on the exposed active area. Forming a film, then selectively etching the interlayer insulating film and the collector extraction layer to form openings for forming a base region and an emitter region, and then forming an insulating film Forming a side wall film covering the side wall of the opening by performing anisotropic etching;
Next, a step of introducing an impurity twice through the opening to form a base region not exceeding the thickness of the sidewall film and an emitter region in the base region. .

[Industrial applications]

The present invention writes information by short-circuiting the junction,
The so-called J-PROM (junction shorting programmable
The present invention relates to a method suitable for manufacturing a semiconductor memory device called “read only memory”.

At present, the J-PROM is required to have a large scale like other semiconductor memory devices. Therefore, it is necessary to manufacture transistors by a self-alignment method, reduce the occupied area, and achieve high integration.

[Conventional technology]

FIG. 6 is a main part circuit diagram for explaining the structure of a normal J-PROM.

In the figure, WL1, WL2, WL3 indicate word lines, and BL1, BL2 indicate bit lines.

As can be seen, one transistor forms one memory cell.

FIG. 7 is a sectional side view for explaining a specific structure of a memory cell in the J-PROM.

In the figure, 21 is a p-type silicon semiconductor substrate, 22 is an n-type buried layer, 23 is an n-type silicon semiconductor layer epitaxially grown, 24 is a p-type element isolation region, and 25 is silicon dioxide (SiO ₂ ). An isolation insulating film, 26 is an insulating film made of SiO ₂ , 27 is a p-type base region, 28 is an n-type emitter region, 29
Is an n-type collector contact region, 30 is an emitter electrode,
Reference numeral 31 denotes a collector electrode.

In this J-PROM, a large reverse current pulse is applied to the floating and base transistors to raise the temperature of the emitter-base junction, and the bit line made of, for example, aluminum (Al), that is, the emitter electrode 30 An AlSi eutectic is generated in between, and the emitter-base junction is short-circuited to write information.

[Problems to be solved by the invention]

In the J-PROM described with reference to FIGS. 6 and 7, since the base region 27 is formed by applying photolithography technology to the emitter region 28, there is a margin for alignment between the two. Required, and the base region 27 and the collector contact region 29 are selectively thermally oxidized (eg, loca
Since they are separated by the isolation insulating film 25 formed by the lized oxidation of silicon (LOCOS) method, the distance between them is the minimum dimension of the mask plus bird's beak.

For this reason, a margin for mask alignment is required between the base region 27 and the collector contact region 29, and between the emitter region 28 and the base region 27, respectively. Since it does not become smaller than the minimum pattern, the size of the transistor cannot be reduced.

The present invention makes it possible to miniaturize a transistor as a memory cell by forming a collector region, a base region, and an emitter region by a self-alignment method.
Attempt to further integrate OM.

[Means for solving the problem]

In the method for manufacturing a semiconductor memory device according to the present invention,
Forming a collector extraction layer (for example, the collector extraction layer 6) and an interlayer insulating film (for example, the interlayer insulation film 7) on the exposed active region, and then selectively etching the interlayer insulation film and the collector extraction layer (For example, opening 6A) for forming base region and emitter region
Forming an insulating film, and then performing anisotropic etching to form a side wall film (for example, insulating film 8) covering the side wall of the opening, and then forming the insulating film twice through the opening. The base region (for example, base region 9) which does not exceed the thickness of the sidewall film by introducing impurities over the entire region and the emitter region (for example, emitter region 1) existing in the base region.
0).

[Action]

By adopting the above-mentioned means, the base, the emitter and the collector can be formed by a self-alignment method, and it is not necessary to consider a margin for alignment of the mask. It is possible to realize an area.

〔Example〕

FIGS. 1 to 5 are cutaway side views of a main part of a semiconductor memory device at important process steps for explaining an embodiment of the present invention, and will be described below with reference to these drawings.

See FIG. 1. (1) An n-type buried layer 2 is formed in a p-type silicon semiconductor substrate 1 by applying a normal technique.

(2) The thickness is, for example, 2.0 [μm] and the specific resistance is, for example, 0.5 [Ω · c] by applying the vapor phase epitaxial growth method.
m] is grown.

(3) By applying ordinary techniques, p
A p-type impurity is selectively introduced so as to reach the p-type silicon semiconductor substrate 1 to form a p-type element isolation region 4.

(4) An element isolation insulating film 5 made of SiO ₂ is formed by applying a selective thermal oxidation method (for example, a LOCOS method) using an oxidation-resistant mask such as a silicon nitride (Si ₃ N ₄ ) film.

(5) The mask at the time of performing the selective thermal oxidation method is removed, and the n-type silicon semiconductor layer 3 as an active region is exposed.

See Fig. 2 (6) Chemical vapor deposition:
By applying the CVD method, the thickness is, for example, 3000 [Å]
A collector lead layer 6 made of polycrystalline silicon doped with n-type impurities is formed. The sheet resistance of the collector lead layer 6 is, for example, 60 [Ω / □].
Degree.

In order to form the collector extraction layer 6 made of the impurity-containing polycrystalline silicon, a non-doped polycrystalline film may be formed, and then phosphorus (P) ions or arsenic (As) ions may be implanted. .

(7) By applying the CVD method, the thickness is, for example, 4000
[Å] An interlayer insulating film 7 made of SiO ₂ is formed.

(8) By applying a normal photolithography technique, the interlayer insulating film 7 and the collector extraction layer 6 are patterned to remove unnecessary portions and to form openings 6A for forming base regions and etching regions. Open the window.

See Fig. 3 (9) The thickness is, for example, 5000 by applying the CVD method.
[Å] An insulating film 8 made of SiO ₂ is formed.

(10) Anisotropic insulating film 8 made of SiO _{2 having} a thickness of 5000 [Å] by applying a reactive ion etching (RIE) method using CF ₄ + H ₂ as an etching gas. Conductive etching, leaving only the sidewall film,
Remove others.

See FIG. 4. (11) By applying the ion implantation method, the dose amount is, for example, about 3 × 10 ¹³ [cm ⁻² ], and the acceleration energy is, for example,
Implant boron (B) ions at 40 [KeV]
Then, arsenic (As) ions are implanted at a dose of about 5 × 10 ¹⁵ [cm ⁻² ] and an acceleration energy of, for example, 40 [KeV].

(12) A heat treatment at a temperature of 900 ° C. for a time of 20 minutes is performed to activate each of the impurities implanted in the step (11), so that the p-type base region 9 and the n-type emitter region that can actually operate are activated. Form 10.

By this heat treatment, the n-type impurity contained in the collector lead-out layer 6 is subjected to solid-solid diffusion to form an n-type collector / contact region 11.

Refer to FIG. 5. (13) The collector electrode contact window is formed by selectively etching the interlayer insulating film 7 by applying a normal photolithography technique.

(14) An Al film having a thickness of, for example, about 1 [μm] is formed by applying the sputtering method.

(15) The Al film is patterned to form an emitter electrode 12 and a collector electrode 13 by applying a normal photolithography technique.

It will be understood that, in the manufacturing process, the emitter region, the base region, and the collector / contact region can be formed with one mask in the process described with reference to FIG. Further, the same effect can be obtained by separating the mask for forming the collector lead-out layer and the mask used for opening the opening for forming the base region and the emitter region in the manufacturing process. Furthermore, in the above-described manufacturing process, the ion implantation method is applied to the formation of the base region 9 and the emitter region 10, but this is performed by applying the double diffusion method using polycrystalline silicon. Alternatively, the collector lead-out layer 6 may replace polycrystalline silicon with a refractory metal silicide or a refractory metal itself. In this case, a sufficient ohmic contact can be obtained without forming a collector contact region.

〔The invention's effect〕

In the method for manufacturing a semiconductor memory device according to the present invention,
Forming a collector lead layer and an interlayer insulating film on the active region, forming an opening in the interlayer insulating film and the collector lead layer, forming a side wall film covering a side wall of the opening, and forming the side wall film twice through the opening; By introducing impurities, a base region not exceeding the thickness of the side wall film and an emitter region are formed in the base region.

By adopting the above means, the base, emitter and collector are all formed by a self-alignment method, so there is no need to consider the margin of mask alignment, and furthermore, the base region and emitter region which are smaller than the minimum pattern width of the mask. Can be realized. Therefore, the transistor as the memory cell is miniaturized, and the J-PROM can be further highly integrated.

[Brief description of the drawings]

FIGS. 1 to 5 are cutaway side views of a main part of a semiconductor memory device at important points in a process for explaining an embodiment of the present invention.
FIG. 7 is a main part circuit diagram for explaining the configuration of the J-PROM, and FIG. 7 is a fragmentary side view for explaining the specific structure of the memory cell in the J-PROM. In the drawing, 1 is a p-type silicon semiconductor substrate, 2 is an n-type buried layer, 3 is an n-type silicon semiconductor layer, 4 is a p-type element isolation region, 5 is an element isolation insulating film, and 6 is a collector extraction layer. , 7 is an interlayer insulating film, 8 is an insulating film as a side wall film, 9 is a p-type base region, 10 is an n-type emitter region, 11 is an n-type collector contact region, 12 is an emitter electrode, and 13 is a collector electrode. Is shown.

Claims (1)

(57) [Claims] A step of forming a collector lead layer and an interlayer insulating film on the exposed active region; and selectively forming the base insulating layer and the emitter region by selectively etching the interlayer insulating film and the collector lead layer. Forming an opening for forming the insulating film, and then performing anisotropic etching to form a sidewall film covering the side wall of the opening, and then forming the insulating film through the opening twice. Forming a base region that does not exceed the thickness of the sidewall film and an emitter region in the base region by introducing impurities.