JP2609767B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2609767B2
JP2609767B2 JP3017867A JP1786791A JP2609767B2 JP 2609767 B2 JP2609767 B2 JP 2609767B2 JP 3017867 A JP3017867 A JP 3017867A JP 1786791 A JP1786791 A JP 1786791A JP 2609767 B2 JP2609767 B2 JP 2609767B2
Authority
JP
Japan
Prior art keywords
package
cap
chip
semiconductor chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3017867A
Other languages
Japanese (ja)
Other versions
JPH04256204A (en
Inventor
亮 熊谷
Original Assignee
山形日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 山形日本電気株式会社 filed Critical 山形日本電気株式会社
Priority to JP3017867A priority Critical patent/JP2609767B2/en
Publication of JPH04256204A publication Critical patent/JPH04256204A/en
Application granted granted Critical
Publication of JP2609767B2 publication Critical patent/JP2609767B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Waveguides (AREA)
  • Microwave Amplifiers (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
にマイクロ波周波数帯域で動作させるGaAs電界効果
トランジスタ(以下GaAsMES FETと記す)を
有する半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a GaAs field effect transistor (hereinafter referred to as a GaAs MES FET) operated in a microwave frequency band.

【0002】[0002]

【従来の技術】従来のGaAsMES FETを有する
半導体装置は、図2(a)に示すように、パッケージ3
の側壁上面に、セラミックもしくは、金属の板状のキャ
ップ2をAuSi等のソルダーで封止する構成となって
いた。このパッケージを導波管(周波数が高くなると、
中空の導体管の中を電磁波が通る様になる)と考えてパ
ッケージの寸法を設計するが、パッケージ内部には、マ
イクロ波周波数帯域における50Ω整合が得られる様に
ストリップ線路5や、チップコンデンサ6などの誘電体
が搭載される為、中空の比誘電率が短縮され、パッケー
ジの実用周波数が低下してしまう。
2. Description of the Related Art A conventional semiconductor device having a GaAs MES FET is, as shown in FIG.
A ceramic or metal plate-like cap 2 is sealed on the upper surface of the side wall with a solder such as AuSi. This package is connected to a waveguide (as the frequency increases,
The dimensions of the package are designed on the assumption that the electromagnetic waves pass through a hollow conductor tube), but the strip line 5 and the chip capacitor 6 are provided inside the package so as to obtain 50Ω matching in the microwave frequency band. Since such a dielectric material is mounted, the dielectric constant of the hollow is reduced, and the practical frequency of the package is reduced.

【0003】図3はパッケージの実用周波数特性の一例
を示す図である。このパッケージの実用周波数は、アイ
ソレーションロスが40dB取れるような周波数を目安
としている。
FIG. 3 is a diagram showing an example of a practical frequency characteristic of a package. The practical frequency of this package is a frequency at which an isolation loss of 40 dB can be obtained.

【0004】[0004]

【発明が解決しようとする課題】この従来の半導体装置
は、パッケージの実用周波数限界近傍で50Ω内部整合
回路を構成する場合、パッケージ自体のアイソレーショ
ンが不十分となり、内部の入出力間のミスマッチを生
じ、特性の低下をきたすという欠点がある。すなわち、
図3で示すアイソレーションが40dB取れる周波数f
は、パッケージの平面形状にみにより算出される共振周
波数(TM 110 モード)Fに内部の充填状態による補正
係数K(K<1)を掛けた値となり、補正係数Kは高比
誘電率のチップコンデンサやストリップ線路基板が占め
る容積に対して低比誘電率の中空が占める容積が短縮さ
れて小になると補正係数Kが小となり周波数fは低下す
る。例えばF=15GHzでもK=0.8となり、fが
12GHzに低下し、12GHz以下の周波数はアイソ
レーションが40dB取れるから実用出来る実用周波数
となるが、12GHzより高い周波数はアイソレーショ
ンが40dB取れないから実用することができない。
In this conventional semiconductor device, when a 50Ω internal matching circuit is formed near the practical frequency limit of the package, the isolation of the package itself becomes insufficient, and the mismatch between the internal input and output is reduced. This has the drawback of causing deterioration of characteristics. That is,
Frequency f at which the isolation shown in FIG.
Is the resonance circumference calculated from the planar shape of the package.
Correction of wave number (TM 110 mode) F by filling state inside
It is a value obtained by multiplying the coefficient K (K <1).
Dielectric chip capacitors and stripline substrates occupy
Volume occupied by hollows with low dielectric constant relative to volume
The correction coefficient K becomes smaller and the frequency f decreases.
You. For example, even if F = 15 GHz, K = 0.8, and f is
The frequency drops to 12 GHz, and frequencies below 12 GHz are
Practical frequency that can be used practically because it can take 40dB
However, frequencies higher than 12 GHz are isolated.
Cannot be put to practical use because 40 dB cannot be obtained.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
パッケージの内側底部に搭載した半導体チップと、前記
半導体チップの入力側と出力側にそれぞれ設けたチップ
コンデンサと、前記チップコンデンサ外側にそれぞれ設
けたストリップ線路と、前記ストリップ線路の外側にそ
れぞれ位置する前記パッケージの側壁と、それぞれの前
記ストリップ線路に接続して前記側壁を貫通して外部に
それぞれ1本づつ導出したリードと、前記パッケージを
封止するキャップとを備えてマイクロ波周波数帯域の電
気的整合を行う50Ω内部整合GaAs電界効果トラン
ジスタを有する半導体装置において、前記側壁の上面
前記キャップとの間に枠状のスペーサを設け、前記キャ
ップは前記半導体チップ上から前記一対のチップコンデ
ンサ上および前記一対のストリップ線路上を経て前記側
壁の上面に至るまで平坦の形状となっている。
According to the present invention, there is provided a semiconductor device comprising:
A semiconductor chip mounted on the inside bottom of the package, the
Chips provided on the input side and output side of the semiconductor chip respectively
Capacitor and the outside of the chip capacitor.
And a strip line outside the strip line.
The respective side walls of the package and in front of each
Connected to the strip line and penetrated through the side wall to the outside
In a semiconductor device having a 50Ω internal matching GaAs field-effect transistor for performing electrical matching in a microwave frequency band including a lead led out one by one and a cap for sealing the package, the upper surface of the side wall and the cap A frame-shaped spacer is provided between
The chip is connected to the pair of chip capacitors from above the semiconductor chip.
On the sensor and on the pair of strip lines
It has a flat shape up to the upper surface of the wall.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。
Next, the present invention will be described with reference to the drawings.

【0007】図1(a),(b)は本発明の一実施例を
示す一部切欠斜視図及びスペーサの斜視図である。
FIGS. 1A and 1B are a partially cutaway perspective view and a perspective view of a spacer showing an embodiment of the present invention.

【0008】図1(a),(b)に示すように、パッケ
ージ3の内側底部に搭載した半導体チップ7と、半導体
チップ7の入力側と出力側に設けて半導体チップ7と接
続したチップコンデンサ6と、チップコンデンサ6の入
力側と出力側に設けたストリップ線路5と、ストリップ
線路5の夫々に接続してパッケージ3の側壁9を貫通し
て外部に導出したリード4と、パッケージ3の側壁上面
に設けた枠状の無酸素銅からなり表面に金めっき層を有
するスペーサ1と、スペーサ1の上に設けてパッケージ
3を封止するキャップ2とを備えて構成される。
As shown in FIGS. 1A and 1B, a semiconductor chip 7 mounted on the inner bottom of the package 3 and a chip capacitor provided on the input and output sides of the semiconductor chip 7 and connected to the semiconductor chip 7 6, a strip line 5 provided on the input side and an output side of the chip capacitor 6, a lead 4 which is connected to each of the strip lines 5 and penetrates through the side wall 9 of the package 3 and extends to the outside, and a side wall of the package 3. It comprises a spacer 1 made of frame-shaped oxygen-free copper provided on the upper surface and having a gold plating layer on the surface, and a cap 2 provided on the spacer 1 to seal the package 3.

【0009】[0009]

【発明の効果】以上説明したように、本発明は、パッケ
ージの側壁上面とキャップとの間にスペーサを設けるこ
とにより、パッケージの実用周波数を整合して入出力回
路相互のアイソレーションを十分に確保し、これによ
り、特に、パッケージの実用周波数限界近傍でマイクロ
波周波数帯域の内部整合回路を構成する際の入出力間の
ミスマッチを防ぎ、ロスの少ない、安定した50Ω内部
整合GaAsMES FETを実現できるという効果を
有する。すなわち他の構成が図2と同じでも、スペーサ
を設けることにより図1では高比誘電率のチップコンデ
ンサやストリップ線路基板が占める容積に対して低比誘
電率の中空が占める容積が増大し補正係数Kが、例えば
0.9〜0.95と大きくなり、実用周波数限界の周波
数fを13.5GHz〜14.25GHzと高い周波数
にすることができる。また、必要な周波数と立体的実装
集積度の両者を考慮してスペーサを選択することによ
り、パッケージ本体およびキャップが同一でも種々の半
導体装置に対処することができ、生産性が向上する。
As described above, according to the present invention, by providing a spacer between the upper surface of the side wall of the package and the cap, the practical frequency of the package is matched and the isolation between the input / output circuits is sufficiently ensured. In this way, it is possible to prevent a mismatch between input and output when configuring an internal matching circuit in the microwave frequency band in the vicinity of the practical frequency limit of the package, and to realize a stable 50Ω internally matched GaAs MES FET with small loss. Has an effect. That is, even if the other configuration is the same as FIG.
In FIG. 1, a chip capacitor having a high relative dielectric constant is provided.
Low ratio to the volume occupied by the
The volume occupied by the hollow of the electric power increases and the correction coefficient K becomes, for example,
0.9 to 0.95, the frequency at the practical frequency limit
The number f is as high as 13.5 GHz to 14.25 GHz
Can be Also required frequency and three-dimensional implementation
By selecting spacers in consideration of both the degree of integration
Even if the package body and cap are the same,
The conductor device can be dealt with, and the productivity is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す一部切欠斜視図及びス
ペーサの斜視図である。
FIG. 1 is a partially cutaway perspective view and a perspective view of a spacer showing an embodiment of the present invention.

【図2】従来の半導体装置の一例を示す一部切欠斜視図
である。
FIG. 2 is a partially cutaway perspective view showing an example of a conventional semiconductor device.

【図3】パッケージの実用周波数特性の一例を示す図で
ある。
FIG. 3 is a diagram illustrating an example of a practical frequency characteristic of a package.

【符号の説明】[Explanation of symbols]

1 スペーサ 2 キャップ 3 パッケージ 4 リード 5 ストリップ線路 6 チップコンデンサ 7 半導体チップ 9 側壁 DESCRIPTION OF SYMBOLS 1 Spacer 2 Cap 3 Package 4 Lead 5 Strip line 6 Chip capacitor 7 Semiconductor chip 9 Side wall

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 パッケージの内側底部に搭載した半導体
チップと、前記半導体チップの入力側と出力側にそれぞ
れ設けたチップコンデンサと、前記チップコンデンサ外
側にそれぞれ設けたストリップ線路と、前記ストリップ
線路の外側にそれぞれ位置する前記パッケージの側壁
と、それぞれの前記ストリップ線路に接続して前記側壁
を貫通して外部にそれぞれ1本づつ導出したリードと、
前記パッケージを封止するキャップとを備えてマイクロ
波周波数帯域の電気的整合を行う50Ω内部整合GaA
s電界効果トランジスタを有する半導体装置において、前記側壁の上面と 前記キャップとの間に枠状のスペーサ
を設け、前記キャップは前記半導体チップ上から前記一
対のチップコンデンサ上および前記一対のストリップ線
路上を経て前記側壁の上面に至るまで平坦の形状となっ
ていることを特徴とする半導体装置。
1. A semiconductor chip mounted on an inner bottom of a package, and an input side and an output side of the semiconductor chip, respectively.
And the chip capacitor provided outside the chip capacitor
A strip line provided on each side and the strip
Side walls of the package respectively located outside the tracks
And the side walls connected to the respective strip lines.
, And leads led out one by one to the outside,
A 50Ω internal matching GaAs for providing electrical matching in a microwave frequency band with a cap for sealing the package.
In a semiconductor device having an s field effect transistor, a frame-shaped spacer is provided between an upper surface of the side wall and the cap.
And the cap is placed on the semiconductor chip from above
On a pair of chip capacitors and said pair of strip lines
It becomes a flat shape up to the upper surface of the side wall through the road
Wherein a is.
JP3017867A 1991-02-08 1991-02-08 Semiconductor device Expired - Fee Related JP2609767B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3017867A JP2609767B2 (en) 1991-02-08 1991-02-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3017867A JP2609767B2 (en) 1991-02-08 1991-02-08 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH04256204A JPH04256204A (en) 1992-09-10
JP2609767B2 true JP2609767B2 (en) 1997-05-14

Family

ID=11955620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3017867A Expired - Fee Related JP2609767B2 (en) 1991-02-08 1991-02-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2609767B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02100344A (en) * 1988-10-06 1990-04-12 Toshiba Corp Semiconductor device for microwave use
JPH0480101U (en) * 1990-11-26 1992-07-13

Also Published As

Publication number Publication date
JPH04256204A (en) 1992-09-10

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Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19961217

LAPS Cancellation because of no payment of annual fees