JPH11312751A - Package for high-frequency circuit - Google Patents

Package for high-frequency circuit

Info

Publication number
JPH11312751A
JPH11312751A JP10117580A JP11758098A JPH11312751A JP H11312751 A JPH11312751 A JP H11312751A JP 10117580 A JP10117580 A JP 10117580A JP 11758098 A JP11758098 A JP 11758098A JP H11312751 A JPH11312751 A JP H11312751A
Authority
JP
Japan
Prior art keywords
conductor layer
ground conductor
package
frequency circuit
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10117580A
Other languages
Japanese (ja)
Other versions
JP3618046B2 (en
Inventor
Katsuyuki Yoshida
克亨 吉田
Chihiro Makihara
千尋 牧原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP11758098A priority Critical patent/JP3618046B2/en
Publication of JPH11312751A publication Critical patent/JPH11312751A/en
Application granted granted Critical
Publication of JP3618046B2 publication Critical patent/JP3618046B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Waveguides (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a package for high-frequency circuit, which is low in the reflection losses in the input/output part of a high-frequency signal, can also be shielded from electromagnetic waves and has low-loss transmission characteristics for the high-frequency signal. SOLUTION: This package is for the high-frequency circuit of a structure, wherein the package is provided with an insulating board 21, having a lower ground conductor layer 26 and a mounting part 21a for a high-frequency circuit component 28, a line conductor 24 and the same surface ground conductor layers 25, which are provided from the vicinity of the mounting part 21a, extending over the vicinity of the outer periphery of the mounting part 21a, and an insulating frame body 22, which is bonded on the board 21 and is formed with an upper ground conductor layer 27, and with castellation conductors 32, which connect the layers 25 with the layer 27, formed on the inner and outer side surfaces of the frame body 22, through conductors, which connect the layers 25 with the layer 26 are respectively formed in the parts, which are located directly under the conductors 32 of the insulating board 21. The ground state of the package is stable, and the reflection loss and radiation loss of the package can be reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高周波帯で用いら
れる高周波用半導体素子や高周波回路等の高周波回路部
品を収容するための高周波回路用パッケージに関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency circuit package for accommodating high-frequency circuit components such as high-frequency semiconductor elements and high-frequency circuits used in a high-frequency band.

【0002】[0002]

【従来の技術】MHz帯またはGHz帯の高周波帯で動
作する高周波半導体素子や高周波回路等の高周波回路部
品を収容するために用いられる高周波回路用パッケージ
には、従来、例えば図5に分解斜視図で、および図6に
その要部平面図で示すようなものがあった。
2. Description of the Related Art A high-frequency circuit package used for accommodating high-frequency circuit components such as a high-frequency semiconductor element or a high-frequency circuit operating in a high-frequency band of a MHz band or a GHz band is conventionally shown in, for example, FIG. And FIG. 6 shows a plan view of the main part.

【0003】図5および図6において、1はセラミック
等から成り上面に高周波用半導体素子を搭載し収容する
搭載部1aを有する絶縁基板、2はセラミック等から成
り絶縁基板1上に搭載部1aを囲むように接合されて収
容部の側壁となる絶縁枠体、3は収容部を気密封止する
ための蓋体であり、これら絶縁基板1と絶縁枠体2と蓋
体3とにより高周波用半導体素子を収容するための収容
部9が形成される。
In FIGS. 5 and 6, reference numeral 1 denotes an insulating substrate having a mounting portion 1a made of ceramic or the like and having an upper surface on which a high-frequency semiconductor element is mounted and accommodated, and 2 denotes a mounting portion 1a made of ceramic or the like on an insulating substrate 1. The insulating frame 3, which is joined so as to surround and serves as a side wall of the housing, is a lid for hermetically sealing the housing. The insulating substrate 1, the insulating frame 2, and the lid 3 form a semiconductor for high frequency. An accommodating portion 9 for accommodating the element is formed.

【0004】4は搭載部1a近傍から絶縁基板1の外周
近傍にかけて収容部9の内外を導通するように配設され
た高周波信号を伝送するための線路導体、5・5は線路
導体4の両側に併設された同一面接地導体層であり、こ
れら線路導体4および同一面接地導体層5・5の一部は
絶縁基板1と絶縁枠体2とに挟まれて気密封止部を構成
している。6は絶縁基板1の下面に形成された下部接地
導体層、7は絶縁枠体2の上面に形成された上部接地導
体層である。8は搭載部1aに搭載され収容部9内に収
容された高周波用半導体素子であり、その電極10と線路
導体4および同一面接地導体層5・5の収容部9内に露
出した部位とがボンディングワイヤ11を介して電気的に
接続される。
Reference numeral 4 denotes a line conductor for transmitting a high-frequency signal disposed so as to conduct inside and outside of the housing 9 from the vicinity of the mounting portion 1a to the vicinity of the outer periphery of the insulating substrate 1; The line conductor 4 and a part of the same-surface ground conductor layers 5 and 5 are sandwiched between the insulating substrate 1 and the insulating frame 2 to form a hermetically sealed portion. I have. Reference numeral 6 denotes a lower ground conductor layer formed on the lower surface of the insulating substrate 1, and reference numeral 7 denotes an upper ground conductor layer formed on the upper surface of the insulating frame 2. Reference numeral 8 denotes a high-frequency semiconductor device mounted on the mounting portion 1a and housed in the housing portion 9, and its electrode 10 and the line conductor 4 and the portions of the same-surface ground conductor layers 5.5 exposed in the housing portion 9 are formed. They are electrically connected via bonding wires 11.

【0005】このような従来の高周波回路用パッケージ
においては、高周波信号の入出力部の構成は、高周波信
号が伝送される線路導体4と、これを挟んで絶縁基板1
の同一面上で両側に併設された同一面接地導体層5・5
と、絶縁基板1下面の下部接地導体層6と、絶縁枠体2
上面の上部接地導体層7とから成り、線路導体4および
同一面接地導体層5・5が絶縁枠体2と絶縁基板1とに
挟持された部分(気密封止部)では上下グランド付きコ
プレーナ線路構造となり、絶縁枠体2の両側の部分では
下グランド付きコプレーナ線路構造となっている。
In such a conventional package for a high-frequency circuit, the configuration of the input / output portion of the high-frequency signal includes a line conductor 4 for transmitting the high-frequency signal and an insulating substrate 1 with the line conductor 4 interposed therebetween.
Ground conductor layers 5.5 provided on both sides on the same plane
And a lower grounding conductor layer 6 on the lower surface of the insulating substrate 1 and an insulating frame 2
A coplanar line with upper and lower grounds is provided at a portion (airtightly sealed portion) where the line conductor 4 and the same-surface ground conductor layer 5.5 are sandwiched between the insulating frame 2 and the insulating substrate 1. A coplanar line structure with a lower ground is formed on both sides of the insulating frame 2.

【0006】なお、このような高周波信号の入出力部に
おいて、同一面接地導体層5・5と接地との電気的な接
続は、例えば図6に示すように、絶縁枠体2の下に位置
する絶縁基板1内に形成されたビア導体等の貫通導体12
により下部接地導体層6と電気的に接続することによっ
て行なわれていた。
In such a high frequency signal input / output section, the electrical connection between the same plane ground conductor layers 5 and the ground is located below the insulating frame 2 as shown in FIG. Through conductors 12 such as via conductors formed in insulating substrate 1
This is performed by electrically connecting the lower ground conductor layer 6 with the lower ground conductor layer 6.

【0007】[0007]

【発明が解決しようとする課題】このような従来の高周
波回路用パッケージにおいては、気密封止部では線路導
体4の上部に存在する絶縁枠体2の誘電率に応じて線路
導体4の特性インピーダンスがその両側の部分よりも低
下するため、それらの間で特性インピーダンスの不整合
が生じ、高周波信号の反射損失が増大して高周波信号の
伝送特性が劣化するという問題点があった。
In such a conventional high-frequency circuit package, the characteristic impedance of the line conductor 4 depends on the dielectric constant of the insulating frame 2 existing above the line conductor 4 in the hermetically sealed portion. However, there is a problem that characteristic impedance mismatching occurs between them, so that reflection loss of a high-frequency signal increases and transmission characteristics of a high-frequency signal deteriorate.

【0008】このため、気密封止部とその両側の部分と
で特性インピーダンスの整合を図る技術が提案され、例
えば特公平8−12887 号公報では、平衡型ストリップ線
路構造(上下グランド付きコプレーナ線路構造)となる
気密封止配線部分の配線の幅を、他のマイクロストリッ
プ線路構造(下グランド付きコプレーナ線路構造)とな
る内部配線部分の配線の幅よりも狭くする方法が提案さ
れている。
For this reason, there has been proposed a technique for matching the characteristic impedance between the hermetic sealing portion and the portions on both sides thereof. For example, Japanese Patent Publication No. 8-12887 discloses a balanced strip line structure (a coplanar line structure with upper and lower grounds). A method has been proposed in which the width of the wiring in the hermetically sealed wiring portion is narrower than the width of the wiring in the internal wiring portion that forms another microstrip line structure (coplanar line structure with lower ground).

【0009】これによれば、気密封止配線部分の幅を内
部配線部分の幅より狭くしたことにより、内部配線部分
と気密封止配線部分との特性インピーダンスを整合させ
ることができ、また、外部端子の特性インピーダンスと
の整合をとることもできて、高速信号の伝搬特性を改善
することができる利点があるというものである。
According to this, since the width of the hermetically sealed wiring portion is made smaller than the width of the internal wiring portion, the characteristic impedance of the internal wiring portion and the characteristic impedance of the hermetically sealed wiring portion can be matched. There is an advantage that the impedance can be matched with the characteristic impedance of the terminal, and the propagation characteristic of a high-speed signal can be improved.

【0010】しかしながら、このような方法により気密
封止配線部分の配線とその両側の部分に当たる内部配線
部分の配線との特性インピーダンスを整合させた場合で
あっても、線路導体が気密封止部へ出入りする部分(図
6中にAおよびBで示す絶縁枠体2の側壁直下の部分)
では上部接地導体層7と同一面接地層5と下部接地導体
層6とが直接接続されていないことにより接地状態が不
安定となる傾向があるため、この部分で局部的に特性イ
ンピーダンスが変化して反射損失を生じることとなり、
また、この部分で高周波信号のシールド効果が不十分と
なって放射損失を生じることとなるため、これらの損失
によって高周波信号の伝送特性が劣化するという問題点
があった。
However, even when the characteristic impedance of the wiring of the hermetically sealed wiring portion and the wiring of the internal wiring portion corresponding to the portions on both sides thereof are matched by such a method, the line conductor moves to the hermetically sealed portion. Portion (portion immediately below the side wall of the insulating frame 2 indicated by A and B in FIG. 6)
In this case, since the upper ground conductor layer 7, the same plane ground layer 5, and the lower ground conductor layer 6 are not directly connected to each other, the ground state tends to be unstable, and the characteristic impedance locally changes at this portion. Will cause reflection loss,
In addition, since the shielding effect of the high-frequency signal is insufficient at this portion and radiation loss occurs, there is a problem that the transmission characteristics of the high-frequency signal are deteriorated by these losses.

【0011】本発明は上記問題点に鑑みて案出されたも
のであり、その目的は、高周波信号の入出力部における
反射損失が低く、かつ電磁波シールドも可能で、高周波
信号に対して低損失な伝送特性を有する高周波回路用パ
ッケージを提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the reflection loss at the input / output portion of a high-frequency signal, to enable electromagnetic shielding, and to reduce the loss to a high-frequency signal. An object of the present invention is to provide a high-frequency circuit package having excellent transmission characteristics.

【0012】[0012]

【課題を解決するための手段】本発明の高周波回路用パ
ッケージは、下面に下部接地導体層が形成され、上面に
高周波回路部品が搭載される搭載部を有する絶縁基板
と、この絶縁基板の前記搭載部近傍から外周近傍にかけ
て配設された線路導体および該線路導体の両側に併設さ
れた同一面接地導体層と、前記絶縁基板上に前記搭載部
を囲むとともに前記線路導体および前記同一面接地導体
層の一部を挟んで接合され、上面に上部接地導体層が形
成された絶縁枠体とを具備し、前記絶縁枠体の内外側面
に前記同一面接地導体層と前記上部接地導体層とを接続
するキャスタレーション導体を形成するとともに、この
キャスタレーション導体直下の前記絶縁基板にそれぞれ
前記同一面接地導体層と前記下部接地導体層とを接続す
る貫通導体を形成したことを特徴とするものである。
According to the present invention, there is provided a high-frequency circuit package comprising: an insulating substrate having a lower grounding conductor layer formed on a lower surface and a mounting portion on which a high-frequency circuit component is mounted on an upper surface; A line conductor disposed from the vicinity of the mounting portion to the vicinity of the outer periphery, a coplanar ground conductor layer provided on both sides of the line conductor, the line conductor and the coplanar ground conductor surrounding the mounting portion on the insulating substrate; An insulating frame having an upper grounding conductor layer formed on an upper surface thereof, wherein the same plane grounding conductor layer and the upper grounding conductor layer are formed on inner and outer surfaces of the insulating frame. Forming a castellation conductor to be connected, and forming a through conductor for connecting the same-plane ground conductor layer and the lower ground conductor layer to the insulating substrate immediately below the castellation conductor, respectively. It is characterized in.

【0013】本発明の高周波回路用パッケージによれ
ば、高周波信号を伝送するための線路導体に対して、絶
縁基板と絶縁枠体とに挟まれた気密封止部において、絶
縁基板を介して下部接地導体層を、絶縁枠体を介して上
部接地導体層を配し、また、その両側に同一面接地導体
層を併設し、さらに、絶縁枠体の内外側面に同一面接地
導体層と上部接地導体層とを接続するキャスタレーショ
ン導体を形成するとともに、このキャスタレーション導
体直下の絶縁基板にそれぞれ同一面接地導体層と下部接
地導体層とを接続する貫通導体を形成したことから、線
路導体が絶縁枠体の内外側面において気密封止部に出入
りする部分の線路構成が疑似導波管構造となる。その結
果、線路導体を取り囲む接地のための導体について接地
状態を安定させて反射損失を低減することができるとと
もに、電磁波シールド効果を高めて放射損失を抑制する
ことができ、それにより、高周波信号の入出力部におけ
る高周波信号の伝送特性を低損失で良好なものとするこ
とができる。
According to the high-frequency circuit package of the present invention, a lower portion of the line conductor for transmitting the high-frequency signal is provided in the hermetically sealed portion sandwiched between the insulating substrate and the insulating frame via the insulating substrate. The grounding conductor layer is provided with an upper grounding conductor layer via an insulating frame, and a coplanar grounding conductor layer is provided on both sides of the grounding conductor layer. Since the castellation conductors connecting the conductor layers were formed, and the through conductors connecting the same-plane ground conductor layer and the lower ground conductor layer were formed on the insulating substrate immediately below the castellation conductors, the line conductor was insulated. The line configuration of a portion of the inner and outer surfaces of the frame that enters and exits the hermetic sealing portion has a pseudo waveguide structure. As a result, it is possible to stabilize the grounding state of the conductor for grounding surrounding the line conductor to reduce the reflection loss, and to enhance the electromagnetic wave shielding effect to suppress the radiation loss. The transmission characteristics of the high-frequency signal at the input / output unit can be improved with low loss.

【0014】[0014]

【発明の実施の形態】以下、本発明を図面に基づき説明
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

【0015】図1は本発明の高周波回路用パッケージの
実施の形態の一例を示す分解斜視図であり、図2はその
要部平面図である。また、図3は図2のC−C’線断面
図、図4は図2のD−D’線断面図である。
FIG. 1 is an exploded perspective view showing an example of an embodiment of a high-frequency circuit package according to the present invention, and FIG. 2 is a plan view of a main part thereof. FIG. 3 is a cross-sectional view taken along line CC ′ of FIG. 2, and FIG. 4 is a cross-sectional view taken along line DD ′ of FIG.

【0016】これらの図において21は上面に高周波回路
部品が搭載される搭載部21aを有する絶縁基板、22は絶
縁基板21上に搭載部21aを囲むように接合されて内側に
高周波回路部品を収容する収容部の側壁となる絶縁枠体
である。これら絶縁基板21と絶縁枠体22とにより高周波
用半導体素子を収容する収容部29が形成され、高周波回
路部品28を搭載部21aに搭載し、この収容部29を塞くよ
うにして蓋体23を絶縁枠体22の上面に接合することによ
り、収容部29の内部に高周波回路部品28が気密封止され
て収容される。
In these figures, reference numeral 21 denotes an insulating substrate having a mounting portion 21a on the upper surface of which a high-frequency circuit component is mounted, and 22 denotes an insulating substrate 21 which is bonded to surround the mounting portion 21a and accommodates the high-frequency circuit component inside. It is an insulating frame which becomes a side wall of the accommodating part. An accommodating portion 29 for accommodating the high-frequency semiconductor element is formed by the insulating substrate 21 and the insulating frame 22, the high-frequency circuit component 28 is mounted on the mounting portion 21a, and the lid 23 is closed so as to cover the accommodating portion 29. Is bonded to the upper surface of the insulating frame body 22, so that the high-frequency circuit component 28 is hermetically sealed and housed inside the housing portion 29.

【0017】24は搭載部21a近傍から絶縁基板21の外周
近傍にかけて収容部29の内外を導通するように配設され
た高周波信号を伝送するための線路導体、25・25は線路
導体24の両側に併設された同一面接地導体層であり、こ
れら線路導体24および同一面接地導体層25・25の一部は
絶縁基板21と絶縁枠体22とに挟まれて気密封止部を構成
している。26は絶縁基板21の下面に形成された下部接地
導体層、27は絶縁枠体22の上面に形成された上部接地導
体層である。28は搭載部21aに搭載され収容部29内に収
容された高周波用半導体素子や高周波回路等の高周波回
路部品であり、その電極30と線路導体24および同一面接
地導体層25・25の収容部29内に露出した部位とがボンデ
ィングワイヤ31を介して電気的に接続される。
Reference numeral 24 denotes a line conductor for transmitting a high-frequency signal disposed so as to conduct inside and outside the housing portion 29 from the vicinity of the mounting portion 21a to the vicinity of the outer periphery of the insulating substrate 21. The line conductor 24 and a part of the same-plane ground conductor layers 25 and 25 are sandwiched between the insulating substrate 21 and the insulating frame 22 to form a hermetic sealing portion. I have. 26 is a lower ground conductor layer formed on the lower surface of the insulating substrate 21, and 27 is an upper ground conductor layer formed on the upper surface of the insulating frame 22. Reference numeral 28 denotes a high-frequency circuit component such as a high-frequency semiconductor element or a high-frequency circuit mounted on the mounting portion 21a and housed in the housing portion 29. The electrode 30 and the line conductor 24 and the housing portion of the same-surface ground conductor layer 25 The portion exposed in 29 is electrically connected via bonding wire 31.

【0018】また、32は絶縁枠体22上面の上部接地導体
層27と同一面接地導体層25・25とを絶縁枠体22の内外側
面で電気的に接続するキャスタレーション導体であり、
例えば絶縁枠体22の内外側面に設けられた凹部表面に導
体層を被着させることにより形成される。そして、33は
同一面接地導体層25・25と絶縁基板21下面の下部接地導
体層26とをキャスタレーション導体32の直下でそれぞれ
電気的に接続するスルーホール導体やビア導体等の貫通
導体である。
Reference numeral 32 denotes a castellation conductor for electrically connecting the upper ground conductor layer 27 on the upper surface of the insulating frame 22 and the same ground conductor layers 25, 25 on the inner and outer surfaces of the insulating frame 22,
For example, it is formed by applying a conductor layer to the surface of a concave portion provided on the inner and outer surfaces of the insulating frame 22. Reference numeral 33 denotes through conductors such as through-hole conductors and via conductors that electrically connect the same-plane ground conductor layers 25 and 25 and the lower ground conductor layer 26 on the lower surface of the insulating substrate 21 directly below the castellation conductor 32, respectively. .

【0019】このような本発明の高周波回路用パッケー
ジにおいては、絶縁基板21と絶縁枠体22とが線路導体24
および同一面接地導体層25・25の一部を挟んで接合され
て構成された気密封止部において、線路導体24が気密封
止部に出入りする部分で、上部接地導体層27とキャスタ
レーション導体32・32と同一面接地導体層25・25と貫通
導体33・33と下部接地導体層26とにより、高周波信号を
伝送する線路導体24を取り囲むようにして接地状態の連
続した導体が形成されていることから、この部分の線路
構成が疑似導波管線路の構成となる。その結果、線路導
体24を取り囲む接地のための導体について接地状態を安
定させて気密封止部における高周波信号の反射損失を低
減することができるとともに、電磁波シールド効果を高
めて放射損失を抑制することができ、また、高次モード
の発生を抑制することができる。
In such a high-frequency circuit package of the present invention, the insulating substrate 21 and the insulating frame 22 are
In the hermetically sealed portion formed by joining a part of the grounded conductor layers 25 and 25 on the same plane, the upper grounded conductor layer 27 and the castellation conductor The ground conductors 25 and 25, the through conductors 33 and 33, and the lower ground conductor layer 26, which are on the same plane as 32 and 32, form a continuous conductor in a ground state so as to surround the line conductor 24 that transmits a high-frequency signal. Therefore, the line configuration of this portion becomes the configuration of the pseudo waveguide line. As a result, it is possible to stabilize the grounding state of the conductor for grounding surrounding the line conductor 24 and reduce the reflection loss of the high-frequency signal in the hermetic sealing part, and to suppress the radiation loss by enhancing the electromagnetic wave shielding effect. And the generation of higher-order modes can be suppressed.

【0020】それにより、高周波信号の入出力部におけ
る高周波信号の反射損失および放射損失を抑え、伝送特
性の劣化を抑えて、低損失で良好な伝送特性を有する高
周波回路用パッケージとなる。
As a result, the reflection loss and radiation loss of the high-frequency signal in the input / output section of the high-frequency signal are suppressed, and the deterioration of the transmission characteristics is suppressed, so that a high-frequency circuit package having low loss and good transmission characteristics is obtained.

【0021】本発明の高周波回路用パッケージにおい
て、絶縁基板21および絶縁枠体22としては、例えばアル
ミナやムライト等のセラミックス材料やガラスセラミッ
クス等の無機系材料、あるいはテフロン(PTFE)・
ガラスエポキシ・ポリイミド等の樹脂系材料などが用い
られる。これら絶縁基板21および絶縁枠体22の形状・寸
法(厚みや幅・長さ)は、使用される高周波信号の周波
数や特性インピーダンスなどに応じて適宜設定される。
In the high-frequency circuit package of the present invention, the insulating substrate 21 and the insulating frame 22 are made of, for example, a ceramic material such as alumina or mullite, an inorganic material such as glass ceramic, or Teflon (PTFE).
Resin-based materials such as glass epoxy and polyimide are used. The shapes and dimensions (thickness, width, and length) of the insulating substrate 21 and the insulating frame 22 are appropriately set according to the frequency and characteristic impedance of the high-frequency signal used.

【0022】なお、絶縁枠体22と絶縁基板21とには通常
は同じ材料を用いればよいが、異なる材料を用いて絶縁
枠体22の誘電率と絶縁基板21の誘電率とを異ならせても
よい。この場合は、例えば、絶縁基板21よりも絶縁枠体
22の誘電率が低い方が好ましく、絶縁枠体22の誘電率を
なるべく真空の誘電率に近づけるのがよい。それによ
り、絶縁基板21と絶縁枠体22との接合部分とそれ以外の
部分とにおける高周波信号の伝搬モードの変化が小さく
なり、伝送損失が小さくなるという点で好ましいものと
なる。
The insulating frame 22 and the insulating substrate 21 may be usually made of the same material, but different materials are used to make the dielectric constant of the insulating frame 22 different from that of the insulating substrate 21. Is also good. In this case, for example, the insulating frame body is
The dielectric constant of the insulating frame 22 is preferably low, and the dielectric constant of the insulating frame 22 is preferably as close as possible to the vacuum dielectric constant. This is preferable in that the change in the propagation mode of the high-frequency signal at the junction between the insulating substrate 21 and the insulating frame 22 and the other portions is reduced, and the transmission loss is reduced.

【0023】線路導体24は高周波線路導体用の金属材
料、例えばCuやMoMn+Ni+Au、W+Ni+A
u、Cr+Cu、Cr+Cu+Ni+Au、Ta2 N+
NiCr+Au、Ti+Pd+Au、NiCr+Pd+
Auなどを用いて厚膜印刷法あるいは各種の薄膜形成方
法やメッキ処理法などにより形成され、その厚みや幅も
伝送される高周波信号の周波数や特性インピーダンスな
どに応じて適宜設定される。なお、絶縁枠体22と絶縁基
板21との接合部における線路導体24の線路幅はそれ以外
の部分での線路幅よりも狭くしてもよく、その場合、そ
れらの幅は理想とする特性インピーダンスに対応する幅
からそれ以外の部分での線路幅までの間で必要とする仕
様に応じて適宜設定される。
The line conductor 24 is a metal material for a high-frequency line conductor, for example, Cu, MoMn + Ni + Au, W + Ni + A
u, Cr + Cu, Cr + Cu + Ni + Au, Ta 2 N +
NiCr + Au, Ti + Pd + Au, NiCr + Pd +
It is formed by a thick film printing method or various thin film forming methods or a plating method using Au or the like, and its thickness and width are appropriately set according to the frequency and characteristic impedance of the transmitted high-frequency signal. The line width of the line conductor 24 at the joint between the insulating frame 22 and the insulating substrate 21 may be narrower than the line width at other portions. Is set as appropriate according to the required specifications from the width corresponding to the line width to the line width in other portions.

【0024】また、同一面接地導体層25は線路導体24と
同様の材料で同様の方法により形成すればよく、線路導
体24と同一面接地導体層25との間隔は一般的な同一面接
地導体層を設ける場合の標準的な設定とすればよい。さ
らに、絶縁枠体22と絶縁基板21との接合部において同一
面接地導体層25を線路導体24に向けて等間隔に突出させ
るなどして特性インピーダンスの整合をより精密に行な
ってもよく、そのような場合には電磁界的影響度を考慮
して必要とする特性に応じて適宜設定すればよい。
The same plane ground conductor layer 25 may be formed of the same material as the line conductor 24 by the same method, and the distance between the line conductor 24 and the same plane ground conductor layer 25 is the same as that of a common plane ground conductor. The standard setting when providing a layer may be used. Further, at the joint between the insulating frame 22 and the insulating substrate 21, the same-surface ground conductor layer 25 may be protruded at equal intervals toward the line conductor 24, so that the characteristic impedance may be more precisely matched. In such a case, an appropriate setting may be made according to the required characteristics in consideration of the degree of electromagnetic field influence.

【0025】下部接地導体層26および上部接地導体層27
は、線路導体24や同一面接地導体層25と同様の材料を用
いて同様の方法により被着形成すればよい。なお、これ
らは導体被膜層として形成される場合の他に、他の導電
部材、例えば金属板や金属ブロックを取着することによ
り形成してもよい。
Lower ground conductor layer 26 and upper ground conductor layer 27
May be formed using the same material as the line conductor 24 and the same-surface ground conductor layer 25 by the same method. These may be formed by attaching another conductive member, for example, a metal plate or a metal block, in addition to the case where they are formed as a conductor coating layer.

【0026】キャスタレーション導体32は、同一面接地
導体層25の直上の絶縁枠体22の内外側面のそれぞれに形
成された凹部等に上部接地導体層27と同一面接地導体層
25とを電気的に接続するように形成され、上記の各導体
層と同様の材料を用いて同様の方法により被着形成すれ
ばよく、また、他の導電部材、例えば金属板や金属ブロ
ックを取着することにより形成してもよい。
The castellation conductor 32 is provided in a recess or the like formed on each of the inner and outer surfaces of the insulating frame 22 directly above the same-plane ground conductor layer 25 and is flush with the upper ground conductor layer 27.
25 and is formed so as to be electrically connected to each other, and may be formed by applying the same method using the same material as each of the above-described conductor layers, and other conductive members, for example, a metal plate or a metal block. It may be formed by attaching.

【0027】また、貫通導体33は、キャスタレーション
導体32直下の絶縁基板21内にそれぞれ同一面接地導体層
25と下部接地導体層26とを電気的に接続するように形成
され、例えばスルーホール導体やビア導体を形成するこ
とにより、あるいは金属板や金属棒、金属パイプ等を埋
設することにより形成すればよい。
Further, the through conductors 33 are provided on the insulating substrate 21 immediately below the castellation conductors 32 in the same plane ground conductor layer.
25 and the lower ground conductor layer 26 are formed so as to be electrically connected, for example, by forming a through-hole conductor or a via conductor, or by embedding a metal plate, a metal rod, or a metal pipe. Good.

【0028】本発明の高周波回路用パッケージの作製に
あたっては、例えば絶縁基板21および絶縁枠体22がガラ
スセラミックスから成る場合であれば、まず絶縁基板21
となるガラスセラミツクスのグリーンシートを準備し、
これに所定の打ち抜き加工を施して貫通導体となる貫通
孔を形成した後、スクリーン印刷法により銅や銀などの
低電気抵抗の導体ペーストを貫通孔に充填するとともに
所定の線路導体パターンおよび導体層パターンの形状に
印刷塗布する。次いで、別途準備したガラスセラミック
スのグリーンシートをその側面にキャスタレーション導
体32を形成する凹部が形成されるようにして枠状に打ち
抜くとともに、絶縁基板21となるグリーンシートの上面
に高周波用半導体素子28の収容部29が形成されるように
して積層して密着し、最後にこれらを約1000℃で一体焼
成することにより製作される。
In manufacturing the high-frequency circuit package of the present invention, if the insulating substrate 21 and the insulating frame 22 are made of glass ceramic, for example,
Prepare a green sheet of glass ceramics that will be
After a predetermined punching process is performed on this to form a through-hole serving as a through-conductor, a low-resistance conductive paste such as copper or silver is filled into the through-hole by a screen printing method, and a predetermined line conductor pattern and a conductor layer are formed. Print and apply to the pattern shape. Next, a separately prepared glass-ceramic green sheet is punched out in a frame shape so that a concave portion for forming the castellation conductor 32 is formed on a side surface thereof, and a high-frequency semiconductor element 28 is formed on the upper surface of the green sheet serving as the insulating substrate 21. Are laminated and adhered so that the accommodating section 29 is formed, and finally, they are integrally fired at about 1000 ° C.

【0029】また、キャスタレーション導体32間のギャ
ップgは、下記式の範囲で表わされるギャップg0 より
も小さな値としておくと、共振による高周波信号の減衰
を避けることができるため、線路導体24を伝送させる高
周波信号の周波数において、その伝送特性を優れたもの
とすることができる。 g0 =C0 /2f・√εreff ただし、g0 は共振の発生するキャスタレーション導体
32間ギャップ、C0 は光速、fは高周波信号の周波数、
εreffは絶縁枠体22および絶縁基板21の比誘電率を合成
した比誘電率である。
If the gap g between the castellation conductors 32 is set to a value smaller than the gap g 0 expressed by the following equation, attenuation of high-frequency signals due to resonance can be avoided. At the frequency of the high-frequency signal to be transmitted, its transmission characteristics can be improved. g 0 = C 0 / 2f · √ε reff where g 0 is a castellation conductor where resonance occurs.
32 gap, C0 is the speed of light, f is the frequency of the high-frequency signal,
ε reff is a relative dielectric constant obtained by combining the relative dielectric constants of the insulating frame 22 and the insulating substrate 21.

【0030】また、図1および図2に示した高周波回路
用パッケージのように、キャスタレーション導体32を絶
縁枠体22側面の凹部に形成する場合は、凹部を絶縁枠体
22の中央部に向かって深く形成するほど、より長い距離
にわたって疑似導波管構造となるため接地状態がより安
定するようになり、高周波信号の伝送特性をより優れた
ものとすることができる。従って、キャスタレーション
導体32が形成される絶縁枠体22側面の凹部は、収容部29
内の気密封止を維持できる範囲でできる限り深く形成す
ることが望ましい。
When the castellation conductor 32 is formed in a concave portion on the side of the insulating frame 22 as in the high-frequency circuit package shown in FIGS.
As the depth increases toward the center of 22, the pseudo-waveguide structure extends over a longer distance, so that the grounding state becomes more stable and the transmission characteristics of high-frequency signals can be further improved. Therefore, the concave portion on the side surface of the insulating frame body 22 where the castellation conductor 32 is formed
It is desirable to form as deep as possible as long as the hermetic seal inside can be maintained.

【0031】このような高周波回路用パッケージを用い
て、その搭載部21aに高周波回路部品28を搭載し、その
電極30をボンディングワイヤ31やボンディングリボン等
を介して収容部29内に位置する線路導体24および同一面
接地導体層25と電気的に接続し、絶縁枠体21の上面にF
e−Ni−CoやFe−Ni42アロイ等のFe−Ni合
金・無酸素銅・アルミニウム・ステンレス・Cu−W合
金・Cu−Mo合金などから成る蓋体23を、半田・Au
Snろう等の低融点金属ろう材やAuGeロウ等の高融
点金属ろう材、あるいはシームウェルド(溶接)等によ
り取着することによって、高周波回路部品28がパッケー
ジ内部に気密封止して収容され、製品としての高周波回
路装置となる。
Using such a high-frequency circuit package, a high-frequency circuit component 28 is mounted on the mounting portion 21a, and its electrode 30 is connected to a line conductor located in the housing portion 29 via a bonding wire 31, a bonding ribbon, or the like. 24 and the ground conductor layer 25 on the same plane.
A lid 23 made of an Fe-Ni alloy such as e-Ni-Co or Fe-Ni42 alloy, oxygen-free copper, aluminum, stainless steel, Cu-W alloy, Cu-Mo alloy, etc.
By attaching with a low melting point metal brazing material such as Sn brazing, a high melting point metal brazing material such as AuGe brazing, or seam welding (welding), the high frequency circuit component 28 is hermetically sealed and housed inside the package. It becomes a high-frequency circuit device as a product.

【0032】そして、これを外部電気回路基板に搭載す
るとともに、絶縁枠体22の外側に位置する線路導体24お
よび同一面接地導体層25を外部電気回路の配線導体にボ
ンディングワイヤやリボン・リード端子等を介して接続
して、パッケージ内部の高周波回路部品28と外部電気回
路とを電気的に接続することにより、高周波回路装置と
して使用される。
Then, this is mounted on an external electric circuit board, and the line conductor 24 and the same plane ground conductor layer 25 located outside the insulating frame 22 are bonded to the wiring conductor of the external electric circuit by bonding wires or ribbon lead terminals. By electrically connecting the high-frequency circuit component 28 inside the package and an external electric circuit by using the above-mentioned components, the device is used as a high-frequency circuit device.

【0033】なお、本発明は以上の実施の形態の例に限
定されるものではなく、本発明の要旨を逸脱しない範囲
で種々の変更・改良を施すことは何ら差し支えない。例
えば、高周波信号の入出力部として、線路導体24および
同一面接地導体層25は必要に応じて複数設けてもよい。
また、この入出力部の構造を、例えば収容部を金属壁で
囲んだいわゆるメタルウォールタイプのパッケージの入
出力部の構造として適用してもよい。
It should be noted that the present invention is not limited to the above-described embodiments, and that various changes and improvements can be made without departing from the scope of the present invention. For example, a plurality of line conductors 24 and the same plane ground conductor layer 25 may be provided as necessary as an input / output unit for a high-frequency signal.
Further, the structure of the input / output unit may be applied, for example, as the structure of the input / output unit of a so-called metal wall type package in which the housing is surrounded by a metal wall.

【0034】[0034]

【発明の効果】本発明の高周波回路用パッケージによれ
ば、高周波信号を伝送するための線路導体に対して、絶
縁基板と絶縁枠体とに挟まれた気密封止部において、下
部接地導体層および上部接地導体層を配し、同一面接地
導体層を併設し、さらに、絶縁枠体の内外側面に同一面
接地導体層と上部接地導体層とを接続するキャスタレー
ション導体を形成するとともにその直下の絶縁基板にそ
れぞれ同一面接地導体層と下部接地導体層とを接続する
貫通導体を形成したことから、線路導体が絶縁枠体の内
外側面において気密封止部に出入りする部分の線路構成
が疑似導波管構造となり、その結果、線路導体を取り囲
む接地導体による接地状態を安定させて反射損失を低減
することができるとともに、電磁波シールド効果を高め
て放射損失を抑制することができ、それにより、高周波
信号の入出力部における高周波信号の伝送特性を低損失
で良好なものとすることができる。
According to the high frequency circuit package of the present invention, the lower grounding conductor layer is provided in the hermetically sealed portion between the insulating substrate and the insulating frame with respect to the line conductor for transmitting the high frequency signal. And an upper grounding conductor layer, a grounding conductor layer on the same plane is provided, and a castellation conductor connecting the grounding conductor layer on the same plane and the upper grounding conductor layer is formed on the inner and outer surfaces of the insulating frame. Since the through conductors that connect the same plane ground conductor layer and the lower ground conductor layer are formed on the insulating substrate, the line configuration of the part where the line conductor enters and exits the hermetically sealed portion on the inner and outer surfaces of the insulating frame is simulated. As a result, it has a waveguide structure, and as a result, it is possible to reduce the reflection loss by stabilizing the grounding state of the grounding conductor surrounding the line conductor, and to suppress the radiation loss by enhancing the electromagnetic wave shielding effect. Rukoto can, thereby, can be made excellent in low loss transmission characteristics of the high-frequency signal in the input-output section of the high-frequency signal.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の高周波回路用パッケージの実施の形態
の一例を示す分解斜視図である。
FIG. 1 is an exploded perspective view showing an example of an embodiment of a high-frequency circuit package according to the present invention.

【図2】図1に示す高周波回路用パッケージの要部平面
図である。
FIG. 2 is a plan view of a main part of the high-frequency circuit package shown in FIG. 1;

【図3】図2のC−C’線断面図である。FIG. 3 is a sectional view taken along line C-C ′ of FIG. 2;

【図4】図2のD−D’線断面図である。FIG. 4 is a sectional view taken along line D-D 'of FIG.

【図5】従来の高周波回路用パッケージの例を示す分解
斜視図である。
FIG. 5 is an exploded perspective view showing an example of a conventional high-frequency circuit package.

【図6】図5に示した従来の高周波回路用パッケージの
要部平面図である。
FIG. 6 is a plan view of a main part of the conventional high-frequency circuit package shown in FIG.

【符号の説明】[Explanation of symbols]

21・・・・・絶縁基板 21a・・・・搭載部 22・・・・・絶縁枠体 23・・・・・線路導体 25・・・・・同一面接地導体層 26・・・・・下部接地導体層 27・・・・・上部接地導体層 28・・・・・高周波回路部品 32・・・・・キャスタレーション導体 33・・・・・貫通導体 21 ... Insulating substrate 21a ... Mounting section 22 ... Insulating frame 23 ... Line conductor 25 ... Coaxial ground conductor layer 26 ... Bottom Ground conductor layer 27 Upper ground conductor layer 28 High-frequency circuit components 32 Castellation conductor 33 Through conductor

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 下面に下部接地導体層が形成され、上面
に高周波回路部品が搭載される搭載部を有する絶縁基板
と、 該絶縁基板の前記搭載部近傍から外周近傍にかけて配設
された線路導体および該線路導体の両側に併設された同
一面接地導体層と、 前記絶縁基板上に前記搭載部を囲むとともに前記線路導
体および前記同一面接地導体層の一部を挟んで接合さ
れ、上面に上部接地導体層が形成された絶縁枠体とを具
備し、 前記絶縁枠体の内外側面に前記同一面接地導体層と前記
上部接地導体層とを接続するキャスタレーション導体を
形成するとともに、該キャスタレーション導体直下の前
記絶縁基板にそれぞれ前記同一面接地導体層と前記下部
接地導体層とを接続する貫通導体を形成したことを特徴
とする高周波回路用パッケージ。
An insulating substrate having a lower ground conductor layer formed on a lower surface and a mounting portion on which an RF circuit component is mounted on an upper surface, and a line conductor disposed from the vicinity of the mounting portion to the vicinity of the outer periphery of the insulating substrate. And a ground conductor layer provided on both sides of the line conductor, which surrounds the mounting portion on the insulating substrate, and is joined with a part of the line conductor and the ground conductor layer on the same surface sandwiched therebetween. An insulating frame on which a ground conductor layer is formed, wherein a castellation conductor for connecting the same-plane ground conductor layer and the upper ground conductor layer is formed on the inner and outer surfaces of the insulating frame, and the castellation is formed. A package for a high-frequency circuit, wherein a through conductor for connecting the same-plane ground conductor layer and the lower ground conductor layer is formed on the insulating substrate immediately below the conductor.
JP11758098A 1998-04-27 1998-04-27 High frequency circuit package Expired - Fee Related JP3618046B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11758098A JP3618046B2 (en) 1998-04-27 1998-04-27 High frequency circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11758098A JP3618046B2 (en) 1998-04-27 1998-04-27 High frequency circuit package

Publications (2)

Publication Number Publication Date
JPH11312751A true JPH11312751A (en) 1999-11-09
JP3618046B2 JP3618046B2 (en) 2005-02-09

Family

ID=14715348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11758098A Expired - Fee Related JP3618046B2 (en) 1998-04-27 1998-04-27 High frequency circuit package

Country Status (1)

Country Link
JP (1) JP3618046B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774748B1 (en) 1999-11-15 2004-08-10 Nec Corporation RF package with multi-layer substrate having coplanar feed through and connection interface
JP2005212017A (en) * 2004-01-28 2005-08-11 Kyocera Corp Electronic component sealing substrate, multiple molding electronic component sealing substrate, and electronic device manufacturing method
JP2008159862A (en) * 2006-12-25 2008-07-10 Hitachi Kokusai Electric Inc Package structure of high-frequency electronic component
WO2013094684A1 (en) * 2011-12-20 2013-06-27 京セラ株式会社 Package for housing electronic components, and electronic device
CN103367349A (en) * 2012-03-28 2013-10-23 富士通株式会社 Stacked module

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63107055A (en) * 1986-06-02 1988-05-12 Fujitsu Ltd Package for integrated circuit
JPS63261859A (en) * 1987-04-20 1988-10-28 Shinko Electric Ind Co Ltd Package for high-frequency elements
JPH05226496A (en) * 1992-02-17 1993-09-03 Shinko Electric Ind Co Ltd Electronic component package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63107055A (en) * 1986-06-02 1988-05-12 Fujitsu Ltd Package for integrated circuit
JPS63261859A (en) * 1987-04-20 1988-10-28 Shinko Electric Ind Co Ltd Package for high-frequency elements
JPH05226496A (en) * 1992-02-17 1993-09-03 Shinko Electric Ind Co Ltd Electronic component package

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774748B1 (en) 1999-11-15 2004-08-10 Nec Corporation RF package with multi-layer substrate having coplanar feed through and connection interface
JP2005212017A (en) * 2004-01-28 2005-08-11 Kyocera Corp Electronic component sealing substrate, multiple molding electronic component sealing substrate, and electronic device manufacturing method
JP2008159862A (en) * 2006-12-25 2008-07-10 Hitachi Kokusai Electric Inc Package structure of high-frequency electronic component
WO2013094684A1 (en) * 2011-12-20 2013-06-27 京セラ株式会社 Package for housing electronic components, and electronic device
JPWO2013094684A1 (en) * 2011-12-20 2015-04-27 京セラ株式会社 Electronic component storage package and electronic device
US9386687B2 (en) 2011-12-20 2016-07-05 Kyocera Corporation Electronic component housing package and electronic apparatus
CN103367349A (en) * 2012-03-28 2013-10-23 富士通株式会社 Stacked module
US8981881B2 (en) 2012-03-28 2015-03-17 Fujitsu Limited Stacked module

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