JP2605657B2 - TDMA mobile phone - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a TDMA (Time Divei
In particular, the present invention relates to a mobile telephone of a TDMA system in which a processing time by a delay equalizer is reduced.

[0002]

2. Description of the Related Art Among conventional TDMA type mobile telephones using a delay equalizer, a reception window is provided for receiving received data including a plurality of slots continuously transmitted and including only its own slot. The data is received by performing slot synchronization in order to obtain necessary data. And
The delay equalizer equalizes only necessary data from the data and sends it as a digital value to a control circuit or a voice conversion circuit.

FIG. 6 is a block diagram showing a schematic configuration of a mobile telephone using a delay equalizer. The radio circuit 20
Radio waves are received and transmitted, and the received data is stored by the data capturing circuit 21. When the data capturing by the data capturing circuit 21 is completed, the data is transmitted to the delay equalizer 22, and is equivalent to digital data in the delay equalizer 22, and is transmitted to the control circuit 23 or the voice conversion circuit 24. . The control circuit 23 processes information included in the data,
4 converts the data into voice and outputs it from the speaker unit 26. On the other hand, control data or microphone unit 2
7 is converted by the transmission controller 25 and transmitted to the base station through the radio circuit 20. B
The ER information is information on the bit error rate input to the delay equalizer 22 from a detection circuit (not shown) that detects the bit error rate.

FIG. 7 is a block diagram showing the internal circuit configuration of the data fetch circuit 21. As shown in FIG. The configuration and operation of the data capturing circuit 21 will be described with reference to FIG.

The electric field strength and intermediate frequency of the received data input from the radio circuit 20 to the A / D conversion circuit 211 and the phase detection circuit 212 are converted into digital data d1 and d2 by the conversion clock signal S1 from the counter circuit 213. You. (For example, if d1 is 10 bits and d
2 is 6 bits, for a total of 16 bits. ) These digital data d1 and d2 are stored in the storage circuit 214 by the write signal S from the counter circuit 213, and 38
When 0 words (1 word is 16 bits) are written, the output of the conversion clock signal S1 and the write signal S is stopped. When the write operation to the storage circuit 214 is completed, the delay equalizer 22 reads the reception data D1 output from the storage circuit 214 and performs an equalization process. The delay equalizer 22 determines the deviation from the position of the SYNC word (described below with reference to FIGS. 8A and 8B),
The position information data D2 of the NC word is sent to the start pulse generation circuit 215. Start pulse generation circuit 215
Adjusts the generation timing of the start pulse P by changing the value of the internal counter according to the position information data D2.
When the start pulse P is generated from the start pulse generation circuit 215, the counter circuit 213 generates the converted clock signal S1 and the write signal S, writes the digital data in the storage circuit 214, and again writes them when 380 words have been written. Signal generation stops. Code 21
Reference numeral 6 denotes a clock pulse generation circuit, and a counter circuit 21
3 and the reference clock pulse signals S3 and S4 to the start pulse generation circuit 215, respectively.

FIGS. 8 (a) and 8 (b) show a transmission data format used between a mobile telephone and a base station, which is standardized by the Electronic Industries Association (EIA) of the United States. The transmission data format shown in (a) is from the mobile phone to the base station, and is shown in FIG.
(B) shows the transmission data format used from the opposite base station to the mobile phone, and its width A
Corresponds to the width of one slot taken into the mobile telephone. The number is the number of bits of each signal.

FIG. 9 shows data transmission / reception timings in the mobile telephone, and data transmitted from the base station (refer to the data format shown in FIG. 8 (b)).
Are the reception timing slots 1 depicted at the top of FIG.
It is received by the mobile telephone as slot 2 or slot 3, while transmission from the mobile telephone to the base station is transmitted at the transmission timing depicted at the bottom of FIG. As is clear from FIG. 9, the transmission data (see the data format shown) is transmitted before the reception timing of the slot being received by the mobile telephone.

[0008]

As described above, in the conventional data acquisition using the delay equalizer, even when slot synchronization is performed at the start of reception, a single acquisition width is determined. Since the capture is performed within the width frame, if the capture width is narrow, a case where the synchronization signal is not captured may occur, and the slot synchronization may not be performed. Therefore, as shown in "b" of FIG.
The actual capture width is set wide in advance so that data can be captured several bits to several tens of bits before and after the range "a" to be received, so that the synchronization signal can be reliably captured. That is, the range to be actually taken starts from a part of the immediately preceding data (for example, RSVD part), includes a range to be received, and further extends to a part of the next slot (for example, SYNC part). The slot is determined by the SYNC signal.

However, once the slot synchronization has been achieved, the reception window is set wider than the width of the slot to be received, so that unnecessary data is already taken in, so that the processing in the delay equalizer increases. Will be. In the delay equalizer, in addition to equalizing predetermined data from the wireless data, adjusting the frequency, correcting the reception position, and the like, the processing time becomes longer when the data amount increases, and the processing may not be in time. There is a problem that transmission and reception are not performed smoothly.

Further, there is also a problem that power consumption increases because the delay equalizer operates for a long time.

The present invention has been made in view of the above circumstances in the prior art, and has as its object the following:
An object of the present invention is to provide a mobile telephone of the TDMA system which can reduce the processing amount in the delay equalizer to shorten the processing time and reduce the power consumption.

[0012]

In order to achieve the above object, according to a basic aspect of the present invention, there is provided a delay equalizer for transmitting necessary data in an equivalent manner, wherein a signal including a plurality of slots is provided. In a mobile telephone of the TDMA system in which data in a predetermined slot is taken in, a recording circuit for storing received data and sending the received data to a delay equalizer, and a position of data sent from the delay equalizer are shifted. The slot synchronization is performed by the position correction data from the delay equalizer when the data is received, and the reception position change circuit for correcting the reception data fetch position and the reference clock pulse from the clock pulse generation circuit when the width of the reception window is determined. A counter circuit for outputting a count value; and comparing circuit means for determining the number of storages in the storage circuit and the width of the reception window. Mobile telephone of the TDMA system is provided.

In connection with the above basic aspects, the present invention provides the following embodiments.

According to the first embodiment, the comparison circuit means according to the basic aspect has a plurality of comparison circuits each receiving the count value from the counter circuit, and one of the comparison circuits to be used by the select signal from the delay equalizer. It consists of a select circuit for selecting one of the comparison circuits. According to the second embodiment, the comparison circuit means according to the basic aspect includes a plurality of comparison circuits each receiving a count value from the counter circuit, and a plurality of comparison circuits among the plurality of signals from the data bus line of the delay equalizer. A latch circuit for setting one signal to the “H” state, and a combination of an AND circuit and an OR circuit configured to take out one of the outputs from each of the plurality of comparison circuits as the “H” signal Become.

According to a third embodiment, the comparison circuit means according to the basic aspect has one comparison circuit for inputting a count value from a counter circuit, and a reception window arbitrarily rewritten by a data bus of the delay equalizer. And a latch circuit for inputting a set value relating to the width of.

According to the fourth embodiment, there is further provided an error rate detection circuit for detecting an error rate of a signal, and when the value of the error rate detected by the error rate detection times becomes equal to or less than a predetermined value, a select operation is performed. The circuit is operated to change the selection of the comparison circuit.

According to the fifth embodiment, there is further provided an error rate detection circuit for detecting an error rate of the signal, and when the value of the error rate detected by the error rate detection times falls below a predetermined value, The configuration is such that the set value of the width of the reception window input from the latch circuit to the comparison circuit is changed by operating the delay equalizer.

[0018]

When the delay equalizer is performing slot synchronization, the capture width for capturing the received data is wider than the required width, and even at an arbitrarily open position, one of the synchronization signals is surely within the capture width. Since it is included, the reception window can be reliably set at the position of the reception slot. On the other hand, when the delay equalizer is performing equivalent operation, the width of capture is changed to a sufficiently narrow width required for equivalent operation, and the processing amount is reduced. Can also be reduced.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be explained in more detail below with reference to several preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing the internal circuit configuration of the data fetch circuit 21 of the present invention. The data acquisition circuit 21 receives and stores received data from the wireless circuit, and outputs the received data D1 to the delay equalizer 22, and delays the number of storages and the width of the receiving window of the storage circuit 30 by delay. A comparison circuit device 32 for determining in accordance with a signal from the device 22, a counter circuit 31 for inputting a counter value S2 to the comparison circuit device 32, and a clock pulse generator for outputting a reference clock pulse signal to the counter circuit 31. A circuit 33, a reception position change circuit 35 for performing slot synchronization upon receiving the position correction data D3 from the delay equalizer 22 when the position of the SYNC WORD is shifted, and correcting a position for receiving the reception data; Is output to the delay equalizer 22.

The comparison circuit device 32 is a device that outputs a stop pulse to the storage circuit 30 when the set value S5 (here, the value of the width of the reception window) matches the counter value from the counter circuit 31. Several embodiments are possible. Here, three examples will be described below with reference to FIGS. 2, 4, and 5.

FIG. 2 is a block diagram showing a circuit configuration of the first embodiment. In the first embodiment, the comparison circuit device 3
The first comparison circuits 321 each having a different set value.
And a second comparison circuit 322, and a select circuit 326 for selecting one of the two circuits in accordance with a select signal from the delay equalizer 22, and the delay equalizer 22 receives from the storage circuit 30 380 words, for example,
The position of C WORD is confirmed and equalized. Where S
When the position of the YNC WORD is shifted, the delay equalizer 22 outputs the position correction data D3 and corrects the position where the received data is taken. When the data capturing position is determined and the reception is stabilized, the delay equalizer 22 outputs a select signal to reduce the number of captured data, and reduces the number of captured data from 380 words to, for example, 324 words (minimum value). Can be.

FIG. 4A is a block diagram showing the circuit configuration of a second embodiment of the comparison circuit device. This second
The comparison circuit device according to the embodiment includes, for example, first to fourth four comparison circuits 321, 32 each having a different set value.
2, 323 and 324, and a latch circuit 329 is connected to the data bus line 328 of the delay equalizer 22 as a select circuit.
Is used. In such a circuit configuration, one of the signals output from the delay equalizer 22 via the data bus line 328 is set to “H” by the latch circuit 329. This allows four gates (A
One of the first to fourth comparison circuits 321 to 324 via three gates (OR circuits) 335 to 337.
Stop pulses are output from the two comparison circuits. If the circuit of the comparison circuit device is configured in this way, one circuit can be selected from among a plurality of comparison circuits. Therefore, the width of the reception window can be set to the capture range c to c shown in FIG. It becomes possible to control in multiple stages like f.

FIG. 5 is a block diagram showing a circuit configuration relating to a third embodiment of the comparison circuit device. According to this aspect, the circuit is configured such that the set value output from set value latch circuit 327 becomes the set value of comparison circuit 325, and the set value output from set value latch circuit 327 is a delay equalizer. The data can be arbitrarily rewritten by the 22 data buses. According to such a configuration, the width of the reception window can be appropriately changed, and therefore, the width of the reception window can be sequentially changed while detecting a decrease in the error rate.

Further, although not illustrated in the drawings, instead of directly changing the width of the reception window, the width of the reception window is increased or decreased by changing the timing of starting reception and the timing of ending reception. You may.

Next, the operation of the mobile telephone of the present invention having the comparison circuit device shown in FIG. 2 will be described with reference to the flowchart of FIG. When newly performing reception, values having different reception window widths are set in the first comparison circuit 321 and the second comparison circuit 322 as initial values, respectively, and the selection circuit 326 is set to a wider value. The first
The comparison circuit 321 is selected (F-
1). At the time of reception, a reception window is first opened regardless of the position of data, and data is fetched (F-2). At this time, the select circuit 326 has selected the first comparison circuit 321 and the value of the wide width set in the first comparison circuit 321 is sent out. Therefore, the width of the reception window is wider than the slot width A as shown in FIG. 9B, and any of the synchronization signals is always included in the first fetched data.

The delay equalizer 22 is selected from the received data.
Finds the synchronization signal, checks the position of the opened reception window (F-3), and outputs the position correction data D3 to the reception position change circuit 35 when the received slot is different from its own slot, The position of the reception window is corrected to the position of its own slot (F-4). Even if the slot is its own, if the position is shifted, the position is similarly corrected and slot synchronization is performed.

When the position of the receiving window is determined by the receiving position changing circuit 35, the delay equalizer 22 checks the synchronization signal and equalizes the control (or voice) data. When the slot synchronization is performed, the delay equalizer 22 sets the error rate detection circuit 3
4 from the bit error rate (BER information) (F-
5) It is determined whether or not the bit error rate is below the reference value (F-6). When the bit error rate is below the reference value, the select signal S5a of the comparator is output to the select circuit 326. Upon receiving the signal, the select circuit 326 switches from the first comparison circuit 321 to the second comparison circuit 322, and the storage circuit 3
The number of data to be taken into 0 and the width of the reception window are switched to narrow the width of the reception window as shown in FIG. 9A (F-7).

As described above, after the position of the reception window is determined and reception is continued, it is sufficient to receive only the width of the slot to be received. Is reduced, the amount of data equivalent in the delay equalizer 22 is reduced, the processing time can be shortened, and the power consumption can be reduced. Then, the communication is continued until a signal to end the communication is input, and the communication is ended when the end signal is received (F-8).

[0030]

According to the present invention, the width of the reception window can be changed in the mobile telephone of the TDMA system, so that the delay equalizer is used when slot synchronization is performed and when the slot synchronization is completed and equalization is performed. The width of the required reception data can be changed.When the position of the reception window is changed at the start of reception, etc., the reception window is widened so that the synchronization signal can always be received, and the position of the reception window is determined. After the start of reception, the width of the reception window is reduced, so that the operation time of the delay equalizer can be shortened, the data acquisition time can be shortened, and the like. Therefore, the processing time and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a main part of a mobile phone according to the present invention.

FIG. 2 is a block diagram showing one embodiment of a comparison circuit device used in the mobile telephone of the present invention.

FIG. 3 is a flowchart showing the operation of a mobile telephone provided with the comparison circuit device shown in FIG. 2;

FIG. 4A is a block diagram showing a second embodiment of the comparison circuit device used in the mobile telephone of the present invention, and FIG.
7A is a diagram for explaining an example of data acquisition by the comparison circuit device illustrated in FIG.

FIG. 5 is a block diagram showing a third embodiment of the comparison circuit device used in the mobile phone of the present invention.

FIG. 6 is a schematic block diagram showing the entire configuration of a conventional mobile telephone.

FIG. 7 is a block diagram showing an internal configuration of a conventional data capturing circuit.

FIGS. 8A and 8B are diagrams showing transmission and reception data formats of a conventional mobile telephone, respectively.

FIG. 9 is a timing chart showing data transmission / reception timing in a conventional mobile telephone.

[Explanation of symbols]

 Reference Signs List 20 wireless circuit 21 data acquisition circuit 22 delay equalizer 23 control circuit 24 voice conversion circuit 25 transmission control unit 26 speaker unit 27 microphone unit 30 storage circuit 31 counter circuit 32 comparison circuit device 33 clock pulse generation circuit 34 error rate detection circuit 35 reception Position change circuit 211 A / D conversion circuit 212 Phase detection circuit 213 Counter circuit 214 Storage circuit 215 Start pulse generation circuit 216 Clock pulse generation circuit 321 First comparison circuit 322 Second comparison circuit 323 Third comparison circuit 324 Fourth comparison circuit 325 Comparison circuit 326 Select circuit 327 Set value latch circuit 328 Data bus line 329 Latch circuit D1 Receive data D2 Position information data D3 Position correction data S Write signal S1 Conversion clock signal S2 Counter value S3, S4 Reference clock pulse signal S5 Set value S5a Select signal

Claims (6)

(57) [Claims] 1. A TDMA-type mobile telephone having a delay equalizer for transmitting necessary data in an equivalent manner and taking in data in a predetermined slot from a signal including a plurality of slots. A recording circuit for storing received data and sending the received data to the delay equalizer; and (b) position correction data from the delay equalizer when the position of the data sent from the delay equalizer is shifted. And (c) outputting a count value of a reference clock pulse from a clock pulse generation circuit when determining the width of a reception window. And (d) comparison circuit means for determining the number of storages in the storage circuit and the width of the reception window.
A type mobile phone. 2. A plurality of comparison circuits to which the comparison circuit means inputs count values from the counter circuit, and a selection circuit for selecting one comparison circuit to be used in accordance with a select signal from the delay equalizer. 2. The TDMA mobile phone according to claim 1, comprising: 3. The comparison circuit means, wherein a plurality of comparison circuits each receiving a count value from the counter circuit, and one of a plurality of signals from a data bus line of the delay equalizer, H ”state, and one of the outputs from each of the plurality of comparison circuits.
AND configured to extract one as an "H" signal
2. The TDMA mobile phone according to claim 1, comprising a combination of a circuit and an OR circuit. 4. A comparison circuit in which the comparison circuit inputs a count value from the counter circuit, and a setting value relating to a width of a reception window arbitrarily rewritten by a data bus of the delay equalizer. 2. The TDMA mobile phone according to claim 1, further comprising a latch circuit for inputting the data to the mobile phone. 5. An error rate detection circuit for detecting an error rate of a signal, wherein when the value of the error rate detected by said error rate detection time falls below a predetermined value, said select circuit is activated. 3. The TDMA mobile phone according to claim 2, wherein a selection of said comparison circuit is changed. 6. An error rate detection circuit for detecting an error rate of a signal, wherein when the value of the error rate detected by the error rate detection becomes equal to or less than a predetermined value, the latch circuit detects the error rate. 5. The TDMA mobile phone according to claim 4, wherein the set value of the width of the reception window input to the mobile phone is changed by operating the delay equalizer.