JP3582924B2 - Demodulator - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a demodulation device used in digital mobile communication of a time-division multiple access system and the like, and in particular, restricts the range of data to be decoded to only data in its own slot, thereby suppressing an increase in the amount of computation. .
[0002]
[Prior art]
In a time-division multiple access communication system, information is transmitted in time-divided slots, and a demodulator on the receiving side receives a slot designated for itself and demodulates it. To this end, the demodulation device includes a reception window generation circuit that defines a reception time, and the baseband demodulation unit restores the reception signal captured while the circuit opens the reception window to a baseband signal. .
[0003]
As shown in FIG. 7, a conventional demodulating apparatus performing such an operation includes a receiving window generating circuit 40 for generating a receiving window 41 and a synchronous detecting circuit 42 for converting a received signal into an in-phase component and a quadrature component of a baseband signal. A reception filter 43 for removing unnecessary signal components; a memory 44 for storing the output of the reception filter; and a decoder 45 for reading and decoding data from the memory 44.
[0004]
As shown in FIG. 2, the reception slot has a known symbol for slot synchronization inserted as a slot synchronization symbol 8 at the beginning, followed by an information symbol 9.
[0005]
The reception window generating circuit 40 of this demodulation device has a built-in timer and measures the reception time of its own slot to generate a reception window. At this time, the reception window generating circuit 40 generates a reception window with a sufficient margin so that the slot can be completely received. The received signal is input to the synchronous detection circuit 42 only while the reception window is open, and the synchronous detection circuit 42 synchronously detects the signal and converts the signal into an in-phase component and a quadrature component. The converted signal is stored in the memory 44 via the reception filter 43. The decoder 45 sequentially reads the received signals stored in the memory 44 from the beginning and digitally processes the received signals to decode the data.
[0006]
[Problems to be solved by the invention]
However, such a configuration has a problem that when the time accuracy of the reception window is coarse, data in slots other than the own slot is redundantly decoded, and the amount of calculation increases.
[0007]
An object of the present invention is to solve such a problem, and an object of the present invention is to provide a demodulation device that prevents decoding from reaching an unnecessary range, thereby suppressing an increase in the amount of calculation.
[0008]
[Means for Solving the Problems]
Therefore, the demodulation device of the present invention is provided with a slot head detecting means for detecting the head of the slot with high accuracy.
[0009]
Therefore, data decoding can be limited to only the data of the own slot, and an increase in the amount of calculation in data decoding can be suppressed.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the first aspect of the present invention, there is provided a receiving window generating means for generating a receiving window with a margin so as to be able to receive a signal without leaving its own slot, and synchronously detecting a received signal captured in the receiving window. A demodulator for a time-division multiple access communication system, comprising: a synchronous detection means for performing synchronization, a memory for storing data of the synchronously detected received signal, and a decoding means for reading and decoding data from the memory. A slot head detecting means for detecting a slot synchronization symbol from the detected received signal and identifying a head position of the own slot is provided, and among the received signals captured in the receiving window, the own slot detected by the slot head detecting means. Only the data after the start position of the data is decoded, and the amount of calculation is reduced by suppressing unnecessary decoding. Can Kusuru.
[0011]
According to a second aspect of the present invention, the slot start detecting means detects a slot synchronization symbol by pattern matching to identify the start position of the own slot. When the held slot head detecting means finds a pattern matching the received signal in the received signal, it detects the position of the received signal as the slot head position.
[0012]
According to a third aspect of the present invention, the slot head detecting means obtains a correlation between a known phase in a slot synchronization symbol and a phase of a received signal, and estimates a frequency offset and detects a head position of the own slot based on the result. Are simultaneously performed, the position of the received signal when the correlation value of the phase error is the smallest is identified as the head position of the slot, and the frequency offset is estimated from the position error at that time.
[0013]
According to a fourth aspect of the present invention, the slot start detecting means outputs information indicating the detected start position of the own slot to the synchronous detecting means, and the synchronous detecting means starts the synchronous detecting operation for the next slot according to the information. The synchronous detection processing is performed only from the head of the own slot, and as a result, the data to be decoded is only the data of the own slot.
[0014]
According to a fifth aspect of the present invention, the slot start detecting means outputs information indicating the detected start position of the own slot to the memory, and the decoding means extracts only the data of the own slot from the memory and decodes the data. That is, only the data of the own slot is decoded.
[0015]
According to a sixth aspect of the present invention, there is provided a symbol extracting means for extracting only data near the symbol identification point from the sampling data outputted from the synchronous detecting means and outputting the data to the memory, wherein the slot head detecting means detects the detected own slot. Is output to the symbol extracting means as information indicating the symbol identification point. Since the data stored in the memory is narrowed down, the memory capacity can be reduced. The amount of calculation in decoding can be reduced.
[0016]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
(First Embodiment)
As shown in FIG. 1, a demodulation device according to a first embodiment includes a reception window generating circuit 1 for generating a reception window 2, and a synchronous detection for converting a received signal into an in-phase component signal and a quadrature component signal of a baseband signal. A circuit 3, a reception filter 4 for removing unnecessary signal components, a memory 5 for storing the output of the reception filter, a decoder 6 for reading and decoding data from the memory 5, and a head of the own slot based on the synchronously detected signal. And a slot head detection circuit 7 for detecting the
[0018]
In this demodulation device, a received signal is captured by a reception window 2 having a coarse time accuracy generated from a reception window generation circuit 1 and converted into an in-phase component signal and a quadrature component signal by a synchronous detection circuit 3. The converted signal is stored in the memory 5 via the reception filter 4, and the decoder 6 reads the received signal stored in the memory 5 sequentially from the head and decodes the data.
[0019]
On the other hand, the slot head detection circuit 7 holds the pattern of the slot synchronization symbol 8 (FIG. 2) of its own slot, performs pattern matching between this pattern and the output signal of the synchronization detection circuit 3, and Search and detect the beginning of the own slot. At this time, when the output signal of the synchronous detection circuit 3 is oversampled at a sampling frequency that is an integral multiple of the symbol rate and digitized, the slot head detection unit 7 detects the head of the own slot with the accuracy of the sampling period. can do.
[0020]
The slot head detection circuit 7 transmits slot head position information to the synchronous detection circuit 3 when one TDMA frame period elapses from the start position detection time of the own slot, and the synchronous detection circuit 3 receives the information and receives the next slot. Of the synchronous detection process is started. By repeating this operation, the synchronous detection circuit 3 performs synchronous detection of only its own slot with high accuracy. As a result, the decoder 6 decodes only the data of the own slot.
[0021]
As described above, in this demodulation device, after capturing a reception signal in the conventional reception window, the head of the own slot is detected by the high-precision slot head detection circuit, and only the demodulation processing of data thereafter is performed. Therefore, data can be decoded with a small amount of calculation.
[0022]
(Second embodiment)
In the demodulator of the second embodiment, as shown in FIG. 3, the slot head position information detected by the slot head detection circuit 16 is transmitted to the memory 14, and the range of data read from the memory 14 based on the information is transmitted. Is limited.
[0023]
The slot head detection circuit 16 of this device searches the slot synchronization symbol 8 by pattern matching from the output signal of the synchronization detection circuit 12 and, when detecting the head of its own slot, transmits slot head position information to the memory 14. The decoder 15 sequentially reads the data stored in the memory 14 from the slot head data designated by the slot head position information, and decodes the data.
[0024]
Thus, this demodulation device decodes only the data of the own slot without performing extra decoding. As a result, useless operations during decoding are suppressed.
[0025]
(Third embodiment)
As shown in FIG. 4, the demodulation device according to the third embodiment includes a frequency offset estimation / slot head detection circuit 23 for simultaneously detecting a slot head position and a frequency offset based on a slot synchronization symbol. Other configurations are the same as those of the conventional device (FIG. 7).
[0026]
In this demodulation device, a received signal captured by a reception window 18 having a coarse time accuracy is converted into an in-phase component and a quadrature component by a synchronous detection circuit 19, and stored in a memory 21 via a reception filter 20.
[0027]
The frequency offset estimation / slot top detection circuit 23 holds the phase information of the known slot synchronization symbol (the slope of the straight line composed of the in-phase component and the quadrature component). The correlation with the phase of the read reception signal is obtained. Then, when the correlation value becomes the largest (when the correlation value of the phase error becomes the smallest), the slot head position is identified, and the slot head position information is transmitted to the memory 21. Further, the frequency offset value is determined from the phase error at that time. The decoder 22 decodes the data by sequentially reading the data stored in the memory 21 starting from the slot head data designated by the slot head position information.
[0028]
As described above, the decoding apparatus of this embodiment captures the received signal in the conventional reception window, and then simultaneously detects the frequency offset value and the head position of the own slot by the frequency offset estimating / slot head detection circuit. The decoding of only the data of the own slot is performed by using the head position information of. The frequency offset value is used for correcting a decoding error.
[0029]
(Fourth embodiment)
The demodulation device of the fourth embodiment also uses slot head position information as symbol identification point information for designating a sample used for symbol identification. As shown in FIG. 5, the apparatus includes a symbol extraction circuit 28 for extracting a sample based on the symbol identification point information. The symbol extraction circuit 28 includes a slot head position detected by the slot head detection circuit 31. The information is transmitted as symbol identification point information. Other configurations are the same as those of the first embodiment.
[0030]
In this demodulator, a received signal captured in a reception window 25 with a coarse time accuracy is input to a synchronous detection circuit 26, which converts this signal into an in-phase component and a quadrature component, and then converts the signal to a symbol rate. Oversampling is performed at an integer multiple of sampling frequency, digitized, and output.
[0031]
When the slot head detection circuit 31 detects the head of the own slot with the accuracy of the sampling period by pattern matching of the slot synchronization symbol from the output of the synchronization detection circuit 26, the slot head position information is sent to the synchronization detection circuit 26 and the symbol extraction circuit 28. Tell The synchronous detection circuit 26 which has received the slot head position information starts the synchronous detection processing of the next own slot from the head of the own slot in the same manner as in the first embodiment.
[0032]
The output of the synchronous detection circuit 26 is input to a symbol extraction circuit 28 via a reception filter 27. The symbol extraction circuit 28 thins out the sampling data output from the synchronous detection circuit 26 based on the slot head position information sent from the slot head detection circuit 31, and outputs only the extracted sampling data to the memory 29.
[0033]
The slot start position information indicates a sample position (symbol identification point) at which the slot synchronization symbol is to be identified among a plurality of samples obtained by sampling the slot synchronization symbol. The same applies to samples of information symbols (9 in FIG. 2). The symbol extraction circuit 28 extracts some samples (for example, three samples) centered on the symbol identification point represented by the slot head position information from the samples of each symbol and outputs the samples to the memory 29.
[0034]
Therefore, the data sampled by the synchronous detection circuit 26 is thinned out by the symbol extraction circuit 28 based on the symbol identification point information and stored in the memory 29 at a reduced sampling rate. The decoder 22 performs data decoding using the data stored in the memory 29.
[0035]
As described above, in this demodulation device, after receiving a reception signal in the conventional reception window, the head of the own slot is detected by the high-precision slot head detection circuit, and the subsequent demodulation processing is performed only in the own slot. The detection result is used as symbol identification point information, and unnecessary sampling data is thinned out by a sample extraction circuit. Therefore, the amount of calculation and the memory capacity in data decoding can be extremely reduced.
[0036]
(Fifth embodiment)
The demodulation device according to the fifth embodiment is obtained by applying the configuration using the slot head position information as the symbol identification point information shown in the fourth embodiment to the device according to the second embodiment. As shown, the slot start position information detected by the slot start detection circuit 39 is output to the symbol extraction circuit 36 and the memory 37.
[0037]
In this demodulation device, a reception signal captured in a reception window 33 with coarse time accuracy is converted into in-phase component and quadrature component sampling data by a synchronous detection circuit 34, and a slot head detection circuit 39 The head of the own slot is detected from the output, and slot head position information based on the detection result is output to the symbol extraction circuit 36 and the memory 37.
[0038]
The symbol extraction circuit 36 thins out the sampling data output from the synchronous detection circuit 34 based on the slot head position information, and outputs only the extracted sampling data to the memory 37.
[0039]
The memory 37 stores the data extracted by the symbol extraction circuit 36 and writes the head position of the own slot notified by the slot head position information. The decoder 38 sequentially reads out the data stored in the memory 37 from the slot head data designated by the slot head position information and decodes the data.
[0040]
As described above, in this demodulator, after receiving the received signal in the conventional reception window, the head of the own slot is detected by the high-precision slot head circuit, and the detection result is used as symbol identification point information to perform necessary sampling. Data is extracted, and based on this detection result, only the data of the own slot is designated as a decoding target from the extracted data. Therefore, the amount of calculation and the memory capacity in data decoding can be extremely reduced.
[0041]
【The invention's effect】
As is apparent from the above description, the demodulation device of the present invention is provided with means for detecting the head of the own slot with high accuracy, and decodes only the data after the head of the own slot detected by this means. Therefore, data decoding can be performed with a small amount of calculation.
[0042]
In addition, the frequency offset value can be obtained simultaneously with the detection of the head of the own slot.
[0043]
Also, by using the detection result of the head of the own slot as the symbol identification point information, the amount of calculation in data decoding can be further reduced, and the memory capacity can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a demodulation device according to a first embodiment of the present invention;
FIG. 2 shows a format of a reception slot demodulated by the demodulation device of the present invention;
FIG. 3 is a block diagram illustrating a configuration of a demodulation device according to a second embodiment of the present invention;
FIG. 4 is a block diagram showing a configuration of a demodulation device according to a third embodiment of the present invention;
FIG. 5 is a block diagram showing a configuration of a demodulation device according to a fourth embodiment of the present invention;
FIG. 6 is a block diagram showing a configuration of a demodulation device according to a fifth embodiment of the present invention;
FIG. 7 is a configuration diagram of a conventional demodulation device.
[Explanation of symbols]
1, 10, 17, 24, 32, 40 reception window generation circuits 2, 11, 18, 25, 33, 41 reception windows 3, 12, 19, 26, 34, 42 synchronous detection circuits 4, 13, 20, 27, 35, 43 Reception filters 5, 14, 21, 29, 37, 44 Memory 6, 15, 22, 30, 38, 45 Decoders 7, 16, 31, 39 Slot start detection circuit 23 Frequency offset estimation / slot start detection circuit 28, 36 Symbol extraction circuit 8 Slot synchronization symbol 9 Information symbol

Claims (6)

Reception window generating means for generating a reception window with a margin so that reception can be performed without leaving its own slot, synchronous detection means for synchronously detecting a received signal captured in the reception window, and a synchronously detected reception signal In a demodulation device of a time division multiple access communication system, comprising a memory for storing the data, and decoding means for reading and decoding the data from the memory,
A slot synchronization symbol that is detected from the synchronously detected reception signal of the synchronous detection means, and a slot head detection means for identifying a head position of the own slot is provided. A demodulation device for decoding only data after the head position of the own slot detected by the detection means. 2. The demodulation device according to claim 1, wherein the slot head detecting means detects the slot synchronization symbol by pattern matching and identifies a head position of the own slot. The slot head detecting means obtains a correlation between a known phase in the slot synchronization symbol and the phase of the received signal, and simultaneously performs frequency offset estimation and detection of a head position of the own slot based on the result. The demodulator according to claim 1, wherein Wherein the slot head detecting means outputs information indicating the detected head position of the own slot to the synchronous detecting means, and the synchronous detecting means starts a synchronous detecting operation for the next slot according to the information. The demodulator according to claim 1, wherein: 2. The apparatus according to claim 1, wherein the slot head detecting means outputs information indicating the detected head position of the own slot to the memory, and the decoding means extracts only the data of the own slot from the memory and decodes the data. 4. The demodulation device according to any one of claims 1 to 3. Symbol extraction means for extracting only data near the symbol identification point from the sampling data output from the synchronous detection means and outputting the data to the memory, wherein the slot head detection means detects the head position of the own slot detected The demodulator according to claim 1, wherein the information is output to the symbol extracting unit as information indicating the symbol identification point.

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