JP2591576B2 - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JP2591576B2
JP2591576B2 JP5048748A JP4874893A JP2591576B2 JP 2591576 B2 JP2591576 B2 JP 2591576B2 JP 5048748 A JP5048748 A JP 5048748A JP 4874893 A JP4874893 A JP 4874893A JP 2591576 B2 JP2591576 B2 JP 2591576B2
Authority
JP
Japan
Prior art keywords
lead
integrated circuit
leads
signal
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5048748A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0613421A (ja
Inventor
ジョセフ レイネル アティリオ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
AT&T Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Inc filed Critical AT&T Inc
Publication of JPH0613421A publication Critical patent/JPH0613421A/ja
Application granted granted Critical
Publication of JP2591576B2 publication Critical patent/JP2591576B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/206—Wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Wire Bonding (AREA)
  • Structure Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP5048748A 1992-02-25 1993-02-16 集積回路装置 Expired - Lifetime JP2591576B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US84113992A 1992-02-25 1992-02-25
US841139 1992-02-25

Publications (2)

Publication Number Publication Date
JPH0613421A JPH0613421A (ja) 1994-01-21
JP2591576B2 true JP2591576B2 (ja) 1997-03-19

Family

ID=25284121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5048748A Expired - Lifetime JP2591576B2 (ja) 1992-02-25 1993-02-16 集積回路装置

Country Status (6)

Country Link
US (1) US5329170A (online.php)
EP (1) EP0558226B1 (online.php)
JP (1) JP2591576B2 (online.php)
KR (1) KR100260664B1 (online.php)
DE (1) DE69330411T2 (online.php)
TW (1) TW214631B (online.php)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761049A (en) * 1994-09-19 1998-06-02 Hitachi, Ltd. Inductance cancelled condenser implemented apparatus
US6452442B1 (en) 1995-12-04 2002-09-17 Intel Corporation Apparatus for obtaining noise immunity in electrical circuits
DE19927285C2 (de) 1999-06-15 2003-05-22 Eupec Gmbh & Co Kg Niederinduktives Halbleiterbauelement
TW200501580A (en) * 2003-06-23 2005-01-01 Mitac Technology Corp Offset circuit for constraining electromagnetic interference and operation method thereof
KR101812594B1 (ko) 2013-07-03 2018-01-30 로젠버거 호흐프리쿠벤츠테흐닉 게엠베하 운트 코. 카게 낮은 전자기 간섭을 갖는 다이 패키지

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3383618A (en) * 1966-03-10 1968-05-14 Bell Telephone Labor Inc Suppression of intermodulation distortion
US3584235A (en) * 1968-10-18 1971-06-08 Bell Telephone Labor Inc Video defect eliminator
US4398106A (en) * 1980-12-19 1983-08-09 International Business Machines Corporation On-chip Delta-I noise clamping circuit
WO1987004855A1 (fr) * 1986-02-07 1987-08-13 Fujitsu Limited Dispositif a semiconducteurs
US4816984A (en) * 1987-02-06 1989-03-28 Siemens Aktiengesellschaft Bridge arm with transistors and recovery diodes
US5006820A (en) * 1989-07-03 1991-04-09 Motorola, Inc. Low reflection input configuration for integrated circuit packages

Also Published As

Publication number Publication date
US5329170A (en) 1994-07-12
TW214631B (online.php) 1993-10-11
KR930018710A (ko) 1993-09-22
KR100260664B1 (ko) 2000-07-01
EP0558226A2 (en) 1993-09-01
DE69330411T2 (de) 2002-05-29
EP0558226A3 (online.php) 1994-03-23
JPH0613421A (ja) 1994-01-21
EP0558226B1 (en) 2001-07-11
DE69330411D1 (de) 2001-08-16

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