JP2591152Y2 - Electronic component mounting circuit board - Google Patents

Electronic component mounting circuit board

Info

Publication number
JP2591152Y2
JP2591152Y2 JP1993069215U JP6921593U JP2591152Y2 JP 2591152 Y2 JP2591152 Y2 JP 2591152Y2 JP 1993069215 U JP1993069215 U JP 1993069215U JP 6921593 U JP6921593 U JP 6921593U JP 2591152 Y2 JP2591152 Y2 JP 2591152Y2
Authority
JP
Japan
Prior art keywords
electronic component
substrate
circuit board
resin
component mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1993069215U
Other languages
Japanese (ja)
Other versions
JPH0742164U (en
Inventor
康二 奥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP1993069215U priority Critical patent/JP2591152Y2/en
Publication of JPH0742164U publication Critical patent/JPH0742164U/en
Application granted granted Critical
Publication of JP2591152Y2 publication Critical patent/JP2591152Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

【考案の詳細な説明】[Detailed description of the invention]

【0001】[0001]

【産業上の利用分野】本考案は、電子機器等に使用され
ている電子部品実装回路基板の構造に係り、特に、チッ
プ部品の保護用樹脂のコーティングが容易な基板構造に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an electronic component mounted circuit board used in electronic equipment and the like, and more particularly to a substrate structure in which a resin for protecting chip components can be easily coated.

【0002】[0002]

【従来の技術】従来から、プリント配線基板上に電子部
品の集積度を上げて搭載する方法として、専用の集積回
路や混成集積回路を使用する方法もあるが、集積度が比
較的低く、また、少量生産の場合には、コストアップに
なる。その対応策として、小型のセラミック、または、
ガラスエポキシの基板上に配線パターンを形成して、そ
の上にベアチップ、モールドチップ等の複数の電子回路
部品を搭載してワイヤーボンディング、半田付け後、リ
ード端子の装着された電子部品実装回路基板をプリント
配線基板上に搭載する方法がある。
2. Description of the Related Art Conventionally, as a method of mounting electronic components on a printed wiring board with an increased degree of integration, there is a method of using a dedicated integrated circuit or a hybrid integrated circuit, but the degree of integration is relatively low. In the case of small-volume production, the cost increases. As a countermeasure, a small ceramic or
A wiring pattern is formed on a glass epoxy board, and a plurality of electronic circuit components such as a bare chip and a mold chip are mounted thereon. After wire bonding and soldering, an electronic component mounting circuit board with lead terminals is mounted. There is a method of mounting on a printed wiring board.

【0003】図3は従来の電子部品実装回路基板の構成
図である。以下、図に従って説明する。1は基板で、ガ
ラスエポキシ、セラミック等の板上に配線パターンが形
成されており、周辺部には半田コーティングされた端子
パターン11が設けられている。2はリード端子で、一
端には基板1の周辺部の端子パターン11に挿入される
コの字型の嵌合部21、他端にはプリント基板に半田付
けされる端子部22を有する。3はモールドチップで、
ダイオードやコンデンサー等のチップ状の電子素子が樹
脂成形され、外部に端子が設けられている。4はベアチ
ップで、IC等の裸のチップが基板1上に搭載され、ワ
イヤーボンディングされている。5はコーティング樹脂
層で、エポキシ樹脂等の熱硬化性の樹脂がベアチップ4
及びワイヤーボンディング部41に塗布、硬化されてい
る。
FIG. 3 is a configuration diagram of a conventional electronic component mounting circuit board. Hereinafter, description will be made with reference to the drawings. Reference numeral 1 denotes a substrate on which a wiring pattern is formed on a plate made of glass epoxy, ceramic, or the like, and a terminal pattern 11 coated with solder is provided on a peripheral portion. Reference numeral 2 denotes a lead terminal, which has a U-shaped fitting portion 21 inserted into the terminal pattern 11 at the peripheral portion of the substrate 1 at one end, and a terminal portion 22 soldered to the printed board at the other end. 3 is a mold chip
A chip-shaped electronic element such as a diode or a capacitor is molded with resin, and a terminal is provided outside. A bare chip 4 has a bare chip such as an IC mounted on the substrate 1 and wire-bonded. 5 is a coating resin layer, and a thermosetting resin such as an epoxy resin is a bare chip 4.
And is applied to the wire bonding section 41 and cured.

【0004】図4は従来の電子部品実装回路基板の実装
工程図である。以下、図に従って、部品実装工程を説明
する。 (a)基板1のB面にペースト状の半田が印刷され、そ
の上にモールドチップ3が搭載され、さらに、基板1の
端子部11にリード端子2のコの字型の嵌合部21が挿
入され、赤外線等の加熱手段によりモールドチップ3が
半田付けされるとともに、端子部11と嵌合部21が固
着される。その後、基板1が反転される。この反転され
た状態が図示のものである。
FIG. 4 is a view showing a mounting process of a conventional electronic component mounting circuit board. Hereinafter, the component mounting process will be described with reference to the drawings. (A) Paste solder is printed on the B side of the substrate 1, the mold chip 3 is mounted thereon, and a U-shaped fitting portion 21 of the lead terminal 2 is provided on the terminal portion 11 of the substrate 1. The molded chip 3 is soldered by a heating means such as infrared rays, and the terminal portion 11 and the fitting portion 21 are fixed. After that, the substrate 1 is inverted. This inverted state is shown in the figure.

【0005】(b)反転された基板1のA面にも同様の
方法により、モールドチップ3が搭載されてリフロー及
び洗浄される。 (c)基板1のA面の所定の位置に接着剤等によりベア
チップ4がダイボンディングされ、続いて、ベアチップ
4の端子部(図示せず)と基板1の端子部(図示せず)
が金線等でワイヤーボンディングされる。
(B) The mold chip 3 is mounted on the inverted surface A of the substrate 1 by the same method, and reflowed and cleaned. (C) The bare chip 4 is die-bonded to a predetermined position on the surface A of the substrate 1 with an adhesive or the like, and subsequently, the terminal portion (not shown) of the bare chip 4 and the terminal portion (not shown) of the substrate 1
Is wire-bonded with a gold wire or the like.

【0006】(d)ワイヤーボンディングされたベアチ
ップ4は汚染防止及びワイヤーボンディング部41の強
度確保のために、エポキシ等のコーティング樹脂層5が
塗布され、紫外線または加熱により硬化されて電子部品
実装回路基板は完成する。
(D) A coating resin layer 5 such as epoxy is applied to the wire-bonded bare chip 4 in order to prevent contamination and secure the strength of the wire bonding portion 41, and is cured by ultraviolet light or heating to form an electronic component mounted circuit board. Is completed.

【0007】[0007]

【考案が解決しようとする課題】上述の図4の電子部品
実装回路基板の実装工程では、コーティング液の粘度が
低い場合、ベアチップ4及びワイヤーボンディング部4
1を保護するコーティング樹脂5が不必要な箇所にまで
流れるため、形状的に見栄えが悪いばかりか、ワイヤー
の上部が露出する可能性がある。また、ベアチップ4自
体が露出し易くIC部が劣化したり、ワイヤーボンディ
ング部41の信頼性品質が損なわれる。逆に粘度が高い
場合には、チップ4の周辺に空気溜まりが発生し易くな
り、これが発生すると膨張等によりコーティング樹脂層
5のクラックやワイヤー断線を生じる恐れがある。従っ
て、特に、樹脂の場合は塗布する量のコントロールだけ
でなく、樹脂の流動性にも関係し粘度のコントロールも
必要なため、その樹脂形成作業が非常に困難となる。こ
の対策として、ワイヤーボンディングされたベアチップ
4の周辺に隔壁を設けて、塗布された粘度の低いコーテ
ィング樹脂層5が流動しないようにする方法も提案され
ている。しかし、この方法では工数が嵩むと言う問題が
ある。また、通常の集積回路のように専用の型(リード
フレーム、樹脂成形型)を使用してベアチップ実装、樹
脂モールドする方法もある。この方法は多品種少量生産
には不向きで価格が高くなると言う問題がある。従って
本考案は、樹脂形成作業を容易にする。実装工数を
少なくする。コストを低くする。これらを同時に解決
した電子部品実装回路基板の構造を提供することを目的
とする。
In the mounting process of the electronic component mounting circuit board shown in FIG. 4, when the viscosity of the coating liquid is low, the bare chip 4 and the wire bonding portion 4
Since the coating resin 5 that protects 1 flows to an unnecessary part, not only the appearance is poor in shape but also the upper part of the wire may be exposed. Further, the bare chip 4 itself is easily exposed, so that the IC part is deteriorated and the reliability quality of the wire bonding part 41 is impaired. Conversely, if the viscosity is high, air pockets are likely to be generated around the chip 4, and when this occurs, there is a possibility that cracks or wire breaks in the coating resin layer 5 may occur due to expansion or the like. Accordingly, in the case of a resin, in particular, not only the control of the amount to be applied but also the control of the viscosity related to the fluidity of the resin are required. As a countermeasure, a method has been proposed in which a partition is provided around the bare chip 4 to which the wire bonding is performed so that the applied coating resin layer 5 having a low viscosity does not flow. However, this method has a problem that the number of steps is increased. There is also a method of mounting a bare chip and resin molding using a dedicated mold (lead frame, resin molding mold) as in a normal integrated circuit. This method has a problem that it is not suitable for high-mix low-volume production and the price is high. Therefore, the present invention facilitates the resin forming operation. Reduce the number of mounting steps. Lower costs. It is an object of the present invention to provide a structure of an electronic component mounted circuit board that solves these problems at the same time.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に本考案は、基板上に電子部品が搭載され、前記電子部
品に樹脂が塗布されてなる電子部品実装回路基板におい
て、前記基板の周縁に導電部が設けられ、前記導電部に
前記樹脂の流出防止用隔壁と一体形成された端子が装着
されてなることを特徴とするものである。
According to the present invention, there is provided an electronic component mounting circuit board comprising an electronic component mounted on a substrate and a resin applied to the electronic component. A conductive part, and a terminal integrally formed with the partition wall for preventing the resin from flowing out is attached to the conductive part.

【0009】[0009]

【作用】本考案によれば、端子は樹脂流出防止用隔壁と
一体化されているため、端子装着工程と流出防止工程と
が同時になされる。そして、装着状態において、樹脂を
塗布したとき、壁により樹脂の流出が防止されるので、
樹脂を高くすることができ、電子部品を充分に覆える。
According to the present invention, since the terminal is integrated with the resin outflow preventing partition, the terminal mounting step and the outflow preventing step are performed simultaneously. And when the resin is applied in the mounted state, the resin is prevented from flowing out by the wall,
The height of the resin can be increased, and the electronic components can be covered sufficiently.

【0010】[0010]

【実施例】図1は本考案の一実施例の電子部品実装回路
基板の構成図である。以下、図に従って説明する。1は
基板で、ガラスエポキシ、セラミック等の板上に配線パ
ターンが形成されており、周辺部には予め、工程前に半
田処理(半田が塗布されている)された端子パターン1
1(導電部)が設けられている。3はモールドチップ
で、ダイオードやコンデンサー等のチップ状の電子素子
が樹脂成形され、外部に端子が設けられている。4はベ
アチップで、IC等の裸のチップが基板1上に搭載さ
れ、ワイヤーボンディングされている。6はコネクタ
で、ポリカーボネート等の耐熱性の樹脂により構成され
るモールド部64とリード端子61が一体成形されてお
り、リード端子61の一端には基板1の周辺部の端子パ
ターン11に挿入されるコの字型の嵌合部62、他端に
はプリント基板に半田付けされる端子部63を有する。
FIG. 1 is a block diagram of an electronic component mounting circuit board according to an embodiment of the present invention. Hereinafter, description will be made with reference to the drawings. Reference numeral 1 denotes a substrate on which a wiring pattern is formed on a plate made of glass epoxy, ceramic, or the like, and a terminal pattern 1 on which a soldering process (solder is applied) before the process is performed in a peripheral portion.
1 (conductive portion) is provided. Reference numeral 3 denotes a molded chip, in which a chip-shaped electronic element such as a diode or a capacitor is molded with a resin, and external terminals are provided. A bare chip 4 has a bare chip such as an IC mounted on the substrate 1 and wire-bonded. Reference numeral 6 denotes a connector, in which a molded portion 64 made of a heat-resistant resin such as polycarbonate and a lead terminal 61 are integrally formed. One end of the lead terminal 61 is inserted into the terminal pattern 11 in the peripheral portion of the substrate 1. It has a U-shaped fitting part 62 and a terminal part 63 at the other end which is soldered to a printed circuit board.

【0011】尚、ここでコネクタ6について若干補足説
明をする。図1では、コネクタ6の両端部は45°の楔
型になっているが、これは基板1に対して額縁のごとく
突き合わせて挟み込むためである。更に、図1におい
て、正方形の基板の場合には、基板1の一辺の長さx
と、この辺に対応して嵌合するコネクタ6の凹部の長さ
yが等しいため、基板1に4つのコネクタ6が隙間なく
嵌合される。尚、この場合、基板の各辺に対するコネク
タ(4個)の形状はいずれも同一である。また、基板が
長方形のものでも長さyが長さxに等しくなるようコネ
クタを作成すればよい。
Here, the connector 6 will be supplementarily described. In FIG. 1, both ends of the connector 6 are wedge-shaped at 45 °, but this is for abutting the substrate 1 like a frame. Further, in FIG. 1, in the case of a square substrate, the length x of one side of the substrate 1
And the length y of the concave portion of the connector 6 fitted corresponding to this side is equal, so that the four connectors 6 are fitted to the board 1 without any gap. In this case, the connectors (four) for each side of the board have the same shape. Further, the connector may be formed so that the length y is equal to the length x even if the substrate is rectangular.

【0012】この端部の形状は隣接するコネクタ6の接
触部に隙間ができないように基板1を挟むのが目的であ
り直角でもかまわない。また、専用の端子数のコネクタ
6を作ってもよいし、汎用性のある長いコネクタを作
り、基板1の寸法に合わせて切断してもよい。端子パタ
ーン11と嵌合部62の位置を対応させて装着すると、
(b)に示すように、コネクタ端部が突き合う形で密着
される。また、パターン11に嵌合部62が圧着した状
態になっており、パターン11及び嵌合部62の厚さも
薄く、基板1とコネクタ6の隙間も僅かである。以上に
より樹脂が基板外部へ流れないようにできる。
The shape of this end is intended to sandwich the board 1 so that there is no gap between the contact portions of the adjacent connectors 6, and may be a right angle. Alternatively, a connector 6 having a dedicated number of terminals may be formed, or a versatile long connector may be formed and cut according to the dimensions of the substrate 1. When the terminal pattern 11 and the fitting portion 62 are attached in a corresponding position,
As shown in (b), the connector ends are brought into close contact with each other. Further, the fitting portion 62 is in a state of being crimped to the pattern 11, the thickness of the pattern 11 and the fitting portion 62 is small, and the gap between the board 1 and the connector 6 is small. Thus, the resin can be prevented from flowing outside the substrate.

【0013】図2は本考案の一実施例の電子部品実装回
路基板の実装工程図である。以下、図に従って、部品実
装工程を説明する。 (a)基板1のB面にペースト状の半田が印刷され、そ
の上にモールドチップ3が搭載され、さらに、コネクタ
端子64を装着し、基板1の四辺の端子部11に隣接す
るコネクタ6相互間が密着されるように、コネクタ6の
コの字型の嵌合部62を挿入し、図1の(a)で示すa
とbの位置を合わせるように嵌め込む。赤外線の加熱手
段(一定範囲の集中的な加熱)によりB面側のみにおい
てモールドチップ3が半田付けされるとともに、端子部
11の予め半田処理された半田が溶融、嵌合部62と固
着される。これにより端子付け工程と壁付け工程が同時
になされる。その後、基板1が反転される。この反転さ
れた状態が図示のものである。
FIG. 2 is a mounting process diagram of an electronic component mounting circuit board according to an embodiment of the present invention. Hereinafter, the component mounting process will be described with reference to the drawings. (A) Paste solder is printed on the B side of the substrate 1, the mold chip 3 is mounted thereon, the connector terminals 64 are further mounted, and the connectors 6 adjacent to the terminal portions 11 on the four sides of the substrate 1 are connected. The U-shaped fitting portion 62 of the connector 6 is inserted so that the gaps are brought into close contact with each other, and a is shown in FIG.
And b are aligned. The mold chip 3 is soldered only on the B side by infrared heating means (intensive heating within a certain range), and the solder of the terminal portion 11 that has been pre-soldered is melted and fixed to the fitting portion 62. . Thereby, the terminal attaching step and the wall attaching step are performed simultaneously. After that, the substrate 1 is inverted. This inverted state is shown in the figure.

【0014】(b)反転された基板1のA面にも同様の
方法により、モールドチップ3が搭載されて赤外線の加
熱手段(一定範囲の集中的な加熱)によりA面側のみに
おいてモールドチップ3が半田付けされるとともに、端
子部11の予め半田処理された半田が溶融、嵌合部62
と固着される。その後洗浄される。 (c)基板1のA面の所定の位置に銀エポキシ接着剤等
によりベアチップ4がダイボンディングされ、続いて、
ベアチップ4の端子部(図示せず)と基板1の端子部
(図示せず)が金線等でワイヤーボンディングされる。
(B) The mold chip 3 is mounted on the inverted surface A of the substrate 1 in the same manner, and the mold chip 3 is mounted only on the surface A by infrared heating means (intensive heating within a certain range). Are soldered and the solder of the terminal portion 11 which has been pre-soldered is melted, and the fitting portion 62 is melted.
Is fixed. After that, it is washed. (C) The bare chip 4 is die-bonded to a predetermined position on the surface A of the substrate 1 with a silver epoxy adhesive or the like, and subsequently,
A terminal portion (not shown) of the bare chip 4 and a terminal portion (not shown) of the substrate 1 are wire-bonded with a gold wire or the like.

【0015】(d)ワイヤーボンディングされたベアチ
ップ4は汚染防止及びワイヤーボンディング部41の強
度確保のために、エポキシ等の粘度の低い樹脂がコネク
タ6のモールド部64で構成された隔壁内に充填され
(樹脂は外に流れないので樹脂を一方的に厚くすること
ができる)、紫外線または加熱によりコーティング樹脂
層7が硬化され、電子部品実装回路基板は完成する。樹
脂の厚さはチップよりも充分高く、完全にチップが保護
できる。尚、裏面(B面)は耐湿性のコーティング樹脂
膜8が薄く塗布されたり、スプレーされることにより信
頼性の向上が図られている。A面にある樹脂は四角形に
成形された状態となっており、樹脂の形の見栄えが良
い。
(D) In order to prevent contamination and ensure the strength of the wire bonding portion 41, the bare chip 4 wire-bonded is filled with a low-viscosity resin, such as epoxy, in a partition formed by the mold portion 64 of the connector 6. (Because the resin does not flow out, the resin can be thickened unilaterally), the coating resin layer 7 is cured by ultraviolet light or heating, and the electronic component mounted circuit board is completed. The thickness of the resin is sufficiently higher than the chip, and the chip can be completely protected. The reliability is improved on the back surface (surface B) by applying or spraying the moisture-resistant coating resin film 8 thinly. The resin on the A side is in a state of being formed into a square shape, and the shape of the resin has a good appearance.

【0016】尚、上記実施例では、両面実装基板につい
て記載したが、片面実装基板についても適用できる。以
上のように本実施例では、コネクタ6のモールド部64
がコーティング樹脂層7の流出防止用の隔壁の役目を果
たすので、コーティング樹脂層7の塗布量や粘度のコン
トロールを必要としない。
In the above embodiment, the double-sided mounting board is described. However, the present invention can be applied to a single-sided mounting board. As described above, in the present embodiment, the mold portion 64 of the connector 6 is used.
Plays a role of a partition for preventing the coating resin layer 7 from flowing out, so that it is not necessary to control the application amount and the viscosity of the coating resin layer 7.

【0017】[0017]

【考案の効果】以上説明したように、本考案ではリード
端子と一体成形されたコネクタを使用することにより、
電子部品を覆う樹脂形成作業が容易になり、実装工数の
削減、コストダウンが図れる。
[Effect of the Invention] As described above, in the present invention, by using a connector integrally formed with a lead terminal,
The resin forming work for covering the electronic component is facilitated, so that the number of mounting steps and the cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本考案の一実施例の電子部品実装回路基板の構
成図である。
FIG. 1 is a configuration diagram of an electronic component mounting circuit board according to an embodiment of the present invention.

【図2】本考案の一実施例の電子部品実装回路基板の実
装工程図である。
FIG. 2 is a mounting process diagram of an electronic component mounting circuit board according to an embodiment of the present invention;

【図3】従来の電子部品実装回路基板の構成図である。FIG. 3 is a configuration diagram of a conventional electronic component mounting circuit board.

【図4】従来の電子部品実装回路基板の実装工程図であ
る。
FIG. 4 is a mounting process diagram of a conventional electronic component mounting circuit board.

【符号の説明】[Explanation of symbols]

1・・・基板 2・・・リード端子 3・・・モールドチップ 4・・・ベアチップ 5、7・・・コーティング樹脂層 8・・・コーティング樹脂膜 6・・・コネクタ DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Lead terminal 3 ... Mold chip 4 ... Bare chip 5, 7 ... Coating resin layer 8 ... Coating resin film 6 ... Connector

Claims (1)

(57)【実用新案登録請求の範囲】(57) [Scope of request for utility model registration] 【請求項1】 基板上に電子部品が搭載され、前記電子
部品に樹脂が塗布されてなる電子部品実装回路基板にお
いて、 前記基板の周縁に導電部が設けられ、前記導電部に前記
樹脂の流出防止用隔壁と一体形成された端子が装着され
てなることを特徴とする電子部品実装回路基板。
1. An electronic component mounted circuit board having an electronic component mounted on a substrate and a resin applied to the electronic component, wherein a conductive portion is provided on a periphery of the substrate, and the resin flows into the conductive portion. An electronic component mounting circuit board, comprising a terminal integrally formed with a prevention partition.
JP1993069215U 1993-12-24 1993-12-24 Electronic component mounting circuit board Expired - Fee Related JP2591152Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1993069215U JP2591152Y2 (en) 1993-12-24 1993-12-24 Electronic component mounting circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1993069215U JP2591152Y2 (en) 1993-12-24 1993-12-24 Electronic component mounting circuit board

Publications (2)

Publication Number Publication Date
JPH0742164U JPH0742164U (en) 1995-07-21
JP2591152Y2 true JP2591152Y2 (en) 1999-02-24

Family

ID=13396281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1993069215U Expired - Fee Related JP2591152Y2 (en) 1993-12-24 1993-12-24 Electronic component mounting circuit board

Country Status (1)

Country Link
JP (1) JP2591152Y2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4693295B2 (en) * 2001-07-24 2011-06-01 大日本印刷株式会社 Circuit formation method
JP2004265958A (en) * 2003-02-27 2004-09-24 Tdk Corp Method for manufacturing electronic component and substrate sheet
JP4725817B2 (en) * 2006-05-17 2011-07-13 株式会社村田製作所 Manufacturing method of composite substrate
KR102290199B1 (en) * 2018-11-13 2021-08-20 (주)다이나테크 Method for Forming Thin Film Replacing Tape

Also Published As

Publication number Publication date
JPH0742164U (en) 1995-07-21

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