JP2588464B2 - Photoelectric conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a photoelectric conversion device.

The present invention relates to a structure on a light irradiation surface side of a photoelectric conversion device, in which an electrode portion region on a semiconductor upper surface has a flat surface, and a region other than the electrode portion, that is, a V-shaped or It has a trapezoidal groove. Further, N ⁺ or P ^{+ of a} conductivity type different from that of the semiconductor substrate is provided above the trench.
A layer is provided, and the inside of the groove exposes the semiconductor substrate itself, and the irradiation light efficiently reaches the inside of the semiconductor.

When an insulating or semi-insulating film of 5 to 100 mm thick made of silicon nitride or silicon carbide having a thickness capable of passing a current is provided, a semiconductor layer of a conductivity type opposite to that of a substrate semiconductor is electrically apparent. The semiconductor device is characterized in that the electrodes are provided so as to float from the upper counter electrode and constitute a floating channel, and the electrodes on the film are provided with electrodes having polarities for generating a depletion layer in the semiconductor layer.

Further, according to the present invention, the semiconductor surface in the counter electrode portion has a flat surface, and the light-irradiated surface other than this electrode portion has a V-shaped cross section in order to reduce the reflection efficiency of the irradiated light.
It is characterized in that a groove of a mold (including a reverse V-shaped groove and referred to as a V-shaped groove in the present invention) or a trapezoid (an inverted trapezoid or a mixed groove of a V-shaped and a trapezoid is generally referred to as a trapezoid in the present invention) is provided. And

According to the present invention, such a V-shaped or trapezoidal groove is selectively formed on the surface of a semiconductor, and when the electrode is formed on the back surface, the groove or the extremely thin insulating or semi-insulating film on the groove is damaged so that a pinhole layer is formed. To prevent the counter electrode from being electrically short-circuited with the opposite conductivity type or the like immediately below the counter electrode, and to allow the opposite conductivity type layer having a thickness of 5000 mm or less, preferably 20 to 200 mm, and the substrate semiconductor to be electrically connected to each other. Ensure that the metal of the counter electrode does not diffuse to the junction and deteriorate the junction, and the counter electrode creates a depletion layer in the semiconductor below this reverse conductivity type layer, improving the open-circuit voltage It is characterized by.

[0006]

2. Description of the Related Art Conventionally, a CNR (COMSAT NON-REFRE) has been used as a photoelectric conversion element in which a V-shaped groove exists infinitely and homogeneously on a light irradiation surface.
CTIDE SOLAR CELL) is known. In this method, a V-shaped groove is anisotropically etched on the surface of a silicon semiconductor, and a very shallow PN junction of 0.2 to 0.3 μm is provided on the entire surface of the groove where a large number of these grooves are present infinitely to oppose this bonding layer. The electrodes were brought into ohmic contact, and the photovoltaic power generated at this joint surface was extracted. This CNR has experimentally obtained a high conversion efficiency of 15% or more at AM0 and 18% at AM1. But because of this very shallow junction,
The junction is easily broken, causing an electrical short or leak at the PN junction, and no practical reliability has been obtained.

Further, conventionally, a PN junction type device is manufactured by diffusing a P or N layer at a high temperature and a high concentration in order to obtain a finely controlled high open-circuit voltage on a semiconductor substrate.

[0008]

In such an apparatus, there are many cost factors due to the diffusion step, subtle electrode contact with electrodes, and the like, and the production yield is not high.

In the MIS type device, an extremely thin silicon oxide film is formed on the light irradiation surface, and a high open-circuit voltage can be obtained by the counter electrode on the upper surface. However, in a light irradiation part other than the electrode part, when this insulating film is formed into a chip for forming the electrode on the back surface or taking out the conversion element from the substrate, it is deteriorated due to mechanical damage and defects due to pinholes or scratches are induced. This causes a decrease in current, and in particular, it has been impossible to stably form an inversion layer (inversion layer) at the light irradiation portion.

The present invention has a feature that an insulating layer as an MIS type device operates as a barrier for preventing deterioration of a junction, and a feature of a PN junction type device by a shallow diffusion (shallow diffusion) method. Another object of the present invention is to provide a method for manufacturing a photoelectric conversion device having a very ideal structure, in which the respective disadvantages are offset.

[0011]

In other words, a semiconductor layer of the opposite conductivity type is formed on the upper surface of a semiconductor of the conductivity type for light irradiation by 0.5 mm.
With a thickness of μm or less, especially 20 to 2000 mm,
It is provided to invert the semiconductor surface to the conductivity type.

Further, an insulating or semi-insulating film having a thickness allowing current to flow is provided on the upper surface thereof, and a counter electrode for determining an open-circuit voltage is provided on the upper surface thereof. For this reason, the open circuit voltage is determined by the work function difference between the semiconductor and the electrode, and the opposite conductive type semiconductor layer is not in contact with the external electrode with respect to the underlying substrate semiconductor. It has a structure. In addition, in the light irradiating portion between the electrode portions, the semiconductor layer of the opposite conductivity type is made thin to prevent a reduction in conversion efficiency due to absorption of light. Also, since this semiconductor layer is floating, a horizontal electric field is generated in the direction of the counter electrode, and one of the charges generated by light irradiation has a so-called channel structure that promotes a drift in the horizontal direction through this semiconductor layer. Have.

In this sense, the structure of the present invention may be called a photoelectric conversion device having a floating channel structure. In the case of a so-called conventional PN junction type, an alloy (alloy) is formed between the electrode and the semiconductor for ohmic contact between the electrodes with respect to the junction between the semiconductor layer and the semiconductor surface which is also formed under the electrode.
Requires a junction depth of 0.5 to 1 .mu.m.
For this reason, as in the present invention, the depth is set to 0.5 μm or less, especially 20 μm.
It was not possible to form a reverse conductivity type semiconductor layer having a thickness of up to 500 mm. However, the present invention does not provide such an ohmic contact electrode, but provides a counter electrode on an insulating or semi-insulating film, and a material having a polarity to expand the depletion layer at the junction of the PN junction below the film. Are used to form a counter electrode.

According to the present invention, in addition to the above, a V-shaped groove is provided on the light irradiation surface to prevent reflection of irradiation light at the portion, and the V-shaped groove is conventionally known. Instead of a PN junction type, it is applied to an MIS type photoelectric conversion device. In addition, the production yield of the MIS type element is improved by having irregularities on the surface other than the counter electrode portion, and an embodiment of the present invention will be described below with reference to the drawings.

[0015]

[Embodiment 1] FIG. 1 is a longitudinal sectional view for manufacturing a photoelectric conversion device for carrying out the present invention.

In FIG. 1A, a semiconductor substrate (10
0) plane or its crystal orientation (± 15 with respect to (100) plane)
°). The P-type specific resistance was 2 to 50 Ωcm. Silicon oxide is formed on the front surface (upper side of the drawing) of the semiconductor (1) by dipping, and boron glass is formed on the entire back side (lower side of the drawing) by dipping. And a P ⁺ layer (11) was formed on the entire back surface to a depth of 2 to 5 μm. Further, silicon oxide on the surface of the semiconductor (1) was chemically removed.

Thereafter, phosphor glass or arsenic glass (23) is formed on the surface of the semiconductor (1) by the same dipping method,
Oxidized and diffused at a temperature of about 1000 ° C. to form a semiconductor layer (7) having a conductivity type opposite to that of the substrate to a thickness of 0.5 μm or less, for example, 20 to 2000 mm, particularly 200 mm.

The P ⁺ layer (11) on the back surface does not need to be formed particularly when the substrate makes sufficient ohmic contact. Further, the phosphorus glass or arsenic glass coating was selectively removed on at least the upper surface thereof, and the remaining regions were defined as (21), (22) and (23). Fig. 1 (A)
In FIG. 7, the coating (21) is a region for forming a counter electrode, and the coating (22) is a region corresponding to a V-shaped groove or a projection for forming a trapezoid. This coating (22) is continuous with the coating (21),
After the formation of the V-shaped groove, the N ⁺ region of the projection was continued to the N ⁺ region under the electrode. The width of the coating (21) is 10-20
It is connected to the external lead terminal coating (23) at μm.

The area (17) is 2 to 10 μm square, typically 5 to 10 μm.
It is a hole of μm square. Around this area (17), a coating (22) is formed in a mesh shape with a width of 2 to 10 μm, typically 5 μm. This mesh-like direction was parallel to the (110) plane of the crystal orientation, and was adjusted so that a rectangular V-shaped or trapezoidal groove was formed by anisotropic etching.

Thereafter, the substrate having the structure shown in FIG.
(Water 8cc-Ethylenediamine 17cc-Pyrocaccol-3g
(Mixture of the above) was heated and etched at a temperature of 70 to 85 ° C. The air was kept away from the WAP solution by bubbling with nitrogen. As a result, the (100) plane is 3300Å /
Min, and the (111) plane obtained 200 l / min.
The silicon oxides (21), (22), and (23) were etched for 30 hours or less at 20 ° or less, and had a sufficient masking action.

When the above-mentioned etching by WAP is performed for 5 minutes to 1 hour, typically for 10 to 30 minutes, the mesh-like pattern in FIG. 1A is patterned in parallel to the (110) plane. As a result, the region (17) was etched into a pyramid-shaped square in the opposite direction to form a V-shaped groove. When the etching time is 5 to 10 minutes, an inverted trapezoidal groove is formed in the portion (7), and by adjusting the width of the regions (17) and (22), an upward trapezoidal or upward V-shaped convex portion is formed. It was formed corresponding to the region (12).

That is, since the region (17) has a square of 2 to 10 μm, typically 5 μm, the depth of the V-shaped groove is 3 μm. Since the semiconductor layer of ^{N +} are to limited 0.5μm or less typically have a 20 to 2000 Å, the upper portion of the V-shaped groove has remained the conductivity type of the ^{N +,} also largely P It turns out that it is a type semiconductor. The N ⁺ semiconductor layers (7), (24) and (24 ′) are made of a silicon oxide mask (21).
(22) Since they are held by (23), they can be connected to each other to form a passage for flowing the carrier to the electrode portion (24).

Further, the upper regions (24) and (24 ') of the electrode portion formed after the comb-shaped electrode have a plane as originally formed because it is masked by the silicon oxide mask.

Thereafter, these semiconductor substrates were immersed in hydrofluoric acid to remove silicon oxide on the substrates, and then sufficiently cleaned to obtain FIG. 1 (B). That is, the N ⁺ region easily absorbs light, and the P-type semiconductor produces electrons and holes rather than light.
Of these electrons, the electrons reach the N ⁺ regions (7) and (24 '), and since the resistance of the N ⁺ region is small, the electrons can be efficiently guided to the electrode portion (24). That is, instead of forming an N ⁺ layer on the entire light irradiation surface, N
⁺ Layer is created and the depletion layer is enlarged. And the light is N
^The V-groove effectively avoids absorption in the ⁺ layer, effectively reaches the inside of the semiconductor, and effectively generates electrons and holes.

In the present invention, thereafter, a silicon nitride film is formed in close contact with the substrate surface to a thickness of 5 to 100 ( particularly, 10 to 30) by a plasma nitriding method. That is, 0.5 to 50 MH
A mixture of ammonia or a mixture of nitrogen and hydrogen is diluted to 1-20% helium with an induction energy of
Nitriding was performed at a pressure of 10 torr. Nitriding temperature is 15
The silicon nitride film (3) was formed by nitriding at 0 to 700 ° C, particularly 400 to 680 ° C. Instead of using plasma, the substrate may be inserted into an ammonia atmosphere, and only heat may be applied to form the silicon nitride film. Thus, the silicon nitride film (3) was formed to a thickness of 5 to 100 °, particularly 10 to 30 °.

Aluminum is formed as a back electrode (2) by vacuum evaporation after removing this nitride film, and a sinter for ohmic contact with the semiconductor substrate is not formed at a temperature range of 300 to 600 ° C. Performed in active gas.

In the step shown in FIG. 1, after that, a magnesium (M) is formed on the surface as a counter electrode (21) and an auxiliary electrode (5).
g) was vacuum deposited. This is not Mg, Al, Be, etc.4.0e
It was preferred that the metal have a small work function below V. Mg and Be are easily oxidized and produce at 150 ° C and 10 ° C.
Since it is left in the air for 00 hours and the reliability is lowered, Mg, Be or a mixture of them and a semiconductor or other metal is coated with aluminum over 0.5 to 5000 mm, especially 500 to 2000 mm. The counter electrodes (21) and (5) were formed to a thickness of about 3 μm and formed into a multilayer film of Ni, Cr and Cu for semiconductors in a thickness of 100 to 1000 °.

Contrary to the above description, the substrate semiconductor (1) is N
In the case of a semiconductor layer (7) for forming a depletion layer and a carrier path above the V-shaped groove, the semiconductor layer (7) is of P ⁺ type,
The counter electrode is Pt, Au, Ru a material of high work function such as Ni. These materials were formed at a thickness of 100 to 1 μm. However, in the case of Au, Pt, etc., in order to make a solar cell at a low cost, the solar cell is formed to a thickness of 50 to 200 [deg.]
m was formed.

Thickness (5 to 100 mm, especially 15 to 30
The silicon nitride film (thickness of Å) (Si ₃ N ₄ or Si ₃ N _4-X 0 <X <4) may be formed by glow discharge CVD instead of plasma nitriding. In that case, two back electrodes were combined with each other. A film was not formed on the electrode. In addition, this film is a film formed in another reducing atmosphere, for example, SiC _1-X (0 <X <
1).

The insulating or semi-insulating film as described above (3)
Except for the comb-shaped electrode (5) and the external lead-out pad (21) where the surface of the semiconductor is flat, a film obtained by vacuum-depositing a counter electrode on the top surface by photoetching is used. The electrode material in the region (17) where was formed was removed. As is clear from the drawings, the main structure of the present invention is such that a counter electrode is not provided on a region having a V-shaped or trapezoidal groove, and a counter electrode and an external lead electrode (21) are provided only on a flat surface on a semiconductor. , Drawer lead (32)
Is provided.

Thus, during photo-etching for forming the counter electrode, the periphery of the counter electrode (5) and the like is flat, so that the pattern is sharp and there is no remaining metal. In addition, the silicon nitride film (3)
The number of pinholes is small. Leaks and the like hardly occur due to external mechanical stress. Further, in the region of the V-shaped or trapezoidal groove where light irradiation is performed, since there is no N ⁺ or P ⁺ semiconductor layer, there is no light absorption loss there, and light can be efficiently introduced into the V-shaped groove inside, Electrons and holes can be effectively generated by the incident light. In addition, since there is no conductor in the groove, even if pinholes and leaks occur, there is no problem in physical properties at all.

FIG. 1 (D) shows that an anti-reflection film (10) of silicon nitride, tantalum oxide, SiO, etc. is formed on this upper surface to a thickness of 600 to 900 mm, and the reflectance of the irradiation light (20) is increased by the reaction. It is reduced to 0.5 to 2.0% to achieve extremely ideal irradiation, and the counter electrode and the like are used as a protective film that does not cause a disconnection short due to mechanical damage and the like. Oxygen at the interface,
The purpose of the present invention is to prevent the deterioration of reliability from occurring due to the contamination of moisture due to moisture. For this reason, the antireflection film was formed by the plasma CVD method so as to completely coat the peripheral portion (25).

In this example, under the condition of AM1, 1
A conversion efficiency of 8.5-20.5% was obtained, and a FF of 0.82-0.90 was obtained. Since the light irradiation (20) was applied twice in the V-shaped groove, the reflectance could be reduced to 12% or less without forming an antireflection film. Although the counter electrode in the present invention is comb-shaped, it may be mesh-like or fish-bone-like, and is characterized by selectively separating the light irradiation surface having grooves and the existence of the counter electrode basically. I have.

Embodiment 2 FIG. 2 shows another embodiment of the present invention. As in FIG. 1, an N ⁺ or P ⁺ semiconductor layer (7) is provided above the V-shaped groove, thereby efficiently forming a depletion layer above the semiconductor (1). Are efficiently transferred to the electrode section (5) in the N ⁺ or P ⁺ layer. In addition, light is irradiated twice in the V-shaped groove, in which there is no N ⁺ or P ⁺ layer, so that light can efficiently reach inside the semiconductor (1).

In order to provide such a V-shaped groove only on the light-irradiated surface and to make the semiconductor layer under the V-shaped groove more easily inverted, the opposite conductive type of 0.5 μm or less, particularly in the vicinity of the upper surface of the substrate semiconductor (1). A layer (7) with a thickness of 20 to 500 mm is provided. In addition, an insulating or semi-insulating film (3) and a counter electrode (5) are provided on the upper side.

In the structure shown in FIG. 2, a semiconductor layer (7) of the opposite conductivity type is provided only above the V-shaped groove, and the semiconductor layers extend continuously below the counter electrode (5). It is effective to make the pattern. Then, one of the electron and the hole formed by light irradiation in the semiconductor below the V-shaped groove is attracted to the opposite conductivity type semiconductor layer (7) and opposed through the floating channel on the upper side. Drift with little loss under the electrode. In addition, when light irradiation is performed on the semiconductor below the V-shaped groove, the irradiation light is characterized in that there is no loss due to absorption of impurity scattered light by the opposite conductivity type layer.
Due to such characteristics, in the present invention, the photoelectric conversion efficiency was able to be obtained under the condition of AM1 up to 20.5%, exceeding the theoretical limit of silicon of 20%. In the drawing, SiO or tantalum oxide is formed to a thickness of 700 to 900 mm as an antireflection film. In addition, with this structure, near-infrared wavelengths can be detected, and photoresponse characteristics can be produced to the extent that 950 nm semiconductor laser light can be used.

[0037]

As a result, the conversion efficiency under AM1 is 1
It was improved to 8%. In addition, the characteristic under a fluorescent lamp (300 Lx), which is a representative of short wavelength light, is 50 μW / cm ^2.
Met. The floating channel MIS type photoelectric conversion device of the present invention is excellent not only in the magnitude of the effect of the floating channel, but also in its mass, that is, the electrode portion is flat and the other portions are uneven, so that mass production is excellent. For the first time, it was possible to increase the mass production yield to 90% or more. Regarding reliability, 150 ° C
No abnormalities were found under the 1000-hour standing test.

Although the present invention is based on a single crystal of silicon, it may be a semiconductor having a polycrystalline, semi-amorphous, or amorphous structure, or a semiconductor such as silicon manufactured by a rapid quenching method or a dentite method. In addition to silicon, germanium or other compound semiconductors may be used. The plane pattern of the V-shaped or trapezoidal groove is not limited to the shape (square) of this embodiment, but may be a rectangle or an octagon.

[Brief description of the drawings]

FIG. 1 shows a longitudinal section of an embodiment for producing the invention.

FIG. 2 is a longitudinal sectional view of another photoelectric conversion device of the present invention.

Claims (1)

(57) [Claims] 1. A semiconductor substrate of one conductivity type, and a semiconductor layer of a conductivity type opposite to the semiconductor substrate is provided on the upper portion of the substrate, and a V-shaped or inverted trapezoidal groove is provided on the upper portion of the substrate. Depth while leaving the semiconductor layer above the semiconductor substrate,
Wherein said over semiconductor layer and the interface between the semiconductor substrate provided led to the inside of the one conductivity type semiconductor, the counter electrode portion of the semiconductor top surface have a semiconductor layer which is the remaining upper
A conductive semiconductor layer provided on the upper surface of the convex portion having a trapezoidal upper surface and remaining on the convex portion.
Is a photoelectric conversion device provided in connection with each other .