JP2004047824A - Solar cell and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solar cell which is much improved in efficiency through a method, wherein carriers are restrained from being recombined by reducing the electrical contact between an electrode material and a semiconductor in area, an open end voltage is increased, and the electrode material is reduced in electrical resistance, and to provide its manufacturing method. <P>SOLUTION: A light-receiving plane is formed on the one surface of a semiconductor substrate, and grooves cut in a p-type semiconductor layer 33 or an n-type semiconductor layer 30 arranged on the other surface of the semiconductor substrate are filled up with an electrode material for the formation of the solar cell. The grooves are each filled with the electrode material as high above their bottoms as prescribed, the electrode material filling the grooves is thermally treated so as to come into ohmic contact with the p-type semiconductor layer 33 or the n-type semiconductor layer 30 for the formation of a first buried electrode 24, and the electrode material additionally and completely fills the grooves so as to be bonded to the first embedded electrode 24 for the formation of a second embedded electrode 27. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solar cell and a method of manufacturing the same, and more particularly, to a solar cell having a back contact structure and a method of manufacturing the same.
[0002]
[Prior art]
Conventionally, in order to ensure the area of the light receiving surface as large as possible, a solar cell in which an electrode is formed on the side opposite to the light receiving surface has been developed. For example, JP-A-3-165578 discloses a solar cell in which ap ⁺ -type silicon layer and an n ⁺ -silicon layer are alternately arranged as a positive electrode and a negative electrode on one surface of a crystalline silicon substrate. I have.
[0003]
In a partial cross-sectional view of a solar cell according to a conventional example, a U-shaped groove made of a p ⁺ -type silicon layer and a U-shaped groove made of an n ⁺ -type silicon layer are formed on the back side of a p-type crystalline silicon substrate. Have been. Further, a metal for a negative electrode made of silver is embedded in the groove made of the n ⁺ type silicon layer, and a positive electrode made of an aluminum-silicon alloy is embedded in the groove made of the p ⁺ type silicon layer. An electrode metal is embedded.
[0004]
According to the solar cell according to the conventional example, the contact area between the p ⁺ -type silicon layer and the n ⁺ -type silicon layer and the metal for the positive electrode and the metal for the negative electrode embedded in these layers is increased, and the contact between them is increased. Resistance can be reduced. Further, since the thickness of the metal for the positive electrode and the metal for the negative electrode can be increased, the electric resistance to the current flowing through the metal for the electrode can also be reduced. Further, since the p ⁺ -type silicon layer and the n ⁺ -type silicon layer have a groove shape as described above, the distance between the concave portion and the light receiving surface of the crystalline silicon substrate is reduced, and the electrode is formed without carrier recombination. The number of carriers (free electrons and free holes) that reach the gate electrode increases, so that the photoelectric conversion efficiency can be improved.
[0005]
[Problems to be solved by the invention]
However, in the above-mentioned prior art, the electrode material and silicon are joined on the entire surface of the groove to form an ohmic contact, so that the recombination of carriers is promoted due to an increase in the electric contact area, and thus the conversion efficiency is reduced. In addition, when the grooves are filled with a metal paste and then fired at a high temperature, which is a condition for obtaining ohmic contact, the electric resistance of the electrode material increases, and as a result, the characteristics of the solar cell deteriorate. .
[0006]
An object of the present invention is to solve the above-mentioned problems, to suppress the recombination of carriers by reducing the electrical contact area between the electrode material and the semiconductor, to increase the open-circuit voltage, and to reduce the electric resistance of the electrode material. It is an object of the present invention to provide a solar cell having a high efficiency by lowering it and a manufacturing method thereof.
[0007]
Means and action for solving the problem
The solar cell according to the present invention is configured as follows to achieve the above object.
[0008]
In a first solar cell (corresponding to claim 1), a light receiving surface is formed on one surface side of a semiconductor substrate, and an electrode material is formed in a groove formed of a p-type semiconductor layer or an n-type semiconductor layer provided on the other surface side. In the filled solar cell, a first buried electrode which is buried with an amount of electrode material buried from the bottom of the groove to a predetermined height and heat-treated under the condition of ohmic contact with a p-type semiconductor layer or an n-type semiconductor layer; The groove is characterized by being filled with a second buried electrode completely buried so as to be bonded to the first buried electrode with a material.
[0009]
According to the first solar cell, a first buried electrode that is buried with an amount of an electrode material buried to a predetermined height from the bottom of the groove and heat-treated under the condition of ohmic contact with the p-type semiconductor layer or the n-type semiconductor layer; Since the groove is filled with the second buried electrode that is completely buried so as to be bonded to the first buried electrode with the electrode material, the first buried electrode provides electrical contact, The area can be reduced, the recombination of carriers can be suppressed, and the open-circuit voltage can be increased. Further, since the groove is filled with the second embedded electrode, a high efficiency solar cell can be obtained by reducing the electric resistance of the electrode material used for the electrode.
[0010]
In the second solar cell (corresponding to claim 2), the semiconductor substrate is preferably crystalline silicon, the p-type semiconductor layer is a p-type silicon layer, and the n-type semiconductor layer is an n-type silicon layer. It is characterized by.
[0011]
According to the second solar cell, the semiconductor substrate is crystalline silicon, the p-type semiconductor layer is a p-type silicon layer, and the n-type semiconductor layer is an n-type silicon layer. A solar cell can be obtained.
[0012]
According to a first method for manufacturing a solar cell (corresponding to claim 3), a light-receiving surface is formed on one surface of a semiconductor substrate, and a groove formed of a p-type semiconductor layer or an n-type semiconductor layer is provided on the other surface. In a method for manufacturing a solar cell in which an electrode material is filled, a first electrode embedding step of embedding an amount of the electrode material from the bottom of the groove to a predetermined height, and the electrode material embedded in the first electrode embedding step and a p-type electrode. It is characterized by including a first heat treatment step in which heat treatment is performed under conditions that make ohmic contact with the semiconductor layer or the n-type semiconductor layer, and a second electrode filling step in which the groove is completely filled with the electrode material.
[0013]
According to the first method for manufacturing a solar cell, a first electrode embedding step of embedding the electrode material with an amount of embedding from the bottom of the groove to a predetermined height, the electrode material embedded in the first electrode embedding step and the p-type Since the method includes a first heat treatment step in which heat treatment is performed under the condition of ohmic contact with the semiconductor layer or the n-type semiconductor layer, and a second electrode filling step in which the groove is completely filled with the electrode material, the electrical contact area can be reduced. As a result, carrier recombination can be suppressed, and the open-circuit voltage can be increased. In addition, after the second electrode embedding step, the characteristics of the solar cell can be improved by firing at a low temperature under conditions that reduce the electrical resistance of the electrode material used for the electrode.
[0014]
In a second method for manufacturing a solar cell (corresponding to claim 4), in the above method, preferably, the semiconductor substrate is crystalline silicon, the p-type semiconductor layer is a p-type silicon layer, and the n-type semiconductor layer is n. It is characterized by being a type silicon layer.
[0015]
According to the second method for manufacturing a solar cell, the semiconductor substrate is crystalline silicon, the p-type semiconductor layer is a p-type silicon layer, and the n-type semiconductor layer is an n-type silicon layer. A highly efficient solar cell can be obtained.
[0016]
A third method for manufacturing a solar cell (corresponding to claim 5) is characterized in that, in the above method, preferably, the metal material is a metal paste.
[0017]
According to the third method for manufacturing a solar cell, since the metal material is a metal paste, the electrodes can be easily formed.
[0018]
A fourth solar cell manufacturing method (corresponding to claim 6) is characterized in that, in the above method, preferably, the metal paste is a silver paste.
[0019]
According to the fourth method for manufacturing a solar cell, since the metal paste is a silver paste, the manufacturing cost can be reduced.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[0021]
1 and 2 are a cross-sectional view of a part of the solar cell according to the present embodiment and a plan view showing an electrode pattern on a surface opposite to a light receiving surface. The solar cell 10 includes a light receiving unit 11, a carrier generation unit 12, and an electrode unit 13. The light receiving section 11 has a texture structure, and the surface of the structure is covered with an antireflection film 14. As the antireflection film 14, a thin film made of, for example, titanium oxide (TiO ₂ ) and silicon oxide (SiO ₂ ) is used. By forming the light receiving unit 11 in a texture structure covered with the antireflection film 14, more incident light enters the carrier generation unit 12, and the conversion efficiency of the solar cell 10 can be increased.
[0022]
The carrier generation unit 12 is composed of the semiconductor 15, and the light incident from the light receiving unit 11, in particular, light having energy equal to or greater than the band gap of the semiconductor 15 excites electrons in the valence band to the conduction band and is free to enter the conduction band. Electrons are generated, and free holes are generated in the valence band. Free electrons and free holes are called carriers. Before the carriers generated by the carrier generation unit 12 are recombined with each other, they reach the electrode unit 13 by diffusion, so that a current can be extracted by the electrode unit 13. Therefore, the conversion efficiency of the solar cell 10 can be increased by using a semiconductor in which the recombination of carriers hardly occurs, that is, by using a semiconductor having a long carrier life. Therefore, high-resistance crystalline silicon is used as the semiconductor 15 used for the carrier generation unit 12.
[0023]
The electrode section 13 is where the carrier generated by the carrier generation section 12 is extracted as a current. The electrode section 13 is formed on the surface of the semiconductor 15 opposite to the light receiving section 11 side. In the electrode section 13, positive electrodes 16 and negative electrodes 17 are alternately formed in a V-shaped groove 18 having a triangular cross section on the surface of the semiconductor 15. In the V groove 18, p ⁺ semiconductor layers 19 and n ⁺ semiconductor layers 20 are formed alternately. The surface of the V-groove 18 in which the p ⁺ semiconductor layer 19 and the n ⁺ semiconductor layer 20 are formed is covered with an oxide film 21.
[0024]
FIG. 3 is a sectional view showing an electrode. The V groove 18 is filled with the same electrode material, for example, silver. At a predetermined height from the bottom 23 of the V-groove 18, a first embedded electrode 24 is formed. The electrode material is directly bonded to the semiconductor by firing through an oxide film, and the electrical contact portions 25 and 26 are formed. Form. The predetermined height is determined such that the conversion efficiency is maximized in consideration of the open-circuit voltage _VOC of the solar cell and the fill factor FF. In the electrical contact portions 25 and 26, the electrode material is in ohmic contact with the p ⁺ type semiconductor layer 19 and the n ⁺ type semiconductor layer 20. In the electrode portion 13, a second buried electrode 27 is formed except for the bottom portion 23 of the V-groove 18, and an oxide film is present between the electrode material and the semiconductor 15 as an insulator without fire-through. Thus, recombination of carriers generated by photoelectric conversion, that is, free electrons and free holes, can be prevented in portions other than the electrical contact portions 25 and 26 outside the V-groove 18. Therefore, the oxide film 21 is called a recombination prevention film. A passivation film, for example, silicon oxide (SiO ₂ ) is deposited on the surface on which the electrode unit 13 is formed.
[0025]
Next, the operation of the solar cell 10 of the present embodiment will be described. Light incident from the light receiving surface of the light receiving unit 11 of the solar cell 10 is suppressed in reflection by the light receiving surface on which the antireflection film 14 having the texture structure is formed, and is transmitted through the semiconductor 15. Of the light transmitted through the semiconductor 15, light having energy equal to or greater than the band gap of the semiconductor 15 excites electrons in the valence band to the conduction band in the carrier generation unit 12 and generates free holes in the valence band. Generates free electrons in the conduction band. Free electrons and free holes diffuse in the semiconductor 15, some recombine, and some reach the electrode portion 13. Since a high-resistance semiconductor with few impurities is used as the semiconductor, the amount of carriers that cause recombination is small, and the amount of carriers that reach the electrode portion 13 without being recombined is large.
[0026]
Among the carriers, free electrons flow into the negative electrode 17 through the n ⁺ semiconductor layer 20 and the electrical contact 25, and free holes flow into the positive electrode 16 through the p ⁺ semiconductor layer 19 and the electrical contact 24. At this time, except for the electrical contact portions 25 and 26 between the first buried electrode 24 of the V-groove 18 and silicon, a recombination prevention film made of an oxide film is formed. Since no electrical contact is formed, recombination of carriers on the surface of the V-groove is suppressed. Then, the carrier that has reached the electrode portion 13 is connected to the first buried electrode 24 formed up to a predetermined height from the bottom portion 23 of the V-groove 18 and the electrical contact portions 25 and 26 between the silicon and the second carrier formed of silver. 1 flows into one embedded electrode 24. Thereby, a current can be extracted.
[0027]
At this time, since only the contact portion between the first buried electrode 24 and the silicon near the bottom portion 22 of the V-groove 18 is an electrical contact portion, the area of the electrical contact portion is small, and therefore, the open-circuit voltage (V _OC ) Can be increased. Further, the electrode has a small electric resistance of the electrode material used for the second buried electrode, and the area increases from the electric contact portion to the upper portion in the V-groove. , The fill factor (FF) increases. Furthermore, since most of the V-grooves are covered with the recombination prevention film by the oxide film, carrier recombination near the electrode portion is suppressed, and most of the carriers generated in the carrier generation portion are removed from the electrical contact portion. Flow into the electrode. With these, conversion efficiency can be improved. In addition, since the p ⁺ semiconductor layer 19, the n ⁺ semiconductor layer 20, and the light receiving section 11 are close to each other, it is not necessary to make the semiconductor substrate thin, so that the semiconductor substrate or a solar cell using the substrate is hard to be broken and strong.
[0028]
Next, a method for manufacturing the solar cell of the present embodiment will be described with reference to FIG. First, an oxide film is formed on both surfaces of a high-resistance silicon (100) substrate 28 having a thickness of about 250 μm (micron). This oxide film is formed, for example, by thermal oxidation. Thereafter, the oxide film formed on one surface of the silicon substrate is removed in a stripe shape at a predetermined width, for example, a width of 100 μm, and at an interval of 300 μm by photolithography or laser etching.
[0029]
Thereafter, anisotropic etching is performed with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) or the like to form stripe-shaped V-shaped grooves having a triangular cross section at intervals of 300 μm.
[0030]
Next, the substrate is placed in a diffusion furnace to diffuse phosphorus. Thereby, as shown in FIG. 4A, the n ⁺ type silicon layer 30 is formed in the silicon portion where the V groove 29 is formed. At this time, in the diffusion furnace, the gas serving as the phosphorus material is stopped, and then only oxygen is introduced, so that the surface of the V groove 29 in which phosphorus is diffused is covered with an oxide film.
[0031]
Next, the oxide film is removed to a width of 100 μm by photolithography or laser etching so that the distance between the V-groove 29 and the V-groove of the oxide film 31 during the 300 μm width is 100 μm.
[0032]
Thereafter, anisotropic etching is performed with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) or the like to form V-shaped grooves 32 having a triangular cross section at intervals of 100 μm.
[0033]
Next, the substrate is placed in a diffusion furnace to diffuse boron. Thereby, as shown in FIG. 4B, ap ⁺ type silicon layer 33 is formed in the silicon portion where the V groove 32 is formed between the V grooves 29 in which the n ⁺ type silicon layer 30 is formed. At this time, in the diffusion furnace, the gas serving as the boron material is stopped, and then only oxygen is introduced, so that the surface of the V-shaped groove 32 in which boron is diffused is covered with an oxide film. FIG. 5 is a perspective view showing a state where a V-groove on the back surface of silicon is formed. V-grooves 29 and 32 are formed in the substrate 28, and impurity diffusion is performed on the side surfaces thereof to form ap ⁺ -type silicon layer 33 and an n ⁺ -type silicon layer 30.
[0034]
The other surface of the silicon substrate 28 is anisotropically etched with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) or the like to form a striped texture structure having a triangular cross section. Then, by performing dry oxidation in a diffusion furnace, an oxide film is formed on the other surface (FIG. 4C).
[0035]
Thereafter, titanium oxide (TiO ₂ ) is deposited on both surfaces at room temperature by sputtering or the like. As a result, a light receiving surface having an antireflection film having a texture structure on the other surface is formed.
[0036]
Next, the step of embedding the electrode material will be described. This step is performed in two stages. That is, a first electrode embedding step of embedding an amount of the electrode material from the bottom of the groove to a predetermined height, and an ohmic contact between the electrode material embedded in the first electrode embedding step and the p-type silicon layer or the n-type silicon layer. And a second electrode embedding step of completely embedding the groove with an electrode material. In the first electrode embedding step, as shown in FIG. 4D, a silver paste is applied to the V-grooves 29 and 32 having ap ⁺ silicon layer and an n ⁺ -type silicon layer, and the surfaces of which are covered with an oxide film. Embed. At this time, the silver paste is filled only up to a predetermined height from the bottom of the V-grooves 29 and 32, and once baked, an electrical contact between silicon and silver is formed only up to a predetermined height from the bottom. FIG. 6 is a perspective view of the substrate on which the V-grooves 29 and 32 are formed at that time. The grooves are filled with a small amount of silver paste 34 and fired to make electrical contact with the electrodes. Filling method and work are changed by adjusting the ratio of paste composition, components other than silver, such as solvents and resins, which are volatilized or burned off before firing, and components that contribute to electrical contact such as silver and glass frit. The electrical contact area can be changed without any change.
[0037]
Thereafter, annealing is performed in a hydrogen atmosphere in order to reduce contact resistance and improve carrier life.
[0038]
In the next second electrode embedding step, silver is embedded in the entire V-grooves 29 and 32 and fired at a temperature lower than the previous firing temperature. As a result, no electrical contact is made except for a predetermined height from the bottom in the V-grooves 29 and 32. In addition, since the firing temperature is low, the electric resistance of the electrode material used for the second embedded electrode can be reduced. FIG. 7 is a perspective view of the substrate on which the V-groove is formed at that time. In order to reduce the electrical resistance in the length direction of the groove, the silver paste 35 is filled again and fired to increase the thickness. The firing at this time can be performed at a lower temperature than in the previous step, and there is no damage to the substrate. Thereby, the cross section of the V-groove is as shown in FIG. In this manufacturing method, an electric contact area can be reduced by first filling and firing a small amount of silver paste. In addition, the sintering can be performed under the best condition by focusing only on the contact resistance. Next, since a sufficient silver paste is filled and firing is performed at a low temperature, firing can be performed under the best conditions by focusing only on the resistance of the electrode itself. Further, by changing the ratio of the paste component, the component burned and removed at the time of firing, and the component contributing to the electrical contact, the amount of silver initially charged can be controlled.
[0039]
Thereafter, wiring is formed by applying conductive ink, which is often covered with a protective film on the surface on the side of the electrode portion, and dicing is performed to produce a solar cell.
[0040]
FIG. 8 shows the short-circuit current (J _SC ), open-circuit voltage (V _OC ), fill factor (FF), and conversion efficiency (η) of the solar cell thus formed, and FIG. 9 shows the conversion efficiency. . Sample 1 is a solar cell in which the step of embedding metal in the electrode is not divided into two steps but is performed by one step (collective electrode). Samples 3 and 4 are solar cells obtained by performing the two-step embedding step of the present invention in the step of embedding the electrode metal. Sample 4 is a solar cell having a smaller electrical contact area than Sample 3. Plot A is a value for sample 1 of the collective electrode, and plots B and C are values for samples 3 and 4 of the two-stage electrode. In sample 1 of the collective electrode, the short-circuit current (J _SC ), open-circuit voltage (V _OC ), and fill factor (FF) are lower than those of samples 3 and 4 of the two-stage electrode, and the conversion efficiency (η) is also lower. You can see that it is.
[0041]
In the two-stage electrode, the condition A of the sample 3 is optimal, the electrical contact area is small, and the open-circuit voltage (V _OC ) is improved. Further, the electrode resistance is reduced, and the fill factor (FF) is improved. Thereby, conversion efficiency is high. In condition B of sample 4, the silver contact of the first embedded electrode was further reduced, the electrical contact area was reduced, and the open-circuit voltage (V _OC ) was improved. However, since the area is too small, the electrical contact resistance increases and the fill factor (FF) decreases. Therefore, the conversion efficiency (η) decreases.
[0042]
As described above, the electric contact area can be reduced, and the open-circuit voltage (V _OC ) is improved. Also, the electric resistance of the electrode itself is reduced, and the fill factor (FF) is improved. Furthermore, the amount of silver initially charged can be controlled by changing the viscosity of the silver paste, and a small-area contact structure that leads to an improvement in open-circuit voltage (V _OC ) can be realized. Further, this structure can be realized at low cost by using a silver paste.
[0043]
Although the present embodiment has been described using crystalline silicon as the semiconductor, the semiconductor is not limited to crystalline silicon, and other semiconductors such as gallium arsenide (GaAs) can be used.
[0044]
Further, in this embodiment, an oxide film is provided between the p ⁺ type semiconductor layer or the n ⁺ semiconductor layer of the V groove and the second buried electrode to serve as a recombination prevention film. However, the oxide film is not provided. By using a metal for the second embedded electrode which does not make ohmic contact with the p + type semiconductor layer and the n + type semiconductor layer, for example, a metal forming a Schottky barrier, it prevents recombination at the interface. It can be used instead of a membrane.
[0045]
【The invention's effect】
As apparent from the above description, the present invention has the following effects.
[0046]
A first buried electrode that is buried with an amount of electrode material buried to a predetermined height from the bottom of the groove and heat-treated under conditions of ohmic junction with the p-type semiconductor layer or the n-type semiconductor layer; Since the groove is filled with the second buried electrode that is completely buried so as to be bonded to the substrate, electric contact is obtained by the first buried electrode. And the open-circuit voltage can be increased. Further, since the groove is filled with the second embedded electrode, a high efficiency solar cell can be obtained by reducing the electric resistance of the electrode material used for the electrode.
[0047]
A first electrode embedding step of embedding an amount of the electrode material from the bottom of the groove to a predetermined height, and conditions for forming an ohmic junction between the electrode material embedded in the first electrode embedding step and the p-type semiconductor layer or the n-type semiconductor layer. And a second electrode embedding step of completely embedding the groove in the electrode material, so that the electrical contact area can be reduced, carrier recombination is suppressed, and the open-circuit voltage is reduced. Can be increased. In addition, after the second electrode embedding step, the characteristics of the solar cell can be improved by firing at a low temperature under conditions that reduce the electrical resistance of the electrode material used for the electrode.
[0048]
In addition, since the semiconductor substrate is crystalline silicon, the p-type semiconductor layer is a p-type silicon layer, and the n-type semiconductor layer is an n-type silicon layer, a highly efficient solar cell can be easily obtained at a low price. .
[0049]
Since the metal material is a metal paste, the electrodes can be easily formed. Further, since the metal paste is a silver paste, the manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a part of a solar cell according to an embodiment of the present invention.
FIG. 2 is a plan view showing an electrode pattern on a surface opposite to a light receiving surface of the solar cell according to the embodiment of the present invention.
FIG. 3 is a sectional view showing an electrode.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a solar cell according to an embodiment of the present invention.
FIG. 5 is a perspective view of a state where a V-groove on the back surface of silicon is formed.
FIG. 6 is a perspective view showing a state where a V-groove on the back surface of silicon is formed.
FIG. 7 is a perspective view showing a state where a V-groove on the back surface of silicon is formed.
FIG. 8 is a table showing short-circuit current, open-end voltage, fill factor, and conversion efficiency of a solar cell.
FIG. 9 is a graph showing the conversion efficiency of a solar cell.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Solar cell 11 Light receiving part 12 Carrier generating part 13 Electrode part 14 Antireflection film 15 Semiconductor 16 Positive electrode 17 Negative electrode 18 V groove 19 p ⁺ semiconductor layer 20 n ⁺ semiconductor layer 21 oxide film 22 silver 23 bottom 24 first burying Electrodes 25 and 26 Electrical contact 27 Second embedded electrode

Claims (6)

A light receiving surface is formed on one side of the semiconductor substrate,
In a solar cell in which a groove formed of a p-type semiconductor layer or an n-type semiconductor layer disposed on the other surface is filled with an electrode material,
A first buried electrode which is buried with an electrode material in an amount to be buried from the bottom of the groove to a predetermined height, and which is heat-treated under ohmic contact with the p-type semiconductor layer or the n-type semiconductor layer;
A solar cell, wherein the groove is filled with a second buried electrode that completely fills the groove with the electrode material so as to be joined to the first buried electrode. The solar cell according to claim 1, wherein the semiconductor substrate is crystalline silicon, the p-type semiconductor layer is a p-type silicon layer, and the n-type semiconductor layer is an n-type silicon layer. A light receiving surface is formed on one side of the semiconductor substrate,
In a method for manufacturing a solar cell, in which a groove made of a p-type semiconductor layer or an n-type semiconductor layer disposed on the other surface is filled with an electrode material,
A first electrode embedding step of embedding an amount of electrode material to be embedded from the bottom of the groove to a predetermined height;
A first heat treatment step of heat-treating the electrode material embedded in the first electrode embedding step and ohmic contact with the p-type semiconductor layer or the n-type semiconductor layer;
And a second electrode embedding step of completely embedding the groove with the electrode material. The method according to claim 3, wherein the semiconductor substrate is crystalline silicon, the p-type semiconductor layer is a p-type silicon layer, and the n-type semiconductor layer is an n-type silicon layer. 4. The method according to claim 3, wherein the metal material is a metal paste. The method according to claim 5, wherein the metal paste is a silver paste.

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