KR20190041989A - Solar cell manufacturing method and solar cell - Google Patents

Abstract

The present invention relates to a solar cell manufacturing method and a solar cell. According to an embodiment of the present invention, the solar cell manufacturing method includes: a step of forming a dopant layer on a side of a semiconductor substrate; a step of selectively etching the dopant layer located in a first area of the semiconductor substrate; a step of forming a conductive area by treating the semiconductor substrate with heat; a step of removing the rest of the dopant layer; and a step of forming a first electrode in a second area of the semiconductor substrate and forming a second electrode on the other side. Through the thermal treatment step, a low-concentration doping part is formed in the first area and a high-concentration doping part is formed in the second area. Moreover, according to an embodiment of the present invention, the solar cell includes: a semiconductor substrate; a first conductive area including the low-concentration and high-concentration doping parts on a side of the semiconductor substrate; and first and second electrodes in the first conductive area. The semiconductor substrate includes first and second areas. In each of the first areas, the low-concentration and high-concentration doping parts are located and in each of the second areas, the high-concentration doping part is located. The low-concentration and high-concentration doping parts located in the first area are placed longitudinally in a second direction intersecting with the first direction.

Description

SOLAR CELL MANUFACTURING METHOD AND SOLAR CELL [0002]

The present invention relates to a solar cell manufacturing method and a solar cell.

With the recent depletion of existing energy resources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells produce electric energy from solar energy, and they are attracting attention because they have abundant energy resources and there is no problem about environmental pollution.

Typical solar cells have a substrate made of different conductivity type semiconductors, such as p-type and n-type, an emitter layer, and electrodes connected to the substrate and the emitter, respectively. At this time, a p-n junction is formed at the interface between the substrate and the emitter.

When light is incident on such a solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes, so that electrons and holes are directed toward the n-type semiconductor and the p- And is collected by an electrode electrically connected to the substrate and the emitter portion, and these electrodes are connected to each other by electric wires to obtain electric power.

Conventionally, in such a solar cell, in order to further improve the contact resistance between the semiconductor substrate and the electrode, a selective doping structure is adopted, but a heavily doped layer is formed between the semiconductor substrate and the electrode, A lightly doped layer was formed in the region of the semiconductor substrate.

Conventionally, such a selective emitter structure is used as a laser. However, in the case of using a laser, there is a problem that the light absorptance of the semiconductor substrate is lowered, for example, the concavo-convex structure formed on the front surface of the semiconductor substrate is damaged by the laser.

The present invention provides a solar cell manufacturing method and a solar cell.

A method of fabricating a solar cell according to an example of the present invention includes: forming a dopant layer on a surface of a semiconductor substrate having texturing irregularities, the dopant layer including impurities as a whole; Selectively etching at least a portion of a dopant layer located in a first region where the first electrode is not formed among the entire one surface of the semiconductor substrate; A heat treatment step of heat treating the semiconductor substrate to form a conductive type region containing impurities; A remaining dopant layer removing step of removing a dopant layer remaining on one surface of the semiconductor substrate; A first electrode forming step of forming a first electrode in a second region of the entire surface of the semiconductor substrate excluding the first region; And a second electrode formation step of forming a second electrode on the opposite side of the semiconductor substrate, wherein a low concentration doped portion in which impurities are doped at a low concentration is formed in the first region of the semiconductor substrate by the heat treatment step, 2 region is formed with a heavily doped portion in which impurities are doped at a higher concentration than the lightly doped portions in the first region.

Here, the thickness of the dopant layer formed in the dopant layer forming step may be between 40 nm and 80 nm.

In addition, the depth at which the dopant layer is etched in the selective etching step may be greater than one-half of the dopant layer thickness and less than the dopant layer thickness.

Here, the dopant layer located in the first region in the selective etching step may be selectively etched by a laser.

As an example, in the selective etching step, the dopant layer located in the first region may be etched as a whole.

Alternatively, however, the dopant layer located in the first region in the selective etching step may be etched into a plurality of regions having a pattern spaced in the first direction.

In this case, a lightly doped portion spaced apart in the first direction is formed in the plurality of regions in which the dopant layer is etched in the first region by the heat treatment step, and the lightly doped portions are formed in the remaining regions except for the plurality of regions in the second direction A long and highly doped portion can be formed.

As an example, the etch width of each of the first direction of the dopant layer etched into the plurality of regions in the selective etching step may be greater than one fourth of the spacing between the first electrodes and less than twice the spacing between the first electrodes .

In addition, the etch intervals of the first direction of the dopant layers etched into the plurality of regions in the selective etching step may be larger than 1/4 of the first electrode width and smaller than the spacing between the first electrodes.

The first region and the second region may be positioned in a first direction and the first region and the second region may be alternately positioned in a second direction intersecting the first direction.

In addition, the step of removing the remaining dopant layer may be performed by forming an etch stopping film entirely on the opposite surface of the semiconductor, and then immersing the semiconductor substrate in the etchant.

Here, the etchant used in the step of removing the remaining dopant layer may be a hydrofluoric acid (HF) diluent.

The second region is formed in a first direction and a second direction intersecting the first direction. In the first electrode formation step, the first electrode is formed in a second region formed in the first direction, and the second region is formed in the second direction. And may not be formed in the second region.

According to another aspect of the present invention, there is provided a solar cell including: a semiconductor substrate having texturing concaves and convexes on one surface; A first conductive type region doped with an impurity of a first conductive type or a second conductive type formed on one surface of a semiconductor substrate and having a lightly doped region doped with impurities at a low concentration and a highly doped region doped at a higher concentration than the lightly doped region; A first electrode connected to the heavily doped region in the first conductivity type region; Wherein the semiconductor substrate comprises a first region in which the first electrode is not located and a second region in which the first electrode is located and each of the first regions is doped with low concentration Concentration doping portion is located in each of the first regions, the first doped portion is located in each second region, and the first doped portion is located in the second region in the first direction. The first doped portion is connected to the heavily doped portion located in the second region, And the heavily doped region and the heavily doped region are alternately arranged in the first direction, and each of the heavily doped region and the heavily doped region is formed in a second direction that intersects the first direction.

Here, the first direction width of the lightly doped portion located in the first region may be larger than 1/4 of the interval between the first electrodes and smaller than twice the interval between the first electrodes.

The first direction width of the heavily doped region located in the first region may be larger than 1/4 of the first electrode width and smaller than the distance between the first electrodes.

The first directional width of the lightly doped region located in the first region may be equal to or larger than the first directional width of the highly doped region located in the first region.

The semiconductor substrate may further include a second conductivity type region on the opposite surface of the semiconductor substrate, the second conductivity type region including an impurity opposite to the impurity doped in the first conductivity type region.

In addition, a control passivation film formed of a dielectric material may be further formed between the second conductive type region and the semiconductor substrate, and the thickness of the control passivation film may be between 0.5 nm and 2.5 nm.

The method for manufacturing a solar cell according to the present invention is a method for manufacturing a solar cell, which comprises selectively etching a portion of a dopant layer in a semiconductor substrate to form a conductive region having a structure including a high concentration doping portion and a low concentration doping portion, Thus, the efficiency of the solar cell can be further improved.

The solar cell according to the present invention is characterized in that the heavily doped portion is located in a region where the first electrode is not located in the solar cell and the pattern of the heavily doped portion is formed to be long in a direction crossing the first electrode, So that it can be smoothly performed.

1A and 1B are diagrams for explaining an example of a solar cell manufactured according to the manufacturing method of the present invention.
2 is a view for explaining another example of a solar cell manufactured according to the manufacturing method of the present invention.
3 is a flowchart for explaining a solar cell manufacturing method according to the first embodiment of the present invention.
FIGS. 4 to 10 are views for explaining the flow chart shown in FIG. 3 in more detail.
FIGS. 11 and 12 are diagrams for explaining solar cells of other structures that can be manufactured by the solar cell manufacturing method according to the first embodiment of the present invention.
13 is a view for explaining an example of a solar cell manufactured according to the second embodiment of the present invention.
14 is an enlarged plan view of the portion K in Fig.
15 is a view for explaining a selective etching method in a solar cell manufacturing method according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

The front surface may be a surface of the semiconductor substrate to which the direct light is incident, and the rear surface may be the opposite surface of the semiconductor substrate on which no direct light is incident or on which reflected light other than direct light may be incident.

In addition, the fact that any two values are equal means that the error range is equal to or less than 10%.

Hereinafter, a solar cell according to the present invention will be described with reference to the accompanying drawings.

1A and 1B are diagrams for explaining an example of a solar cell manufactured according to the manufacturing method of the present invention.

More specifically, FIG. 1A is a partial perspective view of a solar cell according to an example of the present invention, and FIG. 1B is a partial cross-sectional view of the solar cell shown in FIG. 1A.

 1A, an example of a solar cell according to the present invention includes a semiconductor substrate 110, a first conductive type region 120, an antireflection film 130, a second conductive type region 170, a rear passivation film 140, A second electrode 190, a first electrode 140, and a second electrode 150.

1A, the solar cell according to the present invention includes the antireflection film 130 and the rear passivation film 190. However, the present invention is also applicable to the case where the antireflection film 130 and the rear passivation film 190 are formed It is also possible to omit it.

However, in consideration of the efficiency of the solar cell, since it is better to include the antireflection film 130 and the rear passivation film 190, it is preferable that the antireflection film 130 and the rear passivation film 190 are included For example.

The semiconductor substrate 110 may be formed of at least one of monocrystalline silicon and polycrystalline silicon doped with impurities of the first conductivity type or the second conductivity type. In one example, the semiconductor substrate 110 may be formed of a single crystal silicon wafer.

Here, the first conductive type impurity or the second conductive type impurity contained in the semiconductor substrate 110 may be included. Wherein the impurity of the first conductivity type may be either an n-type or p-type conductivity type and the impurity of the second conductivity type may be an impurity opposite to the conductive type of the impurity selected as the impurity of the first conductivity type.

For example, if the first conductivity type is p-type, then the second conductivity type may be n-type. Alternatively, if the first conductivity type is n-type, the second conductivity type may be p-type.

Hereinafter, the case where the first conductivity type is p-type, the case where the second conductivity type is n-type will be described as an example, and the case where the semiconductor substrate 110 contains n-type impurity which is the impurity of the second conductivity type will be described as an example .

When the semiconductor substrate 110 has a p-type conductivity type, impurity of a trivalent element such as boron (B), gallium, indium, or the like is doped in the semiconductor substrate 110. However, when the semiconductor substrate 110 has an n-type conductivity type, impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) may be doped into the semiconductor substrate 110.

Hereinafter, the case where the impurity contained in the semiconductor substrate 110 is an impurity of the second conductivity type and is n-type will be described as an example. However, the present invention is not limited thereto.

The semiconductor substrate 110 may have a plurality of texturing irregularities on the front and rear surfaces thereof. The first conductive type region 120 located on the front surface of the semiconductor substrate 110 may have an uneven surface and the second conductive type region 170 located on the rear surface of the semiconductor substrate 110 may have an uneven surface. have.

Here, the texturing irregularity means irregularities formed on the surface of the solar cell to reduce reflected light. For example, the texturing irregularities may have a pyramidal shape.

Accordingly, the amount of light reflected from the front surface of the semiconductor substrate 110 decreases, and the amount of light incident into the semiconductor substrate 110 increases.

The first conductive type region 120 is located on the front surface of the semiconductor substrate 110 and may contain an impurity of the first conductive type or the second conductive type. In one example, the first conductivity type region 120 may contain a p-type impurity which is an impurity of the first conductivity type.

Hereinafter, the case where the first conductivity type region 120 includes the impurity of the first conductivity type is described as an example, but this is merely an example. Alternatively, the first conductivity type region 120 may contain an impurity of the second conductivity type .

Accordingly, when the semiconductor substrate 110 contains an impurity of the second conductivity type, the first conductivity type region 120 forms a pn junction with the semiconductor substrate 110 and functions as an emitter .

Hereinafter, a case where the first conductivity type region 120 serves as an emitter portion will be described as an example.

Therefore, when the semiconductor substrate 110 is n-type and the first conductivity type region 120 is p-type, holes move toward the first conductivity type region 120 and electrons can move toward the back side of the semiconductor substrate 110 have.

The first conductive type region 120 may be formed by diffusing impurities of the second conductive type on the entire surface of the semiconductor substrate 110. In this case, the first conductive type region 120 may be formed on the semiconductor substrate 110 ). ≪ / RTI >

For example, when the semiconductor substrate 110 is formed of a wafer of monocrystal silicon, the first conductive region 120 may be formed of a single crystal silicon material, and the semiconductor substrate 110 may be formed of a polycrystalline silicon wafer The first conductive type region 120 may also be formed of a multi-layered silicon material.

1A and 1B, the first conductive type region 120 may include a low concentration doping region in which impurities are lightly doped in the first region A1 of the front substrate region 110 of the semiconductor substrate 110, A high concentration doping portion 120H may be formed in the second region A2 of the semiconductor substrate 110 so that impurities are doped at a higher concentration than the low concentration doping portion 120L in the first region A1 have.

Here, the first region A1 of the semiconductor substrate 110 refers to a region where the first electrode 140 is not located, and the second region A2 refers to a region where the first electrode 140 is located .

The antireflection film 130 may be formed on at least one of an aluminum oxide film (AlOx), a silicon nitride film (SiNx), a silicon oxide film (SiOx), and a silicon oxynitride film (SiOxNy) Or may be formed as a single film or a multilayer film.

1A and 1B, the anti-reflection film 130 is formed as a single film. However, the present invention is not limited to a single film.

The antireflection film 130 reduces the reflectivity of light incident on the solar cell, increases the selectivity of a specific wavelength region, and increases the efficiency of the solar cell.

The first electrode 140 may be electrically connected to the first conductive type region 120 through the anti-reflection film 130 and directly connected to the first conductive type region 120.

The first electrode 140 may collect the carriers that have migrated toward the first conductivity type region 120.

As described above, the carriers collected by the first electrode 140 can be connected to other solar cells by an interconnector, or output to an external device.

The first electrode 140 may be formed of at least one conductive metal material. Examples of the conductive metal material include nickel (Ni), copper (Cu), silver (Ag), aluminum (Al) , Zinc (Zn), indium (In), titanium (Ti), gold (Au), and combinations thereof, but may be made of other conductive metal materials.

The first electrode 140 may be formed by forming an antireflection film 130 on the entire surface of the semiconductor substrate 110 and then applying the antireflection film 130 on the antireflection film 130 in a paste state. 130, and connecting the first conductive type region 120 to the first conductive type region 120.

The first electrode 140 may include finger electrodes elongated in a first direction x, as shown in FIGS. 1A and 1B. However, the first electrode 140 does not include only the finger electrode, and the first electrode 140 connects the plurality of finger electrodes to each other in addition to the finger electrode, and the first electrode 140 crosses the first direction x, (Y) in the second direction (y).

Next, the second conductive type region 170 is formed of a polycrystalline silicon material which is located on the rear surface of the semiconductor substrate 110 and contains a conductive type impurity opposite to the conductive type of the impurity contained in the first conductive type region 120 .

For example, the second conductivity type region 170 may contain an n-type impurity, which is an impurity of the second conductivity type, at a higher concentration than the semiconductor substrate 110.

Thus, the second conductivity type region 170 may serve as a backside electrical portion (BSF).

As shown in FIGS. 1A and 1B, the second conductive type region 170 may be formed on the rear surface of the semiconductor substrate 110, and may be in direct contact with the semiconductor substrate 110.

1A and 1B, the second conductive type region 170 is directly formed on the rear surface of the semiconductor substrate 110 to be formed as a whole, and is formed of a polycrystalline silicon material. However, the present invention is not limited thereto. 2 conductivity type region 170 may be formed of the same silicon material as the semiconductor substrate 110 by doping the impurity into the back surface of the semiconductor substrate 110.

Next, the rear passivation film 190 may be located on the entire region except the region where the second electrode 150 is formed in the rear surface of the second conductive type region 170, as shown in FIGS. 1A and 1B.

The rear passivation film 190 may be formed of a dielectric material and may be formed of a single layer or a plurality of layers and may have a specific fixed charge in consideration of the polarity of the second conductive type region 170.

The rear passivation film 190 may be formed of at least one of SiCx, SiOx, silicon nitride (SiNx), hydrogenerated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON), or hydrogenated SiON.

The rear passivation layer 190 may function to passivate the rear surface of the second conductivity type region 170.

The second electrode 150 may be electrically connected to the second conductive type region 170 through the rear passivation film 190.

The second electrode 150 may collect carriers traveling toward the second conductivity type region 170.

1A and 1B, the semiconductor substrate 110 contains an n-type impurity, the first conductivity type region 120 contains a p-type impurity, serves as an emitter, The case where the second conductive type region 170 includes an n-type type impurity to serve as a rear electric field portion has been described as an example.

However, the present invention is not necessarily limited to such a structure. As described above, the semiconductor substrate 110 contains a p-type impurity and the first conductivity type region 120 is a p-type impurity. And serves as a front electric field portion, and the second conductive type region 170 may contain an n-type impurity to serve as a rear emitter portion.

2 is a view for explaining another example of a solar cell manufactured according to the manufacturing method of the present invention.

In FIG. 2, the same parts as those described in FIGS. 1A and 1B are omitted and the other parts are mainly described.

2, a control passivation film 160 may be further formed between the semiconductor substrate 110 and the second conductive type region 170. In this case, .

2, the control passivation film 160 may be formed between the semiconductor substrate 110 and the second conductive type region 170 and may include an entire region excluding the rear edge of the semiconductor substrate 110, Lt; / RTI >

The control passivation layer 160 may pass carriers generated in the semiconductor substrate 110 in the direction of the second conductivity type region 170 and may perform a passivation function with respect to the rear surface of the semiconductor substrate 110. In addition, the control passivation film 160 may increase the open-circuit voltage Voc of the solar cell.

The control passivation film 160 may be formed of a dielectric material formed of SiCx or SiOx having high durability even at a high temperature process of 600 ° C or more. However, it is also possible to form silicon nitride (SiNx), hydrogenerated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON), or hydrogenerated SiON.

In addition, the thickness (T160) of the control passivation film 160 may be between 0.5 nm and 2.5 nm. The thickness of the control passivation film 160 may be an optimal thickness for performing a passivation function or the like.

The control passivation film 160 may be formed by an oxidation process, an LPCVD process, or a PECVD deposition process.

In addition, when the control passivation film 160 is provided, the second conductive type region 170 may be formed on the rear surface of the control passivation film 160, as shown in FIG.

2, the second conductive type region 170 is formed on the semiconductor substrate 110 and the second conductive type region 170 does not directly contact the backside or the rear surface of the semiconductor substrate 110, The open-circuit voltage Voc of the solar cell can be further improved if it is formed of a polycrystalline silicon material, which is formed on the rear surface of the semiconductor substrate 110 and spaced apart from the semiconductor substrate 110 with the control passivation film 160 interposed therebetween.

In addition, since the second conductive type region 170 is formed outside the semiconductor substrate 110 without forming the second conductive type region 170 in the semiconductor substrate 110, the second conductive type region 170 The thermal damage to the semiconductor substrate 110 can be minimized and the characteristics of the semiconductor substrate 110 can be prevented from being deteriorated.

Therefore, the solar cell as shown in FIG. 2 can further improve the efficiency. Up to now, one example of the solar cell according to the manufacturing method of the present invention has been described. Hereinafter, an example of a method of manufacturing such a solar cell Will be described.

FIG. 3 is a flowchart for explaining a first embodiment of the method for manufacturing a solar cell according to the present invention, and FIGS. 4 to 10 are views for explaining the flow chart shown in FIG. 3 in more detail.

3, a solar cell manufacturing method according to an exemplary embodiment of the present invention includes a dopant layer forming step S1, an optional etching step S2, a heat treatment step S3, a remaining dopant layer removing step S4, A first electrode forming step S5 and a second electrode forming step S6.

4, a dopant layer DPL containing impurities of the first conductive type or the second conductive type as a whole is formed on one surface of the semiconductor substrate 110 on which the texturing irregularities are formed, Can be formed.

One surface of the semiconductor substrate 110 may be one surface of the semiconductor substrate 110 having the texturing irregularities. For example, when forming the texturing irregularities on the surface of the semiconductor substrate 110, Lt; / RTI >

1A and 1B, when the first conductive type region 120 is to be formed on the entire surface of the semiconductor substrate 110, in the dopant layer forming step S1, A borosilicate glass (BSG) film containing boron (B), which is an impurity of the first conductivity type, can be formed using a dopant layer (DPL).

1A and 1B, when the second conductive type region 170 is to be formed on the front surface of the semiconductor substrate 110, in the dopant layer forming step S1, the front surface of the semiconductor substrate 110 A phosphosilicate glass (PSG) film containing phosphorus (P) which is an impurity of the second conductivity type can be formed in the dopant layer (DPL).

Hereinafter, as an example, a case where the dopant layer DPL is formed of a BSG film containing an impurity of the first conductivity type will be described as an example.

The thickness TDP of the dopant layer DPL formed in the dopant layer forming step S1 may be such that the first conductivity type region 120 located on the front surface of the semiconductor substrate 110 has a high concentration doping layer, And may be formed between 40 nm and 60 nm.

In the dopant layer forming step S1, the dopant layer DPL may be formed by chemical vapor deposition (CVD).

5, the selective etching step S2 includes a step of forming a dopant layer DPL located in a first region A1 in which the first electrode 140 is not formed among the entire one surface of the semiconductor substrate 110, May be selectively etched.

Here, the first region A1 may be a region where the first electrode 140 is not formed in the entire one surface of the semiconductor substrate 110, and the second region A2 may be a region where the first electrode 140 is formed Lt; / RTI >

Thus, for example, when the first electrode 140 is formed only as a finger electrode formed elongated in the first direction x, as shown in Figs. 1A and 1B, the first region A1 and the second region Each of the regions A2 is elongated in a first direction x and the first region A1 and the second region A2 are alternately arranged in a second direction y intersecting the first direction x, can do.

However, when the first electrode 140 includes not only the finger electrode but also the connection electrode, the second region A2 may be formed long in the second direction y as well as the first direction x. Hereinafter, a case where the first electrode 140 includes only the finger electrode will be described as an example.

Accordingly, at the selective etching step S2, at least a part of the dopant layer DPL located in the first region A1 of the first and second regions may be selectively etched, as shown in FIG.

For example, as shown in FIG. 6, the dopant layer DPL located in the first region of the entire front surface of the semiconductor substrate 110 is etched long in the first direction x, and the dopant layer DPL located in the second region A2 The dopant layer (DPL) may not be etched (for reference, FIG. 6 shows a simplified view of the plane of FIG. 5).

At this time, only the first region A1 can be selectively etched by the laser, and the dopant layer DPL located in the first region A1 can be etched as a whole.

The depth EDP at which the dopant layer DPL is etched in the selective etching step S2 is greater than 1/2 of the thickness TDP of the dopant layer DPL and the depth of the dopant layer DPL, May be less than the thickness (TDP).

For example, the thickness TDP 'of the remaining dopant layer DPL after the dopant layer DPL is etched in the first region A1 may be greater than 0 nm and less than 30 nm.

Thus, the texturing irregularities formed on one surface of the semiconductor substrate 110 can be prevented from being damaged.

Conventionally, when a selective emitter structure is formed using a laser, a low-concentration doping portion is first formed on the surface of the semiconductor substrate, and a portion of the surface region of the semiconductor substrate, The antireflection film was removed and the impurity was further diffused onto the surface of the semiconductor substrate exposed by removing the antireflection film to form a heavily doped portion.

However, in such a case, not only the antireflection film is removed while the laser is irradiated, but also the texturing unevenness of the semiconductor substrate is damaged by the laser, and the reflectivity of the semiconductor substrate is deteriorated and damaged.

However, according to the present invention, it is possible to selectively irradiate a part of the dopant layer with a laser, in a state in which a dopant layer is formed before the antireflection film is formed on the surface of the semiconductor substrate, 7, instead of completely removing the dopant layer in a certain region, etching the dopant layer with a laser so as to leave the dopant layer with a minimum thickness in a certain region, thereby deteriorating the texture unevenness of the semiconductor substrate It is possible to prevent deterioration of the reflectivity and light transmittance of the front surface which is the light receiving surface of the semiconductor substrate. In order to prevent out diffusion of impurities in the dopant layer DPL in the heat treatment step S3, Although not shown, on the dopant layer DPL remaining on the first region A1 and the second region A2 of the semiconductor substrate 110, An undoped silicate glass (USG) film without doping the impurity can be deposited. However, such USG film deposition is not necessarily required, and may be omitted in some cases.

Thereafter, in the heat treatment step S3, the semiconductor substrate 110 on which the dopant layer DPL is formed may be driven into the heat treatment chamber and heat-treated.

8, the semiconductor substrate 110 is subjected to heat treatment to diffuse impurities contained in the dopant layer DPL into the semiconductor substrate 110 to form a first conductive type or a second conductive type, A conductive type region containing two conductive type impurities can be formed.

Therefore, when the dopant layer DPL contains an impurity of the first conductivity type, the first conductivity type region 120 may be formed on one side of the semiconductor substrate 110 in the heat treatment step S3. Alternatively, if the dopant layer DPL contains an impurity of the second conductivity type, the second conductivity type region 170 may be formed on one side of the semiconductor substrate 110 in the heat treatment step S3.

In the heat treatment step S3, the first region A1 of the semiconductor substrate 110 is formed with a lightly doped portion 120L doped with impurities at a low concentration, and a second region A2 of the semiconductor substrate 110 is formed, The high concentration doping portion 120H may be formed in which the impurity is doped at a higher concentration than the low concentration doping portion 120L of the first region A1.

More specifically, the lightly doped region 120L is formed because the thickness TDP 'of the remaining dopant layer DPL is thin in the first region A1 of the semiconductor substrate 110, In the region A2, the thickness TDP of the remaining dopant layer DPL is thick, so that the heavily doped region 120H can be formed.

If the dopant layer DPL located on the first region A1 of the semiconductor substrate 110 in the selective etching step S2 is completely etched, the above-described USG film is not formed. In the heat treatment step S3, Impurities of the dopant layer DPL remaining in the second region A2 of the substrate 110 may diffuse into the first region A1 of the semiconductor substrate 110 through the space in the heat treatment chamber.

After the heat treatment step S3, the remaining dopant layer removing step S4 may be performed. Accordingly, as shown in FIG. 9, the remaining dopant layer DPL on one surface of the semiconductor substrate 110 can be completely removed.

The remaining dopant layer removing step S4 may be performed, for example, by forming an etch stopping film entirely on the opposite surface of the semiconductor substrate 110, and then immersing the semiconductor substrate 110 in a diluted HF solution .

After the remaining dopant layer DPL is removed, the etch stopping layer formed on the opposite side of the semiconductor substrate 110 can be removed.

10, a second conductive type region 170 and a rear passivation film 190 are formed on the opposite side of the semiconductor substrate 110, and an antireflection film 130 (not shown) is formed on the entire surface of the semiconductor substrate 110, The first electrode forming step S5 and the second electrode forming step S6 may be performed.

In the first electrode formation step S5, the first electrode 140 may be formed in the second region A2 except for the first region A1 among the entire one surface of the semiconductor substrate 110, In the electrode forming step S6, the second electrode 150 may be formed on the opposite side of the semiconductor substrate 110. [

Thus, a solar cell as shown in Fig. 10 can be manufactured.

As described above, in the method of manufacturing a solar cell according to the first embodiment of the present invention, a conductive type region including a high-concentration doping portion 120H and a low-concentration doping portion 120L is formed on one surface of a semiconductor substrate 110 having textured concave- The dopant layer DPL located in the first region A1 is selectively etched and the dopant layer DPL is etched to prevent the uneven texture of the semiconductor substrate 110 from being damaged, It is possible to maximize the short circuit current of the solar cell by minimizing the contact resistance between the first electrode 140 and the conductive type region while maximizing the light absorption rate of the solar cell.

The first embodiment of the solar cell manufacturing method has been described as an example in which the second conductivity type region 170 is directly formed on the rear surface of the semiconductor substrate 110. [

However, the method of manufacturing a solar cell according to the first embodiment of the present invention is not limited to such a structure.

FIGS. 11 and 12 are diagrams for explaining solar cells of other structures that can be manufactured by the solar cell manufacturing method according to the first embodiment of the present invention.

11, a method of manufacturing a solar cell according to the first embodiment of the present invention includes a step of forming a first conductive type semiconductor layer Even in the case of a solar cell in which the second conductivity type region 170 having the high concentration doping portion 170H and the low concentration doping portion 170L is located on the rear surface of the region 120 and the semiconductor substrate 110, The first conductive type region 120 and the second conductive type region 170 can be formed according to the method described in FIGS.

12, a method of manufacturing a solar cell according to a first embodiment of the present invention includes a step of forming a first semiconductor substrate 110 having a high concentration doping portion 120H and a low concentration doping portion 120L on a front surface of a semiconductor substrate 110, Even in the case of a solar cell in which the conductive type region 120 is located and the second conductive type region 170 is entirely located on the rear surface of the semiconductor substrate 110 according to the method described in Figures 3 to 10, Regions 120 may be formed.

In the method of fabricating a solar cell according to the first embodiment of the present invention, the dopant layer DPL located in the first region A1 where the first electrode 140 is not formed in the selective etching step S2 is entirely etched The dopant layer DPL located in the first region A1 is not etched as a whole but a plurality of the first regions A1 are formed in the first region A1 so as to be spaced apart from each other in the first direction x. It is also possible to selectively etch the regions.

In such a case, the patterns of the high-concentration doping portion 120H and the low-concentration doping portion 120L of the first conductivity type region 120 formed on one surface of the semiconductor substrate 110 may be deformed.

More specifically, this is as follows.

FIG. 13 is a view for explaining an example of a solar cell manufactured according to the second embodiment of the present invention, and FIG. 14 is an enlarged plan view of a portion K in FIG.

13 and Fig. 14, description of the same components as those described above in Figs. 1A and 1B will be omitted and the other portions will be mainly described.

As shown in FIG. 13, the solar cell structure manufactured according to the second embodiment of the present invention has a first region A1 in which the first electrode 140 is not located, as shown in FIGS. 1A and 1B, The low concentration doping portion 120L and the high concentration doping portion 120H may be positioned in each of the first regions A1.

More specifically, in the solar cell manufactured according to the second embodiment of the present invention, the first electrode 140 has the finger electrodes long in the first direction (x) in each of the second regions A2, 1 conductive type region 120 may be provided with a high concentration doping portion 120H and a low concentration doping portion 120L in the first region A1 and a high concentration doping portion 120H in the second region A2 .

Accordingly, the first electrode 140 located in the second region A2 may be connected to the heavily doped region 120H located in the second region A2.

The lightly doped region 120L and the heavily doped region 120H are alternately arranged in the first direction A1 in the first direction x as shown in FIG. In a second direction y intersecting the first direction y.

The first direction width W120L of the lightly doped portion 120L located in the first region A1 is larger than 1/4 of the distance D140 between the first electrodes 140, May be smaller than twice the interval (D140).

The first direction width W120H of the highly doped portion 120H located in the first region A1 is greater than 1/4 of the width of the first electrode 140 and the distance D140 between the first electrodes 140 ).

In addition, the first directional width W120L of the low-concentration doped region 120L located in the first region A1 is equal to the first directional width W120H of the highly doped region 120H located in the first region A1 It can be bigger.

In such a solar cell structure, the heavily doped portion 120H is formed to be elongated in the second direction (y) intersecting the first electrode 140 in the first region A1 where the first electrode 140 is not formed The carrier collected through the lightly doped portion 120L of the first conductivity type region 120 is moved to the first electrode 140 through the highly doped portion 120H having a relatively low resistance, The efficiency can be further improved.

Such a solar cell structure is entirely the same as the method for fabricating a solar cell according to the first embodiment of the present invention except that a pattern for etching the dopant layer DPL located in the first region A1 in the selective etching step S2 But can be implemented differently.

Hereinafter, a method of manufacturing a solar cell according to a second embodiment of the present invention will be described.

The solar cell manufacturing method according to the second embodiment of the present invention may be entirely the same as the solar cell manufacturing method described with reference to FIGS. 3 to 10, except for the selective etching method.

Therefore, in describing the solar cell manufacturing method according to the second embodiment of the present invention, the selective etching method in the solar cell manufacturing method according to the first embodiment of the present invention shown in FIG. 3 will be described.

15 is a view for explaining a selective etching method in a solar cell manufacturing method according to a second embodiment of the present invention.

15, in the selective etching method of the second embodiment of the present invention, the dopant layer DPL located in the second region A2 of the semiconductor substrate 110 is not etched, The dopant layer DPL located in the first region A1 of the semiconductor substrate 110 can be selectively etched.

At this time, the dopant layer DPL located in the first region A1 may be etched into a plurality of regions EP having a pattern spaced in the first direction x. For reference, in FIG. 15, NEP means a region where the dopant layer (DPL) is not etched.

The etch width W120L of each of the first direction of the dopant layer DPL etched into the plurality of regions EP in the selective etching step S2 is set to 1/10 of the distance D140 between the first electrodes 140, 4 and less than twice the distance D140 between the first electrodes 140. [

In addition, the etching interval W120H in each of the first directions of the dopant layer DPL etched into the plurality of regions EP in the selective etching step S2 is larger than 1/4 of the width of the first electrode 140, And the interval D140 between the first electrodes 140 may be smaller than the interval D140.

At this time, the etching width W120L of each of the first direction of the dopant layer DPL may be equal to or larger than the etching interval W120H of each of the first direction of the dopant layer DPL.

15, the etching width W120L of the first direction x of the dopant layer DPL is larger than the etching interval W120H of the first direction x of the dopant layer DPL For example.

 The lightly doped region 120L spaced in the first direction x is formed in the plurality of regions of the first region A1 where the dopant layer DPL is etched by the heat treatment step S3, A1 and a plurality of heavily doped regions 120H extending in the second direction y are formed in regions other than the plurality of regions, so that a solar cell as described with reference to FIGS. 13 and 14 can be manufactured.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (9)

A semiconductor substrate;
A first conductive type region doped with an impurity of a first conductivity type formed on one surface of the semiconductor substrate and having a lightly doped region doped with the impurity at a low concentration and a highly doped region doped at a higher concentration than the lightly doped region;
A first electrode connected to the heavily doped region in the first conductivity type region;
A second conductive type region formed of a polycrystalline silicon material doped with an impurity of a second conductivity type opposite to the first conductive type region on the opposite side of the semiconductor substrate;
And a second electrode connected to the second conductivity type region. The method according to claim 1,
Wherein the semiconductor substrate includes a first region in which the first electrode is not located and a second region in which the first electrode is located,
Wherein the lightly doped region and the highly doped region are located in the first region,
The heavily doped portion is located in the second region in the first direction,
Wherein the first electrode is connected to the heavily doped region located in the second region and is located in the second region in the first direction,
Wherein the heavily doped region and the heavily doped region located in the first region are alternately located in the first direction and the heavily doped region located in the first region is doped with the heavily doped And a second direction perpendicular to the first direction,
Wherein the first direction width of the lightly doped region located in the first region is larger than 1/4 of the distance between the first electrodes and smaller than twice the distance between the first electrodes. 3. The method of claim 2,
Wherein the first directional width of the highly doped portion located in the first region is larger than 1/4 of the first electrode width and smaller than the interval between the first electrodes. 3. The method of claim 2,
Wherein the first directional width of the lightly doped region located in the first region is equal to or larger than the first directional width of the highly doped region located in the first region. 3. The method of claim 2,
Wherein the semiconductor substrate is formed of a single crystal silicon material containing an impurity of a second conductivity type to form a heterojunction with the second conductivity type region,
Wherein the first conductive type region is formed by diffusing an impurity of the first conductive type on one surface of the semiconductor substrate,
Wherein a concentration of an impurity doped in the second conductivity type region is higher than a concentration of an impurity contained in the semiconductor substrate. 6. The method of claim 5,
And a control passivation film formed of a dielectric material is further formed between the second conductive type region and the semiconductor substrate. The method according to claim 6,
Wherein the thickness of the control passivation film is between 0.5 nm and 2.5 nm. 6. The method of claim 5,
Wherein one surface of the semiconductor substrate has a texturing structure and the opposite surface has a flat surface without the texturing structure,
Wherein one surface and the opposite surface of the semiconductor substrate all have a texturing structure. 6. The method of claim 5,
Wherein a back passivation film is further formed on the second conductive type region and the second electrode is in contact with the second conductive type region through the rear passivation film.

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