JPH05259489A - Manufacture of photoelectric conversion device - Google Patents

Abstract

PURPOSE:To improve mass productivity and yield by forming a reverse-conductive type semiconductor layer on a mono-conductive type semiconductor substrate, and forming, on the reverse-conductive type semiconductor layer, V-shape or trapezoid-shape grooves extending to the mono-conductive type semiconductor layer beyond the reverse- conductive type semiconductor layer with the use of etching treatment. CONSTITUTION:Silicon oxide is formed on the surface of a substrate 1 consisting of semiconductors, and boron glass is formed all over the reverse side of the substrate. Then, a P<+>-type layer 11 is formed all over the reverse side of the substrate due to oxidization and diffusion in wet oxygen at high temperatures. Next. phosphorus glass or arsenic glass 23 is formed after silicon oxide on the surface of the substrate 1 is eliminated, and then a reverse-conductive type semiconductor 7 is formed by oxidizing and diffusing at high temperatures. Successively, the residual regions 21-23 are provided by eliminating selectively glass coating film, and V-shape or trapezoid-shape grooves are formed so that the projected portion of an N<+>-type region can be extended continuously to the portion of the N<+>-type region below an electrode under the coating film 22 by anisotropic etching. After that, a photoelectric conversion device is made by providing a silicon nitride coating film 3, an opposing electrode 21, a supplementary electrode 5, and a wiring lead 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a photoelectric conversion device.

The present invention relates to a structure on a light irradiation surface side of a photoelectric conversion device, in which an electrode region on the upper surface of a semiconductor has a flat surface, and a region other than the electrode region, that is, a photoelectric conversion region is V-shaped or It has a trapezoidal groove. Furthermore, on the upper part of this groove, N ⁺ or P ^{+ of a} conductivity type different from that of the semiconductor substrate is used.
A layer is provided, and the inside of the groove exposes the semiconductor substrate itself so that irradiation light can efficiently reach the inside of the semiconductor.

When an insulating or semi-insulating film having a thickness of 5 to 100 Å made of silicon nitride or silicon carbide having a thickness capable of passing an electric current is provided, a semiconductor layer having a conductivity type opposite to that of the substrate semiconductor is electrically apparent. It is characterized in that it is provided so as to float from the upper counter electrode so as to form a floating channel, and that the electrode on the film is provided with an electrode having a polarity for generating a depletion layer in the semiconductor layer.

Further, according to the present invention, the semiconductor surface of the counter electrode portion has a flat surface, and the light irradiation surface other than this electrode portion reduces the reflection efficiency of the irradiated light, so that its cross-sectional shape is V.
It is characterized in that a groove of a mold (including a reverse V-shaped groove in the present invention is referred to as a V-shaped groove) or a trapezoidal groove (inverse trapezoidal or a mixed groove of V-shaped and trapezoidal is collectively referred to as a trapezoidal in the present invention) is provided. I am trying.

According to the present invention, such a V-shaped or trapezoidal groove is selectively formed on the front surface of a semiconductor, and when forming an electrode on the back surface, the groove or an extremely thin insulating or semi-insulating film on the groove is damaged and the pinhole layer is formed. Exists so that the counter electrode and the reverse conductivity type directly below it are not electrically shorted, and the reverse conductivity type layer having a thickness of 5000 Å or less, preferably 20 to 200 Å and the substrate semiconductor. Guaranteeing that the metal of the counter electrode does not diffuse to the junction and deteriorates the junction, and the counter electrode forms a depletion layer in the semiconductor below this reverse conductivity type layer to improve the open circuit voltage. Is characterized by.

[0006]

2. Description of the Related Art Conventionally, a CNR (COMSAT NON-REFRE) has been used as a photoelectric conversion element in which V-shaped grooves exist infinitely and uniformly on a light irradiation surface.
CTIDE SOLAR CELL) is known. This is because a V-shaped groove is anisotropically etched on the surface of a silicon semiconductor, and an extremely shallow PN junction of 0.2 to 0.3 μm is formed on the entire surface of this groove, which is infinitely present, to oppose this bonding layer. The electrodes are brought into ohmic contact with each other to take out the photoelectromotive force generated at this joint surface. This CNR is experimentally high at 15% or higher for AM0 and 18% for AM1. However, because of this extremely shallow junction,
The joint is easily broken and an electrical short or leak occurs at the PN joint, so that practical reliability is not obtained.

Further, conventionally, in order to obtain a delicately controlled high open-circuit voltage in a semiconductor substrate, a PN junction type device has been manufactured by diffusing a P or N layer at a high temperature with a high concentration.

[0008]

In such a device, there are many cost factors such as the diffusion process and the provision of the subtle ohmic contact electrodes, and the manufacturing yield thereof is not high.

Further, in the MIS type device, a very thin silicon oxide film is formed on the light irradiation surface, and a high open circuit voltage can be obtained by the counter electrode on the upper surface. However, in the light irradiation part other than the electrode part, when this insulating film is formed into a chip for forming the electrode on the back surface or for taking out the conversion element from the substrate, it deteriorates due to mechanical damage and induces defects due to pinholes or scratches. However, this causes a decrease in current, and in particular, it has been impossible to stably form an inversion layer (inversion layer) at the light irradiation portion.

The present invention has both the characteristics of operating an insulating layer as a MIS type device as a barrier for preventing deterioration of a junction portion and the characteristics of a PN junction type device by a shallow diffusion method. In addition, the present invention provides a method for manufacturing a photoelectric conversion device having an extremely ideal structure in which the respective drawbacks are offset.

[0011]

[Means for Solving the Problems] That is, a semiconductor layer of opposite conductivity type is formed on the upper surface of a light-conductivity type semiconductor for light irradiation.
It has a thickness of less than μm, especially 20 to 2000Å,
It is provided to invert the semiconductor surface to the conductivity type.

Further, an insulating or semi-insulating film having a thickness capable of passing a current is provided on the upper surface thereof, and a counter electrode for determining an open circuit voltage is provided on the upper surface thereof. Therefore, the open circuit voltage is determined by the work function difference between the semiconductor and the electrode. Furthermore, since the semiconductor layer of the opposite conductivity type is not in contact with the external electrode with respect to the substrate semiconductor below, the floating voltage is generated. It has a structure. In addition, in the light irradiation part between the electrode parts, the semiconductor layer of the opposite conductivity type is made thin to prevent a decrease in conversion efficiency due to light absorption here. Further, since this semiconductor layer was floating, a horizontal electric field was generated in the direction of the counter electrode, and one charge generated by light irradiation had a so-called channel structure that promotes lateral drift through this semiconductor layer. Have

In this sense, the structure of the present invention may be called a photoelectric conversion device having a floating channel structure. Also, regarding the joint between the semiconductor layer and the semiconductor surface, which is also formed under this electrode, in the case of a so-called conventional PN junction type, an alloy (alloy) is used between electrode semiconductors for ohmic contact between the electrodes.
For this reason, a junction depth of 0.5 to 1 μm is required.
Therefore, as in the present invention, the depth is 0.5 μm or less, especially 20 μm.
It was not possible to make a reverse conductivity type semiconductor layer of ~ 500 Å. However, the present invention does not form such an ohmic contact electrode, but provides a counter electrode on an insulating or semi-insulating film, and a material having a polarity to further expand the depletion layer at the junction part of the PN junction below this film. Is used to form the counter electrode.

In addition to the above, in the present invention, a V-shaped groove is provided on the light irradiation surface to prevent reflection of irradiation light at that portion, and in addition, this V-shaped groove is conventionally known. It is applied to a MIS type photoelectric conversion device instead of the PN junction type. In addition, it is intended to improve the manufacturing yield of the MIS type element by having unevenness on the surface other than the counter electrode portion, and an embodiment of the present invention will be described below with reference to the drawings.

[0015]

[Embodiment 1] FIG. 1 is a vertical sectional view for producing a photoelectric conversion device for carrying out the present invention.

In FIG. 1A, a semiconductor substrate (10
Crystal orientation in or near the (0) plane (± 15 with respect to the (100) plane
A silicon semiconductor having a temperature of less than 90 ° was used. The specific resistance was 2 to 50 Ωcm of P type. Silicon oxide is formed on the front surface (upper side of the drawing) of this semiconductor (1) by the dipping method, and boron glass is formed on the entire back surface (lower side of the drawing) by the dipping method. Then, the P ⁺ layer (11) was formed on the entire back surface to a depth of 2 to 5 μm. Furthermore, silicon oxide on the surface of the semiconductor (1) was chemically removed.

Thereafter, phosphorus glass or arsenic glass (23) is formed on the surface of the semiconductor (1) by the same dip method, and 700
By oxidation and diffusion at a temperature of up to 1000 ° C., a semiconductor layer (7) having a conductivity type opposite to that of the substrate was formed to a thickness of 0.5 μm or less, for example, 20 to 2000 Å, especially 200 Å.

The P ⁺ layer (11) on the back surface is not particularly required to be formed if the substrate makes a sufficient ohmic contact. Further, the phosphorous glass or arsenic glass coating film was selectively removed at least on the upper surface thereof to leave the remaining regions as (21) (22) (23). Figure 1 (A)
In, the coating film (21) is a region forming a counter electrode, and the coating film (22) is a region corresponding to a convex portion for forming a V-shaped groove or a trapezoid. This coating (22) is continuous with the coating (21),
After forming the V-shaped groove, the N ⁺ region of this convex portion was made continuous to the N ⁺ region under the electrode. The width of the coating (21) is 10 to 20
It is connected to the external lead-out terminal coating (23) by μm.

The area (17) is 2 to 10 μm square, typically 5
It is a hole of square μm. Around the area (17), a mesh-like coating (22) is formed with a width of 2 to 10 μm, typically 5 μm. The direction of this mesh was parallel to the (110) plane of the crystal orientation, and was aligned so that a rectangular V-shaped or trapezoidal groove was formed by anisotropic etching.

After that, the substrate having the structure shown in FIG.
(Water 8cc-Ethylenediamine 17cc-Pyrocacoque 3g
Etching was carried out at a temperature of 70 to 85 ° C. in a mixed solution). Air was kept out of contact with the WAP solution by bubbling with nitrogen. As a result, the (100) plane is 3300Å /
We obtained an etch rate of min and 200Å / min for the (111) plane.
Silicon oxides (21), (22) and (23) were etched for 20 hours or less after being carried out for 30 hours and had a sufficient masking action.

When the above WAP etching is performed for 5 minutes to 1 hour, typically 10 to 30 minutes, the mesh pattern shown in FIG. 1 (A) is patterned in parallel with the (110) plane. Then, the region (17) was etched into a square in a reverse pyramid shape to form a V-shaped groove. When the etching time is 5 to 10 minutes, the reverse trapezoidal groove is formed in the portion (7), and the upward trapezoidal or the upward V-shaped convex portion is formed by adjusting the widths of the regions (17) and (22). It was formed corresponding to the region (12).

That is, since the region (17) has a square of 2 to 10 μm, typically a square of 5 μm, the depth of the V-shaped groove is 3 μm.
Becomes The N ⁺ semiconductor layer is typically 0.5 μm or less
Since it has 20 to 2000 μm, the upper part of this V-shaped groove is N
^It can be seen that the ⁺ type conductivity remains and most of the type is a P type semiconductor. And N ⁺ semiconductor layers (7) (24) (24 ')
Are held by the silicon oxide masks (21), (22) and (23), so that they can be connected to each other to form a passage through which carriers flow to the electrode part (24).

Further, the upper regions (24) and (24 ') of the electrode portion formed after the comb-shaped electrode have the plane as originally described because it is masked by the silicon oxide mask.

After that, these semiconductor substrates were immersed in hydrofluoric acid to remove the silicon oxide on the substrates, and then sufficiently cleaned to obtain FIG. 1 (B). That is, the N ⁺ region easily absorbs light, and the P-type semiconductor makes electrons and holes rather than light.
Of these electrons, they reach the N ⁺ regions (7) and (24 '), and the resistance of this N ⁺ region is small, so that they can be efficiently guided to the electrode portion (24). That is, the N ⁺ layer is not formed on the entire light-irradiated surface, but N is formed only on the portion where carriers pass and collect.
^{The +} layer is made and the depletion layer is enlarged. And the light is N
The absorption in the ⁺ layer is avoided and the V groove effectively reaches the inside of the semiconductor to effectively generate electrons and holes.

In the present invention, thereafter, a silicon nitride film was formed in a film thickness of 5 to 50Å, particularly 10 to 30Å, in close contact with the surface of the substrate by the plasma nitriding method. That is, a mixed gas of ammonia or nitrogen and hydrogen was diluted to 1 to 20% of helium by inductive energy of 0.5 to 50 MHz and nitrided under a pressure of 0.1 to 10 torr. Nitriding temperature is 150 to 700 ℃, especially 400 to 680 ℃
A silicon nitride film (3) was formed by nitriding at.
Insert the substrate into the ammonia atmosphere without using plasma,
The silicon nitride film may be formed by simply applying heat. Thus, the silicon nitride film (3) has a thickness of 5-100Å, especially 15-
Formed to a thickness of 25Å.

Aluminum is formed as the back electrode (2) by vacuum evaporation after removing the nitride film, and a sinter for ohmic contact with the semiconductor substrate is formed in the temperature range of 300 to 600 ° C. Performed in active gas.

In the step shown in FIG. 1, thereafter, a counter electrode (21) and an auxiliary electrode (5), which are magnetism (M
g) was vacuum evaporated. This is not Mg, but Al, Be, etc. 4.0e
It was preferable that the metal had a work function of V or less and was small. In Mg and Be, it is easy to oxidize and the formation is 150 ℃, 10
Since it is left to stand in the atmosphere for 00 hours and its reliability deteriorates, Mg, Be or a mixture of them with a semiconductor or other metal is added to the upper side of 50 to 5000 Å, especially 500 to 2000 Å. The counter electrodes (21) and (5) were formed to have a thickness of ˜3 μm, and for the semiconductor, Ni, Cr, and Cu were formed into a multilayer film having a thickness of 100 to 1000 Å.

Contrary to the above description, when the substrate semiconductor (1) is N-type, the semiconductor layer (7) for forming a depletion layer and a carrier passage above the V-shaped groove is P ⁺ -type, It is shown in Table 1 that this counter electrode uses high work function materials such as Pt, Au, and Ni. And these materials are 100 Å ~
1 μm was formed. However, for Au, Pt, etc., a solar cell was formed to a thickness of 50 to 200 Å in order to make it at a low cost, and Al was formed thereon in the range of 1 to 3 µm and Ni and Cu were formed in the range of 0.1 to 0.5 µm.

The thickness that allows the passage of electric current (5 to 100 Å, especially 15 to 30
The silicon nitride film (Si ₃ N ₄ or Si ₃ N _4-X 0 <X <4) having a thickness of Å may be formed by a glow discharge CVD method instead of plasma nitriding. In that case, two back surface electrodes were aligned with each other. No film was formed on the electrode. Also, this film is a film formed in another reducing atmosphere, such as SiC _1-X (0 <X <
It may be 1).

Thus, the insulating or semi-insulating film (3)
The V-shaped or trapezoidal groove of the other part except for the comb-shaped electrode (5) and the pad (21) for external extraction whose surface of the semiconductor is a flat surface is formed by a photo-etching method on the coating on which the counter electrode is vacuum-deposited. It was formed by removing the electrode material in the region (17) in which was formed. As is clear from the drawings, the main structure of the present invention is that the counter electrode is not provided on the region having the V-shaped or trapezoidal groove, and the counter electrode and the external extraction electrode (21) are provided only on the flat surface on the semiconductor. , Drawer lead (32)
Is provided.

Thus, in the photo-etching for forming the counter electrode, the periphery of the counter electrode (5) side is a flat surface, so that the pattern is sharp and no metal remains. In addition, since the underside of the electrode is a flat surface, the silicon nitride film (3)
There are few pinholes. Leaks are less likely to occur due to mechanical stress from the outside. Furthermore, since there is no semiconductor layer of N ⁺ or P ⁺ in the region of the V-shaped or trapezoidal groove where light irradiation is performed, there is no light absorption loss there, and the V-shaped groove allows efficient introduction of light into the inside. The incident light can effectively generate electrons and holes. Further, since there is no conductor in the groove portion, there is a feature that even if pinholes and leaks occur, there is no problem in physical properties.

In FIG. 1 (D), an antireflection film (10) of silicon nitride, tantalum oxide, SiO 2 or the like is formed on the upper surface to a thickness of 600 to 900 Å, and the reflectance of irradiation light (20) is shown by reaction. It is reduced to 0.5-2.0% to achieve extremely ideal irradiation, and the counter electrode is used as a protective film that does not cause disconnection shorts due to mechanical damage, and the counter electrode (5) and silicon nitride film (3). Oxygen at the interface,
The purpose is to prevent the deterioration of reliability caused by the inclusion of moisture and corrosion. For this reason, the antireflection film was also formed on the peripheral portion (25) by the plasma CVD method so that the antireflection film was completely coated.

In this example, 1 under the condition of AM1
The conversion efficiency was 8.5 to 20.5% and the FF was 0.82 to 0.90. Since the light irradiation (20) was applied twice in the V-shaped groove, the reflectance could be 12% or less without forming the antireflection film. Although the counter electrode in the present invention has a comb shape, it may have a mesh shape or a fish bone shape, which is characterized by selectively separating the light irradiation surface having a groove and the presence of the counter electrode. There is.

[Embodiment 2] FIG. 2 shows another embodiment of the present invention. As in FIG. 1, a semiconductor layer (7) of N ⁺ or P ⁺ is provided on the upper part of the V-shaped groove, so that a depletion layer is efficiently formed on the upper part of the semiconductor (1) and the electric field of this depletion layer is The carriers collected by are efficiently moved to the electrode part (5) in the N ⁺ or P ⁺ layer. Further, the light is irradiated twice in the V-shaped groove, and since there is no N ⁺ or P ⁺ layer there, the light can efficiently reach the inside of the semiconductor (1).

In order to provide such a V-shaped groove only on the light-irradiated surface and to facilitate reversal by the semiconductor layer below this V-shaped groove, in this region, that is, near the upper surface of the substrate semiconductor (1), the reverse conductivity type of 0.5 μm or less is particularly preferable. A layer (7) with a thickness of 20 to 500 Å is provided. In addition, an insulating or semi-insulating film (3) and a counter electrode (5) are provided on the upper side.

In the structure of FIG. 2, an opposite conductivity type semiconductor layer (7) is provided only on the upper portion of the V-shaped groove, and the semiconductor layers are continuously extended on the upper portion thereof to below the counter electrode (5). It is effective to use a pattern. Then, one of electrons and holes formed by light irradiation in the semiconductor below the V-shaped groove is attracted to the opposite conductivity type semiconductor layer (7), and counteracts through the floating channel above this. It can be drifted below the electrodes with little loss. In addition, when the light irradiation is performed on the semiconductor below the V-shaped groove, all the irradiation light is characterized by no loss due to absorption of impurity scattered light by the reverse conductivity type layer.
Due to such a feature, in the present invention, the photoelectric conversion efficiency could be obtained under the condition of AM1 exceeding 20% which was the theoretical limit of silicon and up to 20.5%. In the drawing, SiO or tantalum oxide is formed as an antireflection film to a thickness of 700 to 900 Å. In addition, in such a structure, it is possible to detect the wavelength of near infrared, and it is possible to make the photoresponse characteristic to the extent that 950 nm semiconductor laser light can be used practically.

[0037]

As a result of the above, the conversion efficiency under AM1 is 18%.
I was able to improve to. In addition, the characteristic under a fluorescent lamp (300 Lx), which is a representative of short-wavelength light, was 50 μmW / cm ² . The floating channel MIS type photoelectric conversion device of the present invention is excellent not only in the magnitude of the effect of the floating channel, but also in its shape, that is, the electrode portion is flat and the other portions have a concavo-convex shape, which is excellent in mass productivity. For the first time in the MIS type, the mass production yield could be increased to 90% or more.
Regarding the reliability, no abnormalities were found under the 150 ° C 1000-hour storage test.

Although the present invention is based on a single crystal of silicon, it may be a semiconductor having a polycrystalline, semi-amorphous or amorphous structure or a semiconductor such as silicon produced by the rapid quenching method or the dentrite method. In addition to silicon, germanium or other compound semiconductor may be used. Further, the V-shaped or trapezoidal groove plane pattern is not limited to the shape (square) of this embodiment, and may be rectangular or octagonal.

[Brief description of drawings]

1 shows a vertical cross-section of an embodiment for producing the invention.

FIG. 2 shows a vertical sectional view of another photoelectric conversion device of the present invention.

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[Procedure amendment]

[Submission date] August 27, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

Claims (2)

[Claims] 1. A step of forming a semiconductor layer of an opposite conductivity type on a semiconductor substrate of a conductivity type, a mask is selectively formed on the semiconductor layer, and an upper portion of the semiconductor substrate in a region without the mask is removed by etching. By doing so, a V-shaped or trapezoidal groove is formed, and the groove is formed beyond the semiconductor layer of the opposite conductivity type to reach the semiconductor layer of the conductivity type. 2. A semiconductor layer of opposite conductivity type according to claim 1,
A method for manufacturing a photoelectric conversion device, characterized in that the layers are formed to a depth of 000 Å or less, and these layers are continuously formed up to the external extraction electrode.