JPH0562473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure on the light irradiation surface side of a photoelectric conversion device, and includes a semiconductor substrate and a semiconductor layer having a conductivity type different from that of the substrate provided thereon to form a stacked semiconductor. The electrode region on the upper surface of the laminated semiconductor has a flat surface, and the region other than the electrode region, that is, the photoelectric conversion region has a V-shaped or inverted trapezoidal groove.

In other words, the semiconductor surface portion, which is the edge of the groove, is made of an N ⁺ or P ⁺ layer of a conductivity type different from that of the semiconductor substrate, while the inside of the groove exposes the semiconductor substrate itself, allowing irradiation light to efficiently reach the inside of the semiconductor. It's tight.

In addition, when an insulating or semi-insulating film of 5 to 100 Å thick is formed of silicon nitride or silicon carbide to allow current to flow, a semiconductor layer of a conductivity type opposite to that of the substrate semiconductor is electrically apparently separated from the counter electrode. It is characterized in that it is provided so as to float and form a floating channel, and that the electrode on the film has a polarity that generates a depletion layer in the semiconductor layer.

Furthermore, in the present invention, the semiconductor surface in the counter electrode part has a flat surface, and the light irradiation surface other than this electrode part is provided with a groove whose cross section is V-shaped or inverted trapezoid in order to reduce the reflection efficiency of the irradiated light. It is characterized by

The present invention selectively forms such a V-shaped or inverted trapezoidal groove on the semiconductor surface, and when forming an electrode on the back surface, the groove or the extremely thin insulating or semi-insulating film on the groove is damaged, resulting in the existence of a pinhole layer. In addition to preventing electrical short-circuiting between the counter electrode and the opposite conductivity type layer immediately below it, the counter electrode also extends to the junction between the opposite conductivity type layer with a thickness of 5000 Å or less, preferably 20 to 200 Å, and the substrate semiconductor. This feature ensures that the metal does not diffuse and deteriorate the junction, and that the opposing electrode creates a depletion layer in the semiconductor below the opposite conductivity type layer, improving the open circuit voltage.

Conventionally, CNR (COMSAT
NON-REFRECTIDE SOLAR CELL) is known. This is done by anisotropically etching a V-shaped groove on the surface of a silicon semiconductor, and then forming an extremely shallow PN junction of 0.2 to 0.3 μm on the entire surface of the surface, where many grooves exist infinitely, to counteract this bonding layer. The idea was to bring the electrodes into ohmic contact and extract the photovoltaic force generated at this joint surface. This CNR has experimentally achieved a high conversion efficiency of over 15% for AM0 and 18% for AM1. However, because the bond is extremely shallow, it can easily break.
Electric short or leak occurs at the PN junction, and practical reliability is not achieved.

Furthermore, conventionally, PN junction type devices are manufactured by diffusing a P or N layer at high concentration at high temperature in order to obtain a finely controlled high open circuit voltage in a semiconductor substrate. In such a device, there are many cost factors such as the diffusion process and the attachment of delicate ohmic contact electrodes, and the manufacturing yield is not high.

In addition, the MIS type device has an extremely thin silicon oxide film formed on the light irradiation surface, and can obtain a high open-circuit voltage by using a counter electrode on the top surface. However, in light irradiation areas other than the electrode area, this insulating film deteriorates due to mechanical damage or causes defects due to pinholes or scratches when forming electrodes on the back side or chipping to extract the conversion element from the substrate. However, this caused a decrease in current, and it was impossible to stably form an inversion layer, especially in the light irradiated area.

The present invention is characterized by the fact that the insulating layer of the MIS type device acts as a barrier to prevent deterioration of the junction, and by the shallow diffusion method.
It has an extremely ideal structure, having both the features of the PN junction type device and canceling out the drawbacks of each.

That is, on the top surface of a semiconductor of one conductivity type for light irradiation,
and a semiconductor layer of the opposite conductivity type to a thickness of 0.5 μm or less,
In particular, it has a thickness of 20 to 2000 Å, and is provided to invert the conductivity type of the semiconductor surface.

Furthermore, an insulating or semi-insulating film having a thickness that allows current to flow is provided on the upper surface thereof, and a counter electrode for determining the open circuit voltage is provided on the upper surface. Therefore, the open circuit voltage is determined by the difference in work function between the semiconductor and the electrode.Furthermore, since the semiconductor layer of the opposite conductivity type to the underlying substrate semiconductor is not in contact with the external electrode, the floating structure have.
In addition, in the light irradiation part between the electrode parts, the semiconductor layer of the opposite conductivity type is made thin to prevent a reduction in conversion efficiency due to absorption of light here. In addition, since this semiconductor layer was floating, a lateral electric field was generated in the direction of the counter electrode, and one charge generated by light irradiation had a so-called channel structure that promoted drift in the lateral direction through this semiconductor layer. are doing.

In this sense, the structure of the present invention may be referred to as a photoelectric conversion device having a floating channel structure.

In addition, regarding the junction between the semiconductor layer and the semiconductor surface, which is also made under this electrode, in the case of the so-called conventional PN junction type, an alloy is made between the electrode semiconductor for ohmic contact between the electrodes. Therefore, a bonding depth of 0.5 to 1 μm is required. Therefore, as in the present invention, the depth is 0.5 μm or less, especially 20 μm or less.
It was impossible to create a reverse conductivity type semiconductor layer with a thickness of 500 Å. However, in the present invention, such an ohmic contact electrode is not made, but a counter electrode is provided on an insulating or semi-insulating film, and a material with a polarity that should further expand the depletion layer is used at the junction of the PN junction under this film. This constitutes a counter electrode.

In addition to the above, the present invention provides a V-shaped or inverted trapezoidal groove on the light irradiation surface to prevent reflection of the irradiated light at that part. It was applied to an MIS type photoelectric conversion device, rather than the PN junction type that was previously used. In addition, by having irregularities on the surface other than the counter electrode part,
The present invention is intended to improve the manufacturing backlog of MIS type elements, and embodiments of the present invention will be described below with reference to the drawings.

Example 1 FIG. 1 shows a longitudinal cross-sectional view for producing a photoelectric conversion device for carrying out the present invention.

In FIG. 1A, the semiconductor substrate has a crystal orientation of 100 plane or its vicinity (± with respect to 100 plane).
(within 15°) was used. The specific resistance was P type with a resistivity of 2 to 50 Ωcm. Silicon oxide was formed on the surface (upper side of the drawing) of this semiconductor 1 by the dip method, and boron glass was formed entirely on the back surface (lower side of the drawing) by the dip method.
Oxidation diffusion occurs at a temperature of 1000-1200℃, and the P ⁺ layer 11
was formed on the entire back surface to a depth of 2 to 5 μm. Furthermore, silicon oxide on the surface of the semiconductor 1 was chemically removed.

After that, phosphorus glass or arsenic glass 23 is formed on the surface of the semiconductor 1 by the same dip method.
The semiconductor layer 7 is oxidized and diffused at a temperature of 700 to 1000°C to form a semiconductor layer 7 of a conductivity type opposite to that of the substrate to a thickness of 0.5 μm or less, e.g.
It was formed to a thickness of 2000 Å, especially 200 Å.

The P ⁺ layer 11 on the back side is not particularly necessary if the substrate makes sufficient ohmic contact.

Furthermore, the phosphorus glass or arsenic glass coating was selectively removed at least on its upper surface to leave remaining areas 21, 22, and 23. In FIG. 1A, the coating 21
is a region forming a counter electrode, and the coating 22 is V
This is a region corresponding to a convex portion for forming a mold groove or an inverted trapezoidal groove. This coating 22 is continuous with the coating 21, and after forming the V-shaped groove, the N ⁺ region of this convex portion is continuous to the N ⁺ region under the electrode.
The width of the coating 21 is 10 to 20 μm, and the coating 21 is connected to the coating 23 for external lead-out terminals.

Area 17 is a hole 2-10 μm square, typically 5 μm square. Around this region 17, a mesh-like coating 22 is formed with a width of 2 to 10 μm, typically 5 μm. The direction of this mesh is the 11th crystal orientation.
The grooves were parallel to the 0 plane and aligned so that a rectangular V-shaped or inverted trapezoidal groove was formed by anisotropic etching.

After this, the substrate having the structure shown in FIG.
Heat etching was carried out at a temperature of 70 to 85° C. Air was prevented from coming into contact with the WAP solution by bubbling with nitrogen. As a result, an etch rate of 3300 Å/min was obtained for the 100th plane, and 200 Å/min for the 111th plane. silicon oxide 21,2
Nos. 2 and 23 were etched for 30 hours and had an etching depth of 20 Å or less, and had a sufficient masking effect.

Etching using WAP as described above for 5 minutes to 1 hour.
Typically, if this is done for 10 to 30 minutes, when the mesh pattern shown in Figure 1A is patterned parallel to the 110th plane, area 17 will be etched squarely in the shape of an inverted pyramid, creating a V-shaped groove. was completed. If this etching takes 5 to 10 minutes, an inverted trapezoidal (inverted trapezoid) groove will be formed in the part 7, and by adjusting the width of regions 17 and 22, an upward trapezoid or an upward V-shaped convex (inverted V-shaped) groove will be formed. ) was formed corresponding to region 12.

That is, area 17 is 2 to 10 μm square, typically 5 μm.
Since it has a square shape, the depth of the V-shaped groove is 3 μm. In addition, since the N ⁺ semiconductor layer has a thickness of 0.5 μm or less, typically 20 to 2000 μm, the upper part of this V-shaped groove still has the N ⁺ conductivity type, and most of it is a P-type semiconductor. It can be seen that it is. The N ⁺ semiconductor layers 7, 24, 24' are covered with a silicon oxide mask 21,
Since they are held by 22 and 23, they are connected to each other and can be used as a passage through which carriers flow through the electrode section 24.

Further, the upper regions 24, 24' of the electrode portions formed after the comb-shaped electrodes had the same flat surfaces as they had initially because they were masked by a silicon oxide mask.

Thereafter, these semiconductor substrates were immersed in hydrofluoric acid to remove silicon oxide on the substrates, and then sufficiently cleaned to obtain FIG. 1B.

That is, the N ⁺ region easily absorbs light, and the P-type semiconductor creates electrons and holes more than light. The electrons among these are allowed to reach the N ⁺ region 7, 24′, and this N ⁺
Since the resistance of the region is low, it can be efficiently guided to the electrode section 24. That is, instead of forming an N ⁺ layer on the entire surface irradiated with light, the N ⁺ layer is formed only on the portion where carriers pass through and collect, thereby enlarging the depletion layer.

The light avoids absorption in the N ⁺ layer and effectively reaches the interior of the semiconductor through the V-groove or inverted trapezoidal groove, effectively generating electrons and holes.

In the present invention, a silicon nitride film was then formed closely on the surface of the substrate to a thickness of 5 to 50 Å, particularly 10 to 30 Å, by plasma nitriding. That is, ammonia or a mixture of nitrogen and hydrogen is diluted to 1 to 20% helium using induction energy of 0.5 to 50 MHz.
Nitriding was carried out at a pressure of ~10 torr. The nitriding temperature is
A silicon nitride film 3 was formed by nitriding at 150 to 700°C, particularly 400 to 680°C. The silicon nitride film may be formed by inserting the substrate into an ammonia atmosphere and simply applying heat without using plasma. Thus, the silicon nitride coating 3 has a thickness of 5 to 100 Å, in particular 15 Å.
formed to a thickness of ~25 Å.

After removing this nitride film, aluminum was formed as the back electrode 2 by vacuum evaporation, and sintering for ohmic contact with the semiconductor substrate was performed in an inert gas at a temperature range of 300 to 600°C.

In the process shown in FIG. 1, magnesium (Mg) was then vacuum-deposited on the surface as a counter electrode 21 and an auxiliary electrode 5. This is not Mg,
It is preferable to use a metal such as Al or Be with a small work function of 4.0 eV or less. Mg and Be are easily oxidized and are left in the atmosphere at 150°C for 1000 hours, reducing reliability.
Mg, Be, or a mixture of them and a semiconductor or other metal is formed on the upper side of 50 to 5000 Å, especially 500 to 2000 Å, and aluminum is formed to a thickness of 0.5 to 3 μm, and Ni, Cr, and Cu are further formed for semiconductors to a thickness of 100 to 1000 Å. Counter electrodes 21 and 5 were formed in the form of a multilayer film having a thickness of .

Contrary to the above description, when the substrate semiconductor 1 is of N type, the semiconductor layer 7 for forming a depletion layer and a carrier path above the V-type or inverted trapezoidal groove is
It is P ⁺ type, and this counter electrode uses a material with a high work function such as Pt, Au, or Ni.

These materials were formed to a thickness of 100 Å to 1 μm.
However, in order to make solar cells at low cost, Au, Pt, etc. are formed to a thickness of 50 to 200 Å, and on top of that, Al is formed to a thickness of 1 to 3 μm, and Ni and Cu are formed to a thickness of 0.1 to 0.5 μm.

Thickness that allows electric current to pass (5 to 100 Å, especially 15 to 30 Å
silicon nitride film (Si ₃ N ₄ or Si ₃ N _4-x 0
<X<4) is not plasma nitriding but glow discharge
It may be formed by CVD method. In that case, two back electrodes were placed together. Film formation was prevented from occurring on the electrode. This film can also be applied to other films formed in a reducing atmosphere, such as SiC _1-x (0<X<1).
It may be.

The film that will become the counter electrode thus vacuum-deposited on the insulating or semi-insulating film 3 is then photo-etched to remove the comb-shaped electrode 5, which has a flat semiconductor surface, and the external lead-out pad 21, and other parts. The electrode material in the region 17 where the V-shaped or inverted trapezoidal groove was formed was removed.

As is clear from the drawings, the main structure of the present invention is that no counter electrode is provided on the region having a V-shaped or inverted trapezoidal groove, and the counter electrode and the external extraction electrode 21 are provided only on the flat surface of the semiconductor. , a lead-out lead 32 is provided.

As a result, when photo-etching is performed to form the counter electrode, since the periphery of the counter electrode 5 and the like is a flat surface, the pattern is sharp and there is no remaining metal. Furthermore, since the surface under the electrode is flat, there are fewer pinholes in the silicon nitride film 3. Leakage is less likely to occur due to external mechanical stress. Furthermore, since there is no N ⁺ or P ⁺ semiconductor layer in the V-shaped or inverted trapezoidal groove region where light irradiation is performed,
There is no light absorption loss there, and the V-shaped or inverted trapezoidal grooves allow light to be efficiently introduced into the interior, and electrons and holes can be effectively generated by incident light.

Furthermore, since there is no conductor in this groove, even if a pinhole or leak occurs, it will not cause any problem in terms of physical properties.

In FIG. 1D, an antireflection film 10 made of silicon nitride, tantalum oxide, SiO, etc. is formed on this upper surface to a thickness of 600 to 900 Å, and the reflectance of the irradiated light 20 is reduced to 0.5 to 2.0 by reaction.
%, to achieve extremely ideal irradiation, and to provide a protective film that prevents the counter electrode from breaking due to mechanical damage, etc., and to prevent oxygen and moisture from entering the interface between the counter electrode 5 and the silicon nitride film 3. The purpose is to prevent a decrease in reliability due to corrosion, etc. Therefore, the plasma is applied so that the anti-reflection film is completely coated on the peripheral area 25.
Formed by CVD method.

In this example, under AM1 conditions 18.5
We were able to obtain a conversion efficiency of ~20.5% and a FF of 0.82-0.90.

Since the light irradiation 20 was irradiated twice in the V-shaped or inverted trapezoidal groove, the reflectance could be reduced to 12% or less without forming an antireflection film.

Although the counter electrode in the present invention is comb-shaped, it may also be mesh-shaped or fishbone-shaped, and is basically characterized by selectively separating the light irradiation surface having grooves and the presence of the counter electrode. There is.

Embodiment 2 FIG. 2 shows another embodiment of the invention. As ^shown in ^FIG .
In order to efficiently create a depletion layer above the depletion layer, carriers collected by the electric field of this depletion layer are efficiently transferred to the electrode section 5 through the N ⁺ or P ⁺ layer. Further, the light is irradiated twice in the V-shaped groove, and since there is no N ⁺ or P ⁺ layer there, the light can efficiently reach the inside of the semiconductor 1.

In order to provide such a V-shaped or inverted trapezoidal groove only on the light irradiation surface and to facilitate reversal by the semiconductor layer under this V-shaped or inverted trapezoidal groove, a 0.5 inverted conductivity type groove is provided in this region, that is, near the top surface of the substrate semiconductor 1. The layer 7 is provided with a thickness of less than .mu.m, in particular from 20 to 500 .ANG. In addition, an insulating or semi-insulating film 3 and a counter electrode 5 are provided on the upper side.

In the structure shown in FIG. 2, the opposite conductivity type semiconductor layer 7 is provided only on the upper part of the V-shaped or inverted trapezoidal groove, and the pattern is such that the semiconductor layers are continuous with each other and extend below the counter electrode 5. It is effective to do so. Then, one of the electrons and holes formed by light irradiation in the semiconductor below the V-shaped groove is attracted to this opposite conductivity type semiconductor layer 7, and is lost through this upper floating channel to the bottom of the counter electrode. can be made to drift with little effort. In addition, when light is irradiated onto the semiconductor below the V-shaped or inverted trapezoidal groove, the irradiated light is characterized in that there is no loss due to absorption of impurity scattered light by the reverse conductivity type layer. Due to these characteristics, in the present invention, it was possible to obtain a photoelectric conversion efficiency of 20.5% under AM1 conditions, exceeding the theoretical limit of 20% for silicon. In the drawing, SiO or tantalum oxide is used as an anti-reflection coating.
It is formed to a thickness of ~900 Å. In addition, with this structure, it is also possible to detect near-infrared wavelengths, and we have been able to create photoresponse characteristics that are practical even for 950 nm semiconductor laser light.

As a result, the conversion efficiency under AM1 was improved to 18%. In addition, the characteristics under fluorescent light (300 lx), which is a typical short wavelength light, was 50 mW/cm ² .

As is clear from the above embodiments, the floating channel MIS type photoelectric conversion device of the present invention not only has a large effect of the floating channel, but also its shape, that is, the electrode part is flat, and the other parts are uneven. This allows for excellent mass production, and for the first time in the MIS type, we were able to increase the mass production backlog to over 90%. Also regarding reliability,
No particular abnormality was observed during the 1000 hour storage test at 150°C.

Although the present invention is based on a silicon single crystal, semiconductors such as polycrystalline, semi-amorphous, or amorphous structure semiconductors, or silicon produced by a high-speed quenching method or a dentrite method may be used. Further, in addition to silicon, germanium or other compound semiconductors may be used.

Further, the planar pattern of the V-shaped or inverted trapezoidal grooves is not only the shape of this embodiment (square) but may also be rectangular or octagonal.

[Brief explanation of the drawing]

FIG. 1 shows a longitudinal sectional view of an embodiment for manufacturing the invention. FIG. 2 shows a longitudinal cross-sectional view of another photoelectric conversion device of the present invention.

Claims (1)

[Claims] 1. A laminate is formed by providing a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate on top of a semiconductor substrate of one conductivity type, and the semiconductor layer remains on the top of the semiconductor substrate. and a V-shape having a depth extending beyond the interface between the semiconductor layer and the semiconductor substrate and into the inside of the semiconductor substrate on the upper surface of the stack so that the remaining semiconductor layers are electrically connected to each other. Alternatively, an inverted trapezoidal groove is provided, an insulating or semi-insulating film of silicon nitride or silicon carbide with a thickness of 5 to 100 Å is provided on the upper surface of the stacked body, and the insulating or semi-insulating film is provided on the upper surface of the remaining semiconductor layer. A photoelectric conversion device characterized in that an electrode is provided on at least a portion of the upper surface of the photoelectric conversion device.