JP2581054B2 - Semiconductor manufacturing equipment - Google Patents
Semiconductor manufacturing equipmentInfo
- Publication number
- JP2581054B2 JP2581054B2 JP62036266A JP3626687A JP2581054B2 JP 2581054 B2 JP2581054 B2 JP 2581054B2 JP 62036266 A JP62036266 A JP 62036266A JP 3626687 A JP3626687 A JP 3626687A JP 2581054 B2 JP2581054 B2 JP 2581054B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- recess
- semiconductor manufacturing
- edge
- manufacturing apparatus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えばワイヤボンディング工程で使用する
半導体製造装置に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor manufacturing apparatus used in, for example, a wire bonding step.
〔従来の技術〕 従来、この種の半導体製造装置は第３図および第４図
に示すように構成されている。これを同図に基づいて説
明すると、同図において、符号１で示すものはヒータ２
を内蔵するベースブロック、３はこのベースブロック１
上に固定されリードフレーム４のダイパッド５を収納可
能な凹陥部６を有するワイヤボンディング用のプラテン
である。また、７は前記リードフレーム４のダイパッド
５上に接合された半導体素子、８はこの半導体素子７に
Au製のワイヤ９によって接続されたリードである。な
お、前記プラテン３の凹陥部６は放電加工によって形成
される。[Prior Art] Conventionally, this kind of semiconductor manufacturing apparatus is configured as shown in FIGS. This will be described with reference to the same drawing. In FIG.
3 is the base block 1
It is a platen for wire bonding having a recess 6 fixed above and capable of accommodating the die pad 5 of the lead frame 4. Reference numeral 7 denotes a semiconductor element bonded on the die pad 5 of the lead frame 4, and 8 denotes a semiconductor element
The leads are connected by Au wires 9. The recess 6 of the platen 3 is formed by electric discharge machining.
このように構成された半導体製造装置においては、送
り装置（図示せず）によってリードフレーム４をプラテ
ン３に搬送した後、ワイヤ９によって半導体素子７とリ
ード８とを接続することによりワイヤボンディングを行
うことができる。このとき、ダイパッド５がプラテン３
の凹陥部６内に収納されている。In the semiconductor manufacturing apparatus configured as described above, after the lead frame 4 is transported to the platen 3 by a feeder (not shown), the semiconductor element 7 and the lead 8 are connected by wires 9 to perform wire bonding. be able to. At this time, the die pad 5 is
Is housed in the recess 6.
ところで、従来の半導体製造装置においては、プラテ
ン３の加工時に凹陥部６の底面縁部が放電加工治具の摩
耗によって第４図に矢印Ａで示すように曲面状に形成さ
れることがあり、この場合ダイパッド５が凹陥部６の底
面とこの縁部に載置されることになって、ワイヤボンデ
ィング時に半導体素子７に作用する衝撃力や振動（例え
ば超音波等）によってダイパッド５も弾性振動し、良好
なワイヤボンディングを行うことができないという問題
があった。すなわち、ダイパッド５が凹陥部６の底面と
この縁部に載置されると、ダイパッド５とプラテン３と
の間に間隙が形成されるため、半導体素子７からダイパ
ッド５に伝達される衝撃力や振動をプラテン３（ベース
ブロック）によって吸収することができないからであ
る。By the way, in the conventional semiconductor manufacturing apparatus, the edge of the bottom surface of the concave portion 6 may be formed in a curved shape as shown by an arrow A in FIG. In this case, the die pad 5 is placed on the bottom surface of the recess 6 and the edge thereof, and the die pad 5 is also elastically vibrated by an impact force or vibration (for example, ultrasonic wave) acting on the semiconductor element 7 during wire bonding. However, there is a problem that good wire bonding cannot be performed. That is, when the die pad 5 is placed on the bottom surface of the recess 6 and on the edge thereof, a gap is formed between the die pad 5 and the platen 3. This is because vibration cannot be absorbed by the platen 3 (base block).
本発明はこのような事情に鑑みなされたもので、ワイ
ヤボンディング時に半導体素子に作用する衝撃力および
振動をプラテンによって吸収することができ、もってワ
イヤボンディングを良好に行うことができる半導体製造
装置を提供するものである。The present invention has been made in view of such circumstances, and provides a semiconductor manufacturing apparatus capable of absorbing a shock force and a vibration acting on a semiconductor element at the time of wire bonding by a platen, thereby performing good wire bonding. Is what you do.
本発明に係る半導体製造装置は、ワイヤボンディング
用のプラテンにおけるリードフレームのダイパッドを収
納可能な凹陥部を、前記ダイパッドよりも大きく形成す
るとともに、この凹陥部の底面の縁部に沿って凹溝を設
け、この凹溝によって取り囲まれた凹陥部底面の載置部
に前記ダイパッドを配置するにあたって、このダイパッ
ドの縁部が凹溝における載置部寄りの一部を覆うように
構成したものである。In the semiconductor manufacturing apparatus according to the present invention, a concave portion capable of accommodating a die pad of a lead frame in a platen for wire bonding is formed larger than the die pad, and a concave groove is formed along an edge of a bottom surface of the concave portion. When the die pad is arranged on the mounting portion on the bottom surface of the concave portion surrounded by the concave groove, an edge of the die pad covers a part of the concave groove near the mounting portion.
本発明においては、ワイヤボンディング時にリードフ
レームのダイパッドを凹陥部の底面側に収納して載置す
るにあたって、このダイパッドを、凹陥部底面の縁部に
沿って形成した凹溝に臨む縁部を除いて、この凹溝によ
って取り囲まれた凹陥部底面の載置部に密着させて載置
することができる。In the present invention, when the die pad of the lead frame is stored and placed on the bottom surface side of the recess at the time of wire bonding, the die pad is removed except for the edge facing the groove formed along the edge of the bottom of the recess. Thus, it can be placed in close contact with the placing portion on the bottom surface of the concave portion surrounded by the concave groove.
第１図は第２図のＩ−Ｉ断面図、第２図は本発明に係
る半導体製造装置を示す斜視図で、同図において第３図
および第４図と同一の部材については同一の符号を付
し、詳細な説明は省略する。同図において、符号11で示
すものは枠状の凹溝で、前記凹陥部６の底面の縁部に沿
って凹溝を設けている。また、この凹陥部６は、前記ダ
イパッド５よりも面方向において大きく形成している。
そして、この凹陥部６の底面側で凹溝11によって取り囲
まれた部分を前記ダイパッド５の載置部として構成し、
かつこの載置部に載置したときに、前記ダイパッド５の
縁部が凹溝11における載置部寄りの一部を覆うように構
成している。FIG. 1 is a sectional view taken along the line II of FIG. 2, and FIG. 2 is a perspective view showing a semiconductor manufacturing apparatus according to the present invention. In FIG. 1, the same members as those in FIGS. And a detailed description is omitted. In the figure, reference numeral 11 denotes a frame-shaped concave groove, which is provided along the edge of the bottom surface of the concave portion 6. The recess 6 is formed larger in the surface direction than the die pad 5.
A portion surrounded by the concave groove 11 on the bottom surface side of the concave portion 6 is configured as a mounting portion for the die pad 5,
In addition, the edge of the die pad 5 is configured to cover a part of the groove 11 near the mounting portion when the die pad 5 is mounted on the mounting portion.
このように構成された半導体製造装置においては、ワ
イヤボンディング時にリードフレーム４のダイパッド５
を凹陥部６の底面側に収納して載置するにあたって、こ
のダイパッド５を、凹陥部６底面の縁部に沿って形成し
た凹溝11に臨む縁部を除いて、この凹溝11によって取り
囲まれた凹陥部６底面の載置部に密着させて載置するこ
とができる。In the semiconductor manufacturing apparatus thus configured, the die pad 5 of the lead frame 4 is
When the die pad 5 is stored and placed on the bottom surface side of the recess 6, the die pad 5 is surrounded by the recess 11 except for an edge facing the recess 11 formed along the edge of the bottom of the recess 6. It can be placed in close contact with the placement portion on the bottom of the recessed recess 6.
したがって、半導体素子７からダイパッド５に伝達さ
れる衝撃力や振動をプラテン３等によって吸収すること
ができる。Therefore, the impact force and vibration transmitted from the semiconductor element 7 to the die pad 5 can be absorbed by the platen 3 or the like.
すなわち、本発明においては、プラテン３に対し凹溝
11を設けることにより、一次加工によって形成される曲
面状の底面縁部を無くして、ワイヤボンディング時に発
生するダイパッド５の振動を防止することができるので
ある。That is, in the present invention, the concave groove is formed on the platen 3.
By providing 11, the edge of the curved bottom surface formed by the primary processing can be eliminated, and the vibration of the die pad 5 generated at the time of wire bonding can be prevented.
以上説明したように本発明に係る半導体製造装置によ
れば、プラテンのダイパッド収納用の凹陥部を、ダイパ
ッドよりも大きく形成するとともに、この凹陥部の底面
の縁部に沿って凹溝を設け、この凹溝によって取り囲ま
れた凹陥部底面の載置部に前記ダイパッドを載置するに
あたって、このダイパッドの縁部が凹溝における載置部
寄りの一部を覆うように構成したので、以下に述べる優
れた効果を奏する。As described above, according to the semiconductor manufacturing apparatus of the present invention, the recess for accommodating the die pad of the platen is formed larger than the die pad, and the recess is provided along the edge of the bottom surface of the recess, In mounting the die pad on the mounting portion on the bottom surface of the concave portion surrounded by the concave groove, the edge of the die pad is configured to cover a part of the concave groove near the mounting portion, and will be described below. It has excellent effects.
すなわち、本発明によれば、ワイヤボンディング時に
リードフレームのダイパッドを凹陥部の底面側に収納す
るにあたって、このダイパッドを、凹陥部底面の縁部に
沿って形成した凹溝に臨む縁部を除いて、この凹溝によ
って取り囲まれた凹陥部底面の載置部に密着させて載置
することができる。したがって、半導体素子からダイパ
ッドに伝達される衝撃力および振動をプラテンによって
吸収することができるため、ダイパッドの振動を防止す
ることができ、その結果としてワイヤボンディングを良
好に行うことができる。That is, according to the present invention, when accommodating the die pad of the lead frame on the bottom side of the recess at the time of wire bonding, this die pad is removed except for the edge facing the groove formed along the edge of the bottom of the recess. It can be placed in close contact with the mounting portion on the bottom surface of the concave portion surrounded by the concave groove. Therefore, the impact force and the vibration transmitted from the semiconductor element to the die pad can be absorbed by the platen, so that the vibration of the die pad can be prevented, and as a result, the wire bonding can be favorably performed.
第１図は第２図のＩ−Ｉ断面図、第２図は本発明に係る
半導体製造装置を示す斜視図、第３図および第４図は従
来の半導体製造装置を示す斜視図と断面図である。 ３……プラテン、４……リードフレーム、５……ダイパ
ッド、６……凹陥部、７……半導体素子、11……凹溝。1 is a sectional view taken along the line II of FIG. 2, FIG. 2 is a perspective view showing a semiconductor manufacturing apparatus according to the present invention, and FIGS. 3 and 4 are perspective views and sectional views showing a conventional semiconductor manufacturing apparatus. It is. 3 ... platen, 4 ... lead frame, 5 ... die pad, 6 ... recessed part, 7 ... semiconductor element, 11 ... concave groove.
フロントページの続き (56)参考文献 実開 昭59−159947（ＪＰ，Ｕ) 実開 昭55−145047（ＪＰ，Ｕ) 実開 昭54−35859（ＪＰ，Ｕ)Continuation of the front page (56) References Japanese Utility Model Showa 59-159947 (JP, U) Japanese Utility Model Showa 55-145047 (JP, U) Japanese Utility Model Showa 54-35859 (JP, U)
Claims (1)
凹陥部を有するワイヤボンディング用のプラテンを備え
た半導体製造装置において、 前記凹陥部を前記ダイパッドよりも大きく形成するとと
もに、この凹陥部の底面の縁部に沿って凹溝を設け、こ
の凹溝によって取り囲まれた凹陥部底面の載置部にダイ
パッドを配置するにあたって、このダイパッドの縁部が
前記凹溝における載置部寄りの一部を覆うように構成し
たことを特徴とする半導体製造装置。1. A semiconductor manufacturing apparatus provided with a wire bonding platen having a recess capable of accommodating a die pad of a lead frame, wherein the recess is formed larger than the die pad and an edge of a bottom surface of the recess. A groove is provided along the portion, and when the die pad is arranged on the mounting portion on the bottom surface of the concave portion surrounded by the groove, the edge of the die pad covers a part of the concave groove near the mounting portion. A semiconductor manufacturing apparatus characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62036266A JP2581054B2 (en) | 1987-02-18 | 1987-02-18 | Semiconductor manufacturing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62036266A JP2581054B2 (en) | 1987-02-18 | 1987-02-18 | Semiconductor manufacturing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63202928A JPS63202928A (en) | 1988-08-22 |
| JP2581054B2 true JP2581054B2 (en) | 1997-02-12 |
Family
ID=12464963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62036266A Expired - Lifetime JP2581054B2 (en) | 1987-02-18 | 1987-02-18 | Semiconductor manufacturing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2581054B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55145047U (en) * | 1979-04-02 | 1980-10-17 | ||
| JPS59159947U (en) * | 1983-04-11 | 1984-10-26 | 日本電気ホームエレクトロニクス株式会社 | Semiconductor device manufacturing equipment |
-
1987
- 1987-02-18 JP JP62036266A patent/JP2581054B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63202928A (en) | 1988-08-22 |
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