JPH0680749B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0680749B2
JPH0680749B2 JP62112901A JP11290187A JPH0680749B2 JP H0680749 B2 JPH0680749 B2 JP H0680749B2 JP 62112901 A JP62112901 A JP 62112901A JP 11290187 A JP11290187 A JP 11290187A JP H0680749 B2 JPH0680749 B2 JP H0680749B2
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
main surface
external
external connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62112901A
Other languages
Japanese (ja)
Other versions
JPS63276250A (en
Inventor
博司 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62112901A priority Critical patent/JPH0680749B2/en
Publication of JPS63276250A publication Critical patent/JPS63276250A/en
Publication of JPH0680749B2 publication Critical patent/JPH0680749B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置、特に樹脂成型された半導体集積
回路装置に関するものである。
The present invention relates to a semiconductor device, and more particularly to a resin-molded semiconductor integrated circuit device.

〔従来の技術〕[Conventional technology]

第5図は従来の樹脂成型された半導体集積回路装置の一
例を示す斜視図である。図において(1)は互いにほぼ
平行な第1の主表面(上主面)と第2の主表面(下主
面)と周側面とを有する半導体集積回路チップ、(2)
は上記第1主表面上に被着された複数の外部接続用パッ
ド、(3)は上記第2主表面に固着された支持板、
(4)は複数の外部リード、(5)は外部接続用パッド
(2)と外部リード(4)を接続するワイヤ、(6)は
(1),(2),(3),(4),を被覆する樹脂成型
部材である。また第6図はプリント配線板等に実装され
た半導体集積回路チップの一例を示す断面図である。図
において(7)はプリント配線板、(8)はプリント配
線板(7)上に配線された配線導体、(9)は外部接続
パッド(2)上に設けられ、同パッドと配線導体(8)
を接続する突起電極、(10)はチップ(1)、パッド
(2)、電極(9)等を保護するため、電極(9)を配
線(8)に接合した後に被着された被覆材である。
FIG. 5 is a perspective view showing an example of a conventional resin-molded semiconductor integrated circuit device. In the figure, (1) is a semiconductor integrated circuit chip having a first main surface (upper main surface), a second main surface (lower main surface) and a peripheral side surface which are substantially parallel to each other, (2)
Is a plurality of pads for external connection adhered to the first main surface, (3) is a support plate fixed to the second main surface,
(4) is a plurality of external leads, (5) is a wire connecting the external connection pad (2) and the external lead (4), (6) is (1), (2), (3), (4) , Which is a resin molded member for covering the. FIG. 6 is a sectional view showing an example of a semiconductor integrated circuit chip mounted on a printed wiring board or the like. In the figure, (7) is a printed wiring board, (8) is a wiring conductor wired on the printed wiring board (7), (9) is provided on an external connection pad (2), and the pad and the wiring conductor (8) are provided. )
The protruding electrode (10) for connecting the electrodes is a covering material applied after the electrode (9) is bonded to the wiring (8) in order to protect the chip (1), the pad (2), the electrode (9) and the like. is there.

さて、第5図に示す如き従来の樹脂成型された半導体集
積回路装置では集積回路チップ(1)は支持板(3)で
固着して機械的強度を保たせ、外部接続用パット(2)
と外部リード(4)をワイヤ(5)で接続し、半導体集
積回路チップ(1)と、外部回路との電気信号の授受を
可能としている。また半導体集積回路チップ(1)は機
械的強度が弱く、また半導体集積回路の特性は外部雰囲
気の影響を受けやすい。更にワイヤ(5)は通常直径20
〜50μmの金、アルミニウム、銅等の金属細線が用いら
れるためその機械的強度は弱い。半導体集積回路チッ
プ、ワイヤの機械的強度を保護し、半導体集積回路の特
性を外部雰囲気から保護するため樹脂成型部材(6)が
被覆成型されている。
Now, in the conventional resin-molded semiconductor integrated circuit device as shown in FIG. 5, the integrated circuit chip (1) is fixed by the support plate (3) to maintain the mechanical strength, and the external connection pad (2) is provided.
The external lead (4) is connected to the external lead (4) by a wire (5), so that electric signals can be exchanged between the semiconductor integrated circuit chip (1) and the external circuit. Further, the semiconductor integrated circuit chip (1) has low mechanical strength, and the characteristics of the semiconductor integrated circuit are easily affected by the external atmosphere. Furthermore, the wire (5) usually has a diameter of 20
The mechanical strength is weak because a fine metal wire of gold, aluminum, copper or the like having a thickness of up to 50 μm is used. A resin molding member (6) is covered and molded to protect the mechanical strength of the semiconductor integrated circuit chip and the wires and to protect the characteristics of the semiconductor integrated circuit from the external atmosphere.

また第6図の如き例はプリント配線板(7)へ樹脂成型
されていない半導体集積回路チップ(1)を直接突起し
たもので、ワイヤ、外部リードを介さずに外部接続用パ
ッド(2)とプリントは配線板(7)上の配線(8)と
を接合するため、パッド(2)上に突起電極(9)を設
け所謂フェーズ・ダウンボンディングで接続したもの
で、チップ(1)、及び配線(8)と電極(9)の接続
部を保護するため被覆材(10)(例えば熱可塑性樹脂)
が被覆されている。この被覆材(10)は成型されていな
いため、被覆された形状は必ずしも一定していない。
Further, in the example as shown in FIG. 6, a semiconductor integrated circuit chip (1) which is not resin-molded is directly projected onto a printed wiring board (7), and an external connection pad (2) is formed without interposing wires or external leads. Since the print is connected to the wiring (8) on the wiring board (7), a bump electrode (9) is provided on the pad (2) and connected by so-called phase down bonding. The chip (1) and the wiring are connected. A covering material (10) (for example, a thermoplastic resin) for protecting the connection between the electrode (8) and the electrode (9)
Are covered. Since this covering material (10) is not molded, the covered shape is not always constant.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

第5図の如き半導体集積回路においては、半導体集積回
路チップ(1)の他支持板(3)、外部リード(4)、
ワイヤ(5)を必要とし、更に樹脂成型されるため、そ
の組立工程においてこれらを接続、成型する組立工程が
複雑であり、また精密な組立技術を必要とする。即ちか
かる半導体集積回路を組立てるには例えば予め作成され
た半導体集積回路チップ(1)を一般にリードフレーム
と呼ばれる支持板(3)、外部リード(4)が一体化さ
れたものの、支持板(3)の所定部に固定し、外部接続
用パッド(2)と外部リード(4)をワイヤ(5)によ
り接続する。このワイヤは前記の如く直径は通常20〜50
μと極めて細く、この接続は極めて精密な技術を必要と
する。また外部接続用パッドの数は通常10前後から100
以上に及ぶものもあり多くの手数を要する。次いで全体
を樹脂成型した後、前記リードフレームの不要部分を除
去し、必要に応じ外部リードの曲げ等の成型が行われ
る。以上の様に組立工程は多くの手数を要すると共に外
部リード(4)を要するため、半導体集積回路チップ
(1)に比し完成した半導体集積回路装置ははるかに大
きなものとなり、これを使用する場合の実装密度は低く
なる。更に接続に用いるワイヤによる浮遊容量、浮遊イ
ンダクタンスは半導体集積回路の信号処理時間を遅らせ
る結果にもなる。
In the semiconductor integrated circuit as shown in FIG. 5, the semiconductor integrated circuit chip (1), the other supporting plate (3), the external leads (4),
Since the wire (5) is required and is further resin-molded, the assembling process of connecting and molding these is complicated in the assembling process, and a precise assembling technique is required. That is, for assembling such a semiconductor integrated circuit, for example, a semiconductor integrated circuit chip (1) prepared in advance is integrated with a support plate (3) generally called a lead frame and external leads (4), but a support plate (3) Then, the external connection pad (2) and the external lead (4) are connected to each other by a wire (5). This wire usually has a diameter of 20 to 50 as described above.
Very thin as μ, this connection requires extremely precise technology. The number of external connection pads is usually around 10 to 100.
Some of them are more than the above, which requires a lot of trouble. Next, after the whole is resin-molded, unnecessary parts of the lead frame are removed, and molding such as bending of external leads is performed as necessary. As described above, the assembling process requires a large number of steps and requires the external leads (4). Therefore, the completed semiconductor integrated circuit device is much larger than the semiconductor integrated circuit chip (1). The packaging density of is low. Furthermore, stray capacitance and stray inductance due to the wires used for connection also result in delaying the signal processing time of the semiconductor integrated circuit.

第6図の如き例では第5図の例の欠点の一部は除かれて
いる。例えばワイヤによる接続が不要のため、半導体集
積回路の組立工程は簡単になり、また半導体集積回路チ
ップが直接使用する電子機器のプリント配線板等に実装
されるので実装密度は高まり、接続ワイヤによる浮遊イ
ンダクタンス、浮遊容量が軽減されるため信号処理時間
も早く出来る。しかし一方プリント配線板に実装し被覆
材を被着する迄半導体集積回路チップは保護手段がとら
れていないため外部雰囲気により特性が劣化する可能性
がある。また半導体集積回路チップは通常数mm角、厚み
200〜500μm程度の小片で脆いため取扱中割れ、欠けを
生じやすい。また実装後被覆材で被着する場合プリント
配線板上の被着範囲、形状は一定にし難い。更にプリン
ト配線板とは突起電極による接続のため熱放散が困難で
ある。
The example of FIG. 6 eliminates some of the drawbacks of the example of FIG. For example, since the wire connection is not required, the process of assembling the semiconductor integrated circuit is simplified, and since the semiconductor integrated circuit chip is directly mounted on the printed wiring board of an electronic device, the mounting density is increased and the floating by the connection wire is caused. Since the inductance and stray capacitance are reduced, the signal processing time can be shortened. On the other hand, however, the semiconductor integrated circuit chip has no protective means until it is mounted on the printed wiring board and coated with a covering material, so that the characteristics may be deteriorated by the external atmosphere. Also, semiconductor integrated circuit chips are usually several mm square and have a thickness
Small pieces of about 200 to 500 μm are fragile and easily cracked or chipped during handling. In addition, when a covering material is applied after mounting, it is difficult to make the adhered area and shape on the printed wiring board constant. Furthermore, it is difficult to dissipate heat because it is connected to the printed wiring board by the protruding electrodes.

この発明は上記の問題点を解決するためになされたもの
で、半導体集積回路チップを外部雰囲気から保護し、機
械的に保護し、組立が容易で、小型化し使用時の実装密
度が高く、信号処理速度の早い半導体集積回路を提供す
ることにある。
The present invention has been made to solve the above problems, and protects a semiconductor integrated circuit chip from the external atmosphere, protects it mechanically, is easy to assemble, is small in size, has a high packing density during use, and has a high signal density. It is to provide a semiconductor integrated circuit having a high processing speed.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体集積回路装置は支持板に固着され
た半導体集積回路チップの表面に設けた外部接続用パッ
ドを開口させる切込みを有する樹脂成型部材により、半
導体集積回路チップ表面及側面を覆ったものである。
A semiconductor integrated circuit device according to the present invention covers a surface and a side surface of a semiconductor integrated circuit chip with a resin molding member having a notch for opening an external connection pad provided on the surface of the semiconductor integrated circuit chip fixed to a support plate. Is.

〔作用〕[Action]

この発明による半導体集積回路装置は外部リードを持た
ない故に小型であり、しかも半導体集積回路チップのパ
ッドを有する側の主表面、及び側面は成型樹脂で被覆さ
れた機械的保護、外部雰囲気にも影響され難しくなって
いる。またワイヤによる接続がなく組立が簡単であると
共に回路の浮遊容量、浮遊インダクタンスが減少し、信
号処理時間を早くすることが出来る。また支持板は半導
体集積回路の熱放散を高める。
Since the semiconductor integrated circuit device according to the present invention has no external leads, it is small in size, and the main surface and side surface of the semiconductor integrated circuit chip on the side having the pad are covered with molding resin for mechanical protection and influence on the external atmosphere. It is getting harder. Further, since there is no connection by wires, the assembly is simple, and the stray capacitance and stray inductance of the circuit are reduced, and the signal processing time can be shortened. The support plate also enhances heat dissipation of the semiconductor integrated circuit.

〔発明の実施例〕Example of Invention

第1図はこの発明の一実施例を示す半導体集積回路装置
の斜視図で(1)〜(3),(6)は上記従来装置と同
一のものである。半導体集積回路チップ(1)の第1主
表面(1A)には複数の外部接続用パッド(2)が設けら
れており、第2主表面(1B)は支持板(3)に固着され
ている。半導体集積回路チップ(1)の第1主表面(1
A)、側面(1C)は樹脂成型部材(6)で被覆されてお
り、この樹脂成型部材(6)はパッド(2)と同数の開
口切込部(11)を備え、この開口切込部(11)は各外部
接続用パッド(2)を露出させている。この外部接続用
パッド(2)は通常アルミニューム等の良導電体材料で
作られるが、湿気等外部雰囲気の影響を避けるためには
モリブデン、タングステン、タンタル、チタン、金等の
耐候性金属、又はその合金を少なくともその一部に用い
ると効果的である。
FIG. 1 is a perspective view of a semiconductor integrated circuit device showing an embodiment of the present invention, and (1) to (3) and (6) are the same as those of the conventional device. A plurality of external connection pads (2) are provided on the first main surface (1A) of the semiconductor integrated circuit chip (1), and the second main surface (1B) is fixed to the support plate (3). . First main surface (1) of a semiconductor integrated circuit chip (1)
A), the side surface (1C) is covered with a resin molding member (6), and the resin molding member (6) has the same number of opening notches (11) as the pad (2). (11) exposes each external connection pad (2). The external connection pad (2) is usually made of a good conductor material such as aluminum, but in order to avoid the influence of external atmosphere such as moisture, molybdenum, tungsten, tantalum, titanium, gold or the like weather resistant metal, or It is effective to use the alloy for at least a part thereof.

第1図の例では外部接続用パッド(2)は半導体集積回
路チップ(1)の一つの辺のみに沿って設けられている
シングルインライン型である。このような場合にこれに
合せて、実施例のように、開口切込部(11)を樹脂成型
部材(6)の一つの端辺(6A)から各パッド(2)の上
部へ延長することにより、例えば実装するプリント配線
等の所定位置に外部接続用パッド(2)に接続する突起
を設け、ここにこの発明による集積回路装置を挿着する
ことも可能で、実装密度をより上げることが出来る。ま
た外部接続パッド(2)を一辺に限らず各辺に設けるな
り、複数の半導体集積回路チップを一つに成型すること
も可能なことは言う迄もない。
In the example of FIG. 1, the external connection pad (2) is a single in-line type provided along only one side of the semiconductor integrated circuit chip (1). In such a case, the opening notch (11) is extended from one end side (6A) of the resin molding member (6) to the upper part of each pad (2) in accordance with this, as in the embodiment. Thus, for example, it is possible to provide a projection connected to the external connection pad (2) at a predetermined position of a printed wiring to be mounted, and insert the integrated circuit device according to the present invention therein, and to further increase the mounting density. I can. Further, it goes without saying that the external connection pads (2) are not limited to one side and are provided on each side, and a plurality of semiconductor integrated circuit chips can be molded into one.

上記のように構成された半導体集積回路では半導体集積
回路チップ(1)は樹脂成型部材(6)により第1主表
面(1A)、側面(1C)が被覆成型され外部雰囲気からの
保護、機械的保護が施され、外部接続用パッド(2)は
樹脂成型部材(6)の開口切込部(11)により外部に露
出しており、これにより半導体集積回路の外部回路との
接続が可能となる。
In the semiconductor integrated circuit configured as described above, the semiconductor integrated circuit chip (1) has the first main surface (1A) and the side surface (1C) covered and molded with the resin molding member (6) to protect it from the external atmosphere and mechanically. Protected, the external connection pad (2) is exposed to the outside by the opening notch (11) of the resin molding member (6), which enables connection with the external circuit of the semiconductor integrated circuit. .

第2図はこの発明の他の実施例を示す斜視図、第3図は
同実施例のA−B断面図である。(12)は半導体集積回
路チップ(1)と支持板(3)を接着する接着材であ
る。この実施例では外部接続用パッド(2)の上面の限
定された部分、即ちその中央部のみが露出されており、
周端部は樹脂成型部材で覆われている。この実施例で
は、外部接続用パッドの一部のみが外部雰囲気に接し、
残は樹脂成型部材で被覆保護されたいるので、外部雰囲
気からの保護にも優れている。樹脂成型部材(6)の端
辺(6A)と外部接続用パッド(2)との間の部分(6B)
の樹脂成型部材(6)の厚みが薄くされており、プリン
ト配線板に実装する場合、プリント配線板に設けられた
可撓性金属電極部材がこの部分(6B)上から外部接続端
子(2)上に導入されて圧接するのが容易になる。
FIG. 2 is a perspective view showing another embodiment of the present invention, and FIG. 3 is an AB sectional view of the same embodiment. Reference numeral (12) is an adhesive material for adhering the semiconductor integrated circuit chip (1) and the support plate (3). In this embodiment, only a limited part of the upper surface of the external connection pad (2), that is, the central part thereof is exposed,
The peripheral end is covered with a resin molding member. In this embodiment, only a part of the external connection pad is exposed to the external atmosphere,
Since the rest is covered and protected by a resin molding member, it is also excellent in protection from the external atmosphere. Portion (6B) between the edge (6A) of the resin molded member (6) and the external connection pad (2)
When the resin molded member (6) is thinned and mounted on the printed wiring board, the flexible metal electrode member provided on the printed wiring board is connected to the external connection terminal (2) from above this portion (6B). Introduced on top to facilitate pressure contact.

第4図はこの発明の更に他の実施例を示す半導体集積回
路装置の側断面図である。この実施例では半導体集積回
路チップ(1)の第2主表面(1B)に固着された支持板
(3)の前記第2主表面(1B)を固着した面と反対側の
面を樹脂成型部材(6)より露出させたものであって支
持板(3)の熱放散を容易とすることが出来る。
FIG. 4 is a side sectional view of a semiconductor integrated circuit device showing still another embodiment of the present invention. In this embodiment, the surface of the supporting plate (3) fixed to the second main surface (1B) of the semiconductor integrated circuit chip (1) opposite to the surface to which the second main surface (1B) is fixed is a resin molding member. Since it is exposed from (6), the heat dissipation of the support plate (3) can be facilitated.

〔発明の効果〕〔The invention's effect〕

この発明は以上説明した如く半導体集積回路の組立にお
いてワイヤの接続が不要で組立工程が簡単になり、より
安価な集積回路装置の提供が可能となり、また小型にな
るため実装密度が上り、一方樹脂成型部材で被覆されて
いるため機械的強度が保ち得て、取扱いが容易になる効
果がある。
INDUSTRIAL APPLICABILITY As described above, the present invention does not require wire connection in assembling a semiconductor integrated circuit, simplifies the assembling process, makes it possible to provide a cheaper integrated circuit device, and because the size is small, the mounting density is increased, while the resin Since it is covered with the molded member, the mechanical strength can be maintained and the handling becomes easy.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の一実施例を示す斜視図、第2図はこ
の発明の他の実施例を示す斜視図、第3図はその断面
図、第4図は更に他の実施例を示す断面図、第5図は従
来の半導体集積回路の斜視図、第6図は従来の他の半導
体集積回路の実装の側断面図である。 図において(1)は半導体集積回路チップ、(2)は外
部接続用パッド、(3)は支持板、(6)は樹脂成型部
材、(11)は開口切込部である。
FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a perspective view showing another embodiment of the present invention, FIG. 3 is a sectional view thereof, and FIG. 4 is a further embodiment. A sectional view, FIG. 5 is a perspective view of a conventional semiconductor integrated circuit, and FIG. 6 is a side sectional view of mounting of another conventional semiconductor integrated circuit. In the figure, (1) is a semiconductor integrated circuit chip, (2) is an external connection pad, (3) is a support plate, (6) is a resin molding member, and (11) is an opening notch.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】互いにほぼ平行な第1主表面と第2主表面
及び側面を有し、第2主表面側が支持板に固着され、上
記第1主表面側に複数の外部接続用パッドを有する半導
体集積回路チップ、少くとも上記チップの第1主表面側
と、上記チップの側面を覆う樹脂成型部材を備え、上記
外部接続用パッドを開口させる切込みを上記樹脂成型部
材に形成したことを特徴とする半導体集積回路装置。
1. A first main surface, a second main surface and side surfaces that are substantially parallel to each other, a second main surface side being fixed to a support plate, and a plurality of external connection pads being provided on the first main surface side. A semiconductor integrated circuit chip, comprising a resin molding member covering at least the first main surface side of the chip and a side surface of the chip, wherein a notch for opening the external connection pad is formed in the resin molding member. Integrated circuit device.
【請求項2】支持板のチップ固着面と反対側の表面を樹
脂成型部材より露出させたこを特徴とする特許請求の範
囲第1項記載の半導体集積回路装置。
2. The semiconductor integrated circuit device according to claim 1, wherein a surface of the supporting plate opposite to the chip fixing surface is exposed from a resin molding member.
JP62112901A 1987-05-08 1987-05-08 Semiconductor integrated circuit device Expired - Lifetime JPH0680749B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62112901A JPH0680749B2 (en) 1987-05-08 1987-05-08 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62112901A JPH0680749B2 (en) 1987-05-08 1987-05-08 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS63276250A JPS63276250A (en) 1988-11-14
JPH0680749B2 true JPH0680749B2 (en) 1994-10-12

Family

ID=14598329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62112901A Expired - Lifetime JPH0680749B2 (en) 1987-05-08 1987-05-08 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0680749B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199548A (en) * 2009-01-30 2010-09-09 Elpida Memory Inc Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JPS63276250A (en) 1988-11-14

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