JP2576287B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a data processing device, which aims to prevent a state in which a processor is stopped due to occurrence of a parity error during running at a specific running level. A processor that outputs running level information representing the following, a data transfer circuit that performs data transfer between the processor and peripheral circuits, and a data transfer control unit that controls the data transfer of the processor accompanying execution of the program. Wherein the data transfer circuit has different data transfer functions of a first transfer circuit having a parity check circuit and a second transfer circuit having a parity check circuit and a parity generation circuit. , The data transfer control unit, based on the running level information output from the processor, the first transfer circuit and the The data transfer control is performed by switching to the transfer circuit corresponding to the traveling level information among the two transfer circuits.

[Industrial applications]

 The present invention relates to an improvement in a data processing device.

If a processor with multiple running levels detects a parity error in the read data and performs error processing at the highest machine check level, and a parity error occurs again, the error interrupt will not be accepted, or The processor stops.

When the processor stops, it becomes impossible to determine the cause of the error. Therefore, there is a need for a data processing device that prevents the processor from stopping due to the double error.

[Conventional technology]

The data transfer control in the conventional data processing apparatus will be described with reference to FIG.

In FIG. 3, 1 is a processor, 18 is a processor 1
The data transfer control unit 21 provided outside the display unit 5
A memory / IO bus 20 for connecting and controlling IO devices such as the disk unit 6 and the floppy unit 7 and a memory not shown, and a data bus 20 having a parity for exchanging data between the processor 1 and the memory / IO bus 21 And 3, a driver for transferring data from the processor 1 in the direction of the memory / IO bus 21;
Is a receiver for transferring data from the memory / IO bus 21 to the processor 1.

The processor 1 has a plurality of running levels, here, a machine check level, an IO 1 level, an IO 2 level, and a CPU level.

The machine check level is a driving level used only when the system detects any error or abnormality, IO 1
The level and the IO2 level are running levels used when accessing an IO device or the like, and are set arbitrarily in the control program, or are switched by a status corresponding to the running level or an interrupt from the device.

The CPU level is a normal running level and can be set only by the control program.

The priority of each running level is determined, and the machine check, IO1, IO2, and CPU levels are in descending order. Then, when an interruption of a traveling level higher than the current traveling level occurs, the interruption is accepted and the traveling level is switched to the accepted traveling level.

Further, the processor 1 has a parity check function for the data bus 20.

In the function as described above, the processor 1 has a memory / I
When reading data from the O bus 21, the data transfer control unit 18 outputs an R Enable signal to the receiver 4 according to a W / R control signal output from the processor 1. This allows
The processor 1 receives data sent from the memory / IO bus 21 through the receiver 4.

If the received data has a parity error, a machine check factor occurs in the processor 1 and the processor 1 switches to the machine check level.

At this time, if the processor 1 is already running at the machine check level, an interrupt is not accepted or halt (stopped) even if a factor for the machine check occurs.

[Problems to be solved by the invention]

As described above, if there is a parity error in the read data to the processor 1, the operation of the processor 1 stops depending on the running level.

When the processor 1 stops, the system also stops.
Even if the stop is due to an error, it is not known where the error occurred.

Therefore, when a parity error is detected, the processor 1 may be configured to generate a normal parity. However, in this case, two read cycles are required, and there is a problem that the data transfer speed is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processing device that eliminates the cause of the above-mentioned processor stoppage.

[Means for solving the problem]

FIG. 1 In the principle diagram of the present invention, reference numeral 1 denotes a processor which has a plurality of running levels and outputs running level information of a running program.

Reference numeral 30 denotes a data transfer circuit (hereinafter referred to as a data transfer path), which is composed of a plurality of different transfer functions of a first transfer circuit having a parity check circuit and a second transfer circuit having a parity check circuit and a parity generation circuit. You.

Reference numeral 2 denotes a data transfer control unit which performs data transfer control by switching to a transfer circuit corresponding to the running level of the first transfer circuit and the second transfer circuit based on the running level information output from the processor 1.

[Action]

Processor 1 outputs a running level state signal, and data transfer control unit 2 switches data transfer path 30 according to the running level based on the signal.

The data transfer path 30 is provided with a predetermined function corresponding to the running level, for example, a parity checking function for a normal running level, and a parity check and parity generating function for a machine checking level. At the check level, normal data is reproduced outside the processor 1 and transferred to the processor 1.

As a result, a parity error is not detected by the processor 1 during the machine check, and therefore, a factor that causes the processor 1 to stop is eliminated.

〔Example〕

 An embodiment of the present invention will be described in detail with reference to the drawings.

 FIG. 2 is a configuration diagram of one embodiment.

In the present embodiment, an example in which the data transfer path is switched from the conventional data transfer path shown in FIG. 3 to the second data transfer path 30a (the path shown by the thick line in FIG. 2) at the time of data reading during machine check level running. Is shown. Then, a parity check function and a parity generation function are provided as functions of the second data transfer path 30a. In the drawing, reference numeral 1 denotes a processor CPU, which runs at four levels of a machine check level, an IO 1 level, an IO 2 level, and a CPU level, and a running level state signal (a level [X, X described later) representing the running level during running. ]) Is output. A parity check circuit PC17 is provided to check the parity of the read data.

2 is a data transfer control unit. In the data transfer control unit 2, reference numeral 12 denotes a receiver, which is provided in the second data transfer path 30a and transfers data from the memory / IO bus 21 to the processor 1.

Reference numeral 8 denotes a decoder, which is a state signal of the encoded running level output from the processor 1, here the level [X, X]
To decode.

Reference numeral 9 denotes a W / R Enable control circuit which turns on the R Enable signal to open the receiver 4 when reading IO1, IO2, and CPU levels other than the machine check level.

An R Enable control circuit 10 turns on the MCH R Enable signal to open the receiver 12 when the machine check level is read.

Reference numeral 15 denotes a parity check circuit.PC 14 denotes a parity generator.PG 11 denotes a switching control circuit. When a parity error is detected by PC 15, the multiplexer MPX 13 is controlled to
And outputs the newly generated parity to the receiver 12.

13 is a multiplexer MPX, which outputs the read data with parity of the memory / IO bus 21 to the receiver 12 as it is when no parity error is detected, and replaces the parity in the read data with a new parity when a parity error is detected. And output to the receiver 12.

A status register 16 stores a parity error status.

 In addition, the same reference numerals represent the same objects throughout the drawings.

In the above configuration, the following data transfer control is performed.

When the processor 1 is running at the IO1, IO2, and CPU levels, the processor 1 outputs the level [0,
[0], [0,1], and [1,0] are output, and the corresponding outputs 0, 1, and 2 are output from the decoder 8.

At the machine check level, [1,1] is output, and the output 8 is output from the decoder 8.

While the processor 1 is running at the IO1, IO2, and CPU levels, when a read (R) signal is output from the processor 1 as a W / R control signal, the W / R Enable control circuit 9 performs R Enable. The signal is turned on, and the receiver 4 is opened. As a result, the read data passes through the receiver 4 and passes through the data bus.
Output to 20 and read to processor 1.

In the processor 1, the parity check of the read data is performed. If an error occurs, a machine check factor is caused, and the running level becomes the machine check level and predetermined processing is performed.

Since the output of the decoder 8 is "3" during the machine check level running, the R Enable control circuit 10 sets the MCH R Enable
Turn on the signal. As a result, the receiver 12 is opened, and the read data is sent to the processor 1 through the data bus 20.

At this time, parity check and generation are performed in the PC 15 and the PG 14. At this time, if there is a parity error in the data, a parity error status is set in the register STS16, and a newly generated parity is sent to the data bus 20.

Since the processor 1 performs a parity check using the newly generated parity, the processor 1 does not detect a parity error inside the processor 1 and can continue processing.

Note that the parity error detected in the second data transfer path 30a is detected by the processor 1 later in the register STS16.
Or the processor 1 may be notified by means that does not directly cause a machine check.

As described above, during the machine check level, the read data is transferred by switching the path to the second data transfer path 30a having the parity check and parity generation functions. Therefore, the parity error is detected by the processor 1 during the error processing. Therefore, the processor 1 does not halt.

〔The invention's effect〕

As described above, the present invention provides a plurality of data transfer paths and switches the data transfer path in accordance with the running level of the processor. In particular, at the machine check level, the data transfer path is switched and read through the path. If the parity error of the data is detected and the parity is generated, the parity error will not be detected by the processor, and therefore, there is an effect that the stop of the processor due to the double error can be prevented.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a configuration diagram of one embodiment,
FIG. 3 is a configuration diagram of a conventional example. In the figure, 1 is a processor CPU, 2 and 18 are data transfer control units,
3 is a driver, 4 and 12 are receivers, 5 is a display unit, 6 is a disk unit, 7 is a floppy unit, 8 is a decoder, and 9 is W / R En.
able control circuit, 10 is an R enable control circuit, 11 is a switching control circuit, 13 is a multiplexer MPX, 14 is a parity generator PG, 15 and 17 are parity check circuits PC, 16 is a status register STS, 20 is a data bus, and 21 is a data bus. Memory / IO bus,
30 is a data transfer path, and 30a is a second data transfer path.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hitari Ogura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-63-86162 (JP, A) JP-A-2-199936 (JP, A)

Claims (1)

(57) [Claims] 1. A processor for outputting running level information indicating a type of a running program, a data transfer circuit for transferring data between the processor and a peripheral circuit, and the data of the processor accompanying execution of the program. A data transfer control unit that controls transfer, wherein the data transfer circuit is different from a first transfer circuit including a parity check circuit and a second transfer circuit including a parity check circuit and a parity generation circuit. The data transfer control unit comprises a first transfer circuit and a second transfer circuit based on the running level information output from the processor.
The data transfer control is performed by switching to the transfer circuit corresponding to the traveling level information among the transfer circuits of the above. The plurality of data transfer circuits having different data transfer functions are provided, and the data transfer circuit is switched according to the traveling level. Data transfer based on the running of the program.