JP2546482B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2546482B2 JP2546482B2 JP5078399A JP7839993A JP2546482B2 JP 2546482 B2 JP2546482 B2 JP 2546482B2 JP 5078399 A JP5078399 A JP 5078399A JP 7839993 A JP7839993 A JP 7839993A JP 2546482 B2 JP2546482 B2 JP 2546482B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- mercury
- connection hole
- insulating film
- barrier metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に関し、特に配線及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to wiring and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来の半導体装置は、配線材としてアル
ミニウムが広く用いられてきたが、半導体素子の微細化
に伴って金属配線の微細化が進み、ストレスマイグレー
ションやエレクトロマイグレーションによる配線材料の
断線といった問題が生じている。そこで、配線部の製造
工程で生じるストレスマイグレーションやエレクトロマ
イグレーションによる断線や、金属配線およびそのコン
タクトホール部等に通電したときに生じるストレスマイ
グレーションやエレクトロマイグレーションによる断線
を抑制する為に、例えば、図３に示すように、絶縁膜２
１の上に窒化チタン膜２２，アルミニウム・シリコン合
金膜２３及びタングステン膜２４を順次積層してパター
ニングし、これらの表面にパッシベーション膜としてＢ
ＰＳＧ膜２５を被覆した配線が使用され、配線材料の積
層化や配線材料のアルミニウム合金化、配線材料を構成
している元素の結晶粒径を大きく成長させる等の対策が
行われている。2. Description of the Related Art In conventional semiconductor devices, aluminum has been widely used as a wiring material. However, with the miniaturization of semiconductor elements, the miniaturization of metal wiring has progressed, resulting in disconnection of wiring materials due to stress migration and electromigration. There is a problem. Therefore, in order to suppress disconnection due to stress migration or electromigration that occurs in the manufacturing process of the wiring portion and stress migration or electromigration that occurs when the metal wiring and its contact hole portion are energized, for example, as shown in FIG. As shown, insulating film 2
1, a titanium nitride film 22, an aluminum-silicon alloy film 23, and a tungsten film 24 are sequentially laminated and patterned, and B is formed as a passivation film on these surfaces.
Wiring covered with the PSG film 25 is used, and measures are taken such as stacking the wiring material, making the wiring material into an aluminum alloy, and increasing the crystal grain size of the elements constituting the wiring material.
【０００３】[0003]
【発明が解決しようとする課題】この従来の半導体装置
の配線は、製造工程が複雑で、製造工程数が多くなると
いった問題がある。そのうえ、上記の方法を用いてもス
トレスマイグレーションやエレクトロマイグレーション
による断線を完全に無くすことはできないという問題が
あった。The wiring of the conventional semiconductor device has a problem that the manufacturing process is complicated and the number of manufacturing processes increases. Moreover, there is a problem in that even if the above method is used, it is not possible to completely eliminate disconnection due to stress migration or electromigration.
【０００４】本発明の目的は、ストレスマイグレーショ
ンやエレクトロマイグレーションによる断線をほぼ完全
に無くすことのできる半導体装置及びその製造方法を提
供することにある。An object of the present invention is to provide a semiconductor device capable of almost completely eliminating disconnection due to stress migration or electromigration, and a manufacturing method thereof.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に設けた第１の絶縁膜と、前記第１の絶縁
膜に設けた接続孔と、前記接続孔の底部に露出する下層
の導電層の表面に設けた第１のバリアメタル膜と、前記
第１のバイアメタル膜上の前記接続孔内に充填して設け
た水銀又は水銀合金膜と、前記接続孔の上面に設けて前
記水銀又は水銀合金膜を接続孔内に密閉する第２のバリ
アメタル膜と、前記第２のバリアメタル膜を含む表面に
設けた第２の絶縁膜と、前記第２のバリアメタル膜上を
含む前記第２の絶縁膜に設けた配線形成用の溝と、前記
構内に充填して設けた水銀又は水銀合金膜からなる配線
と、前記配線を含む表面に設けて配線を溝内に密閉する
第３の絶縁膜とを有する。According to the present invention, there is provided a semiconductor device comprising:
A first insulating film provided on a semiconductor substrate; a connection hole provided in the first insulating film; and a first barrier metal film provided on the surface of a lower conductive layer exposed at the bottom of the connection hole. A mercury or mercury alloy film filled in the connection hole on the first via metal film, and a mercury or mercury alloy film provided on the upper surface of the connection hole to seal the mercury or mercury alloy film in the connection hole Barrier metal film, a second insulating film provided on the surface including the second barrier metal film, and a groove for forming a wiring provided on the second insulating film including on the second barrier metal film And a wiring made of mercury or a mercury alloy film filled in the premises, and a third insulating film provided on the surface including the wiring and sealing the wiring in the groove.
【０００６】本発明の半導体装置の製造方法は、半導体
基板上の導電層の表面に第１のバリアメタル膜を形成し
た後第１の絶縁膜および接続孔を形成する工程もしくは
半導体基板上に設けた第１の絶縁膜に接続孔を形成し前
記接続孔の底部に露出する下層の導電層の表面に第１の
バリアメタル膜を形成する工程と、前記半導体基板を冷
却し前記接続孔を含む表面に蒸着法により固体状の水銀
又は水銀合金膜を堆積し前記接続孔内に充填する工程
と、冷却されて固体状の前記水銀又は水銀合金膜の表面
をイオンビームスパッタエッチングによりエッチバック
して前記接続孔内にのみ水銀又は水銀合金膜を残して埋
込む工程と、冷却されて固体状の前記水銀又は水銀合金
膜を含む表面に電子線蒸着法により第２のバリアメタル
膜を堆積してパターニングし、前記接続孔内に水銀又は
水銀合金膜を密閉する工程と、前記第２のバリアメタル
膜を含む表面に高周波マグネトロンスパッタ法により低
温で第２の絶縁膜を堆積する工程と、前記第２の絶縁膜
をパターニングして配線形成用の溝を形成し且つ前記第
２のバリアメタル膜の上面を露出させる工程と、前記半
導体基板を冷却し前記溝を含む表面に蒸着法で固体状の
水銀又は水銀合金膜を堆積して前記溝内に充填する工程
と、冷却されて固体状の前記水銀又は水銀合金膜の表面
をエッチバックし前記溝内にのみ埋込む工程と、冷却さ
れて固体状の前記水銀又は水銀合金膜を含む表面に低温
で第３の絶縁膜を堆積し前記下層の導電層と電気的に接
続された配線を形成する工程とを含んで構成される。According to the method of manufacturing a semiconductor device of the present invention, a first barrier metal film is formed on the surface of a conductive layer on a semiconductor substrate.
Or a step of forming a first insulating film and a connection hole after
Before forming the connection hole in the first insulating film provided on the semiconductor substrate
The first conductive layer is formed on the surface of the lower conductive layer exposed at the bottom of the connection hole.
Forming a barrier metal film; cooling the semiconductor substrate; depositing a solid mercury or mercury alloy film on the surface including the contact hole by a vapor deposition method and filling the film in the contact hole; A step of etching back the surface of the mercury or mercury alloy film in a solid state by ion beam sputter etching to leave the mercury or mercury alloy film only in the connection hole, and the solid mercury or mercury alloy cooled. A step of depositing and patterning a second barrier metal film on the surface including the film by an electron beam evaporation method, and sealing the mercury or mercury alloy film in the connection hole; A step of depositing a second insulating film at a low temperature by a high-frequency magnetron sputtering method, patterning the second insulating film to form a groove for forming a wiring, and the second barrier metal film Exposing the upper surface; cooling the semiconductor substrate; depositing a solid mercury or mercury alloy film on the surface including the groove by vapor deposition to fill the groove; and cooling the semiconductor in the solid state. A step of etching back the surface of the mercury or mercury alloy film and burying it only in the groove; and depositing a third insulating film at a low temperature on the surface containing the cooled mercury or mercury alloy film in a solid state, And a step of forming a wiring electrically connected to the conductive layer.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００８】図１（ａ）〜（ｄ）及び図２（ａ）〜
（ｃ）は本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図である。1A to 1D and 2A to 2D.
(C) is sectional drawing of the semiconductor chip shown in order of process for demonstrating the manufacturing method of one Example of this invention.
【０００９】まず、図１（ａ）に示すように、Ｓｉ基板
１の表面に電子線蒸着法によりＴｉ膜を０．１μｍの厚
さに堆積してパターニングし、第１のバリアメタル膜２
を形成する。次に、バリアメタル膜２を含む表面にＣＶ
Ｄ法により、ＳｉＯ2 膜３を１μｍの厚さに堆積して選
択的に異方性エッチングし、口径が約０．８μｍのコン
タクトホール４を形成する。First, as shown in FIG. 1A, a Ti film having a thickness of 0.1 μm is deposited on the surface of a Si substrate 1 by an electron beam evaporation method and patterned to form a first barrier metal film 2
To form. Next, CV is formed on the surface including the barrier metal film 2.
By the method D, the SiO 2 film 3 is deposited to a thickness of 1 μm and selectively anisotropically etched to form the contact hole 4 having a diameter of about 0.8 μm.
【００１０】次に、図１（ｂ）に示すように、同一真空
容器内にそれぞれ独立に取付けたボート内でＨｇを２０
℃（蒸気圧１０-1Ｐａ）に、Ａｕを１１００℃（蒸気圧
１０-2Ｐａ）にそれぞれ加熱して蒸発させ、−４０℃に
冷却したＳｉ基板１のコンタクトホール４を含む表面に
Ｈｇ中にＡｕを０．１３ｗｔ％含む固体状の水銀合金膜
５を堆積させる。このとき、水銀合金膜５はコンタクト
ホール４内の段差部で段差被覆性が悪くなることがあ
る。Next, as shown in FIG. 1 (b), Hg is set to 20 in a boat independently mounted in the same vacuum container.
Au at 1100 ° C (vapor pressure 10 -2 Pa) to evaporate at ℃ (vapor pressure 10 -1 Pa) and cooled to -40 ° C on the surface including the contact holes 4 of the Si substrate 1 in Hg. A solid mercury alloy film 5 containing 0.13 wt% of Au is deposited on. At this time, the step coverage of the mercury alloy film 5 may deteriorate at the step in the contact hole 4.
【００１１】次に、図１（ｃ）に示すように、基板を−
３０℃まで加熱してコンタクトホール４内の水銀合金膜
５を流動させ段差被覆を改善させた後、再度基板を−４
０℃まで冷却して固体化し、コンタクトホール４を含む
表面に水銀合金膜を更に追加して堆積し、表面を平坦化
する。Next, as shown in FIG. 1C, the substrate is
After heating to 30 ° C. to flow the mercury alloy film 5 in the contact hole 4 to improve the step coverage, the substrate is again placed at −4.
It is cooled to 0 ° C. to be solidified, and a mercury alloy film is further added and deposited on the surface including the contact holes 4 to flatten the surface.
【００１２】次に、図１（ｄ）に示すように、ガス圧１
×１０-2ＰａのＡｒガスをエッチングガスとして用い加
速電圧５００ｅＶ、ビーム電流１ｍＡ／ｃｍ2 のイオン
ビームスパッタエッチングにより水銀合金膜５の全面を
エッチバックしてＳｉＯ2 膜３の上面がちょうど露出し
た時点でエッチングを停止しコンタクトホール４内にの
み水銀合金膜５を埋込む。次に、基板を−４０℃に冷却
して水銀合金膜５を固体状態にした状態で水銀合金膜５
を含む表面にＴｉ膜を電子線蒸着法で０．１μｍの厚さ
に堆積し、パターニングして第２のバリアメタル膜６を
形成し、水銀合金膜５をコンタクトホール４内に密閉す
る。Next, as shown in FIG. 1D, the gas pressure 1
The entire surface of the mercury alloy film 5 was etched back by ion beam sputter etching with an acceleration voltage of 500 eV and a beam current of 1 mA / cm 2 using Ar gas of × 10 -2 Pa as an etching gas, and the upper surface of the SiO 2 film 3 was just exposed. At this point, the etching is stopped and the mercury alloy film 5 is embedded only in the contact hole 4. Then, the substrate is cooled to -40 ° C. to make the mercury alloy film 5 in a solid state, and then the mercury alloy film 5 is formed.
A Ti film is deposited to a thickness of 0.1 μm on the surface including P by an electron beam evaporation method, patterned to form a second barrier metal film 6, and the mercury alloy film 5 is sealed in the contact hole 4.
【００１３】次に、図２（ａ）に示すように、高周波電
力４ｋＷ．ガス圧１０-1ＰａのＡｒイオンによりＳｉＯ
2 ターゲットをスパッタし、基板温度５０℃でバリアメ
タル膜６を含む表面にＳｉＯ2 膜７を厚さ０．５μｍの
厚さに堆積する。次に、ＳｉＯ2 膜７をイオンビームス
パッタエッチングにより選択的にエッチングしてバリア
メタル膜６上のＳｉＯ2 膜７に配線形成用の幅１〜２μ
ｍの溝８を形成する。Next, as shown in FIG. 2A, high frequency power of 4 kW. SiO by Ar ions with a gas pressure of 10 -1 Pa
2 A target is sputtered, and a SiO 2 film 7 is deposited to a thickness of 0.5 μm on the surface including the barrier metal film 6 at a substrate temperature of 50 ° C. Next, the SiO 2 film 7 is selectively etched by ion beam sputter etching, and the SiO 2 film 7 on the barrier metal film 6 has a wiring width of 1 to 2 μm.
A groove 8 of m is formed.
【００１４】次に、図２（ｂ）に示すように、溝８を含
む表面に水銀合金膜５の形成方法と同様の工程で水銀合
金膜９を堆積して表面を平坦化する。Next, as shown in FIG. 2B, a mercury alloy film 9 is deposited on the surface including the groove 8 in the same step as the method of forming the mercury alloy film 5 to flatten the surface.
【００１５】次に、図２（ｃ）に示すように、基板を−
４０℃に冷却した状態で水銀合金膜９の表面をエッチバ
ックしてＳｉＯ2 膜７の上面を露出させ、水銀合金膜９
を溝８内にのみ埋込む。次に、基板温度を−４０℃に保
った状態で水銀合金膜９を含む表面に高周波マグネトロ
ンスパッタによりＳｉＯ2 膜１０を堆積して水銀合金膜
９を溝８内に密閉し、コンタクトホール４の水銀合金膜
５を介してＳｉ基板１と電気的に接続する配線を形成す
る。Next, as shown in FIG. 2C, the substrate is-
While being cooled to 40 ° C., the surface of the mercury alloy film 9 is etched back to expose the upper surface of the SiO 2 film 7,
Is embedded only in the groove 8. Next, with the substrate temperature kept at -40 ° C., a SiO 2 film 10 is deposited on the surface including the mercury alloy film 9 by high-frequency magnetron sputtering, the mercury alloy film 9 is sealed in the groove 8, and the contact hole 4 is formed. Wiring that is electrically connected to the Si substrate 1 through the mercury alloy film 5 is formed.
【００１６】このように構成した半導体装置は、動作状
態において接続孔及び溝内に密閉されて形成された配線
の水銀合金膜が液体状になっており、従って、液体の持
つ流動性によって本質的にストレスマイグレーションや
エレクトロマイグレーションを発生せず、これらに起因
する断線を完全に防ぐことが可能になる。In the semiconductor device configured as described above, the mercury alloy film of the wiring formed in the contact hole and the groove in an operating state is in a liquid state. Stress migration and electromigration do not occur, and it is possible to completely prevent disconnection due to these.
【００１７】なお、本実施例では、半導体基板に接続す
る配線の例について説明したが、下層配線に接続する上
層配線を形成する場合にも適用でき、これらの工程を繰
返すことによって多層配線を構成することができる。In this embodiment, the example of the wiring connected to the semiconductor substrate has been described, but the present invention can be applied to the case of forming the upper layer wiring connected to the lower layer wiring, and the multilayer wiring is formed by repeating these steps. can do.
【００１８】さらに、本実施例では半導体基板上の導電
層の表面に第１のバリアメタル膜を形成した後第１の絶
縁膜および接続孔を形成する工程を含む製造方法につい
て説明したが、半導体基板上に設けた第１の絶縁膜に接
続孔を形成し前記接続孔の底部に露出する下層の導電層
の表面に第１のバリアメタル膜を形成する工程を用いて
も本実施例と同様な効果が得られる。また、配線材とし
て水銀合金の代りにＨｇを使用しても良く、同様の効果
が得られる。 Further, in this embodiment, the conductivity on the semiconductor substrate is
After forming the first barrier metal film on the surface of the layer, the first insulating film is formed.
A manufacturing method including a step of forming an edge film and a connection hole is described.
As described above, contacting the first insulating film provided on the semiconductor substrate
A lower conductive layer that forms a continuous hole and is exposed at the bottom of the connection hole
Using the process of forming the first barrier metal film on the surface of
Also, the same effect as in this embodiment can be obtained. Further, Hg may be used as the wiring material instead of the mercury alloy, and the same effect can be obtained.
【００１９】[0019]
【発明の効果】以上説明したように本発明は、水銀又は
水銀合金を配線材として用いることにより、半導体装置
の動作状態で液体状の配線を実現でき、ストレスマイグ
レーションやエレクトロマイグレーションに起因する断
線をほぼ完全に防止することができるという効果を有す
る。As described above, according to the present invention, by using mercury or a mercury alloy as a wiring material, it is possible to realize a liquid wiring in an operating state of a semiconductor device and to prevent disconnection due to stress migration or electromigration. It has an effect that it can be almost completely prevented.
【図１】本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【図２】本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図。FIG. 2 is a sectional view of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【図３】従来の半導体装置の一例を示す半導体チップの
断面図。FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
１ Ｓｉ基板 ２，６ バリアメタル膜 ３，７，１０ ＳｉＯ2 膜 ４ コンタクトホール ５，９ 水銀合金膜 ８ 溝1 Si substrate 2, 6 Barrier metal film 3, 7, 10 SiO 2 film 4 Contact hole 5, 9 Mercury alloy film 8 Groove
Claims (3)
記第１の絶縁膜に設けた接続孔と、少なくとも 前記接続孔の底部に露出する下層の導電層の
表面に設けた第１のバリアメタル膜と、前記第１のバリ
アメタル膜上の前記接続孔内に充填して設けた水銀又は
水銀合金膜と、前記接続孔の上面に設けて前記水銀又は
水銀合金膜を接続孔内に密閉する第２のバリアメタル膜
と、前記第２のバリアメタル膜を含む表面に設けた第２
の絶縁膜と、前記第２のバリアメタル膜上を含む前記第
２の絶縁膜に設けた配線形成用の溝と、前記構内に充填
して設けた水銀又は水銀合金膜からなる配線と、前記配
線を含む表面に設けて配線を溝内に密閉する第３の絶縁
膜とを有することを特徴とする半導体装置。1. A first insulating film provided on a semiconductor substrate, a connection hole provided in the first insulating film, and a first insulating film provided on a surface of a lower conductive layer exposed at least at a bottom portion of the connection hole. The first barrier metal film and the first burr.
A mercury or mercury alloy film provided in the connection hole on the ametal film and a second barrier metal film provided on the upper surface of the connection hole to seal the mercury or mercury alloy film in the connection hole; A second layer provided on the surface including the second barrier metal film
An insulating film, a groove for forming a wiring provided in the second insulating film including on the second barrier metal film, a wiring made of mercury or a mercury alloy film filled in the premises, A third insulating film, which is provided on a surface including a wiring and seals the wiring in the groove, the semiconductor device.
アメタル膜を形成した後第１の絶縁膜および接続孔を形
成する工程と、前記半導体基板を冷却し前記接続孔を含
む表面に蒸着法により固体状の水銀又は水銀合金膜を堆
積し前記接続孔内に充填する工程と、冷却されて固体状
の前記水銀又は水銀合金膜の表面をイオンビームスパッ
タエッチングによりエッチバックして前記接続孔内にの
み水銀又は水銀合金膜を残して埋込む工程と、冷却され
て固体状の前記水銀又は水銀合金膜を含む表面に電子線
蒸着法により第２のバリアメタル膜を堆積してパターニ
ングし、前記接続孔内に水銀又は水銀合金膜を密閉する
工程と、前記第２のバリアメタル膜を含む表面に高周波
マグネトロンスパッタ法により低温で第２の絶縁膜を堆
積する工程と、前記第２の絶縁膜をパターニングして配
線形成用の溝を形成し且つ前記第２のバリアメタル膜の
上面を露出させる工程と、前記半導体基板を冷却し前記
溝を含む表面に蒸着法で固体状の水銀又は水銀合金膜を
堆積して前記溝内に充填する工程と、冷却されて固体状
の前記水銀又は水銀合金膜の表面をエッチバックし前記
溝内にのみ埋込む工程と、冷却されて固体状の前記水銀
又は水銀合金膜を含む表面に低温で第３の絶縁膜を堆積
し前記下層の導電層と電気的に接続された配線を形成す
る工程とを含むことを特徴とする半導体装置の製造方
法。2. A first burr on the surface of a conductive layer on a semiconductor substrate.
After forming the ametal film, form the first insulating film and the connection hole.
A step of cooling the semiconductor substrate, depositing a solid mercury or mercury alloy film on the surface including the connection hole by an evaporation method and filling the film into the connection hole, and cooling the solid mercury. Alternatively, a step of etching back the surface of the mercury alloy film by ion beam sputter etching to embed the mercury or mercury alloy film only in the connection hole, and a surface containing the mercury or mercury alloy film in a solid state when cooled. And patterning a second barrier metal film by electron beam vapor deposition on the surface of the contact hole and sealing the mercury or mercury alloy film in the connection hole, and a high frequency magnetron sputtering method on the surface including the second barrier metal film. A step of depositing a second insulating film at a low temperature, and patterning the second insulating film to form a trench for forming a wiring and exposing the upper surface of the second barrier metal film. The step of cooling the semiconductor substrate, depositing a solid mercury or mercury alloy film on the surface including the groove by vapor deposition and filling the groove in the groove, and cooling the solid mercury or mercury alloy in the solid state. A step of etching back the surface of the film and burying it only in the groove; and depositing a third insulating film at a low temperature on the surface containing the mercury or mercury alloy film in a solid state when cooled to electrically connect with the lower conductive layer. And a step of forming wirings that are electrically connected to each other.
アメタル膜を形成した後第１の絶縁膜および接続孔を形After forming the ametal film, form the first insulating film and the connection hole.
成する工程にかわって、半導体基板上に設けた第１の絶The first insulation layer provided on the semiconductor substrate instead of the process
縁膜に接続孔を形成し前記接続孔の底部に露出する下層A lower layer that forms a connection hole in the edge film and is exposed at the bottom of the connection hole
の導電層の表面に第１のバリアメタル膜を形成する工程Of forming a first barrier metal film on the surface of the conductive layer of
よりなることを特徴とする請求項２記載の半導体装置の3. The semiconductor device according to claim 2, wherein
製造方法。Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5078399A JP2546482B2 (en) | 1993-04-06 | 1993-04-06 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5078399A JP2546482B2 (en) | 1993-04-06 | 1993-04-06 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06291195A JPH06291195A (en) | 1994-10-18 |
| JP2546482B2 true JP2546482B2 (en) | 1996-10-23 |
Family
ID=13660953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5078399A Expired - Lifetime JP2546482B2 (en) | 1993-04-06 | 1993-04-06 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2546482B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3641342B2 (en) | 1997-03-07 | 2005-04-20 | Ｔｄｋ株式会社 | Semiconductor device and organic EL display device |
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1993
- 1993-04-06 JP JP5078399A patent/JP2546482B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06291195A (en) | 1994-10-18 |
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