JP3597379B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device manufacturing method and a semiconductor integrated circuit device technology, and more particularly, to an embedded wiring technology formed by embedding a wiring conductor film in a groove or a connection hole formed in an insulating film. And effective technology.
[0002]
[Prior art]
As a method for forming wiring in a semiconductor integrated circuit device, there is a process called a damascene method. According to this method, after a trench for forming a wiring is formed in an insulating film, a conductor film for forming a wiring is deposited on the entire surface of the semiconductor substrate, and the conductor film in a region other than the trench is chemically and mechanically polished (CMP). A method of forming a buried interconnect in a trench for forming an interconnect by removing the buried interconnect by chemical mechanical polishing. This method is particularly suitable as a method for forming an embedded wiring made of a copper-based conductor material (copper or copper alloy), which is difficult to perform fine etching.
[0003]
Further, there is a dual-damascene method as an application of the damascene method. In this method, after forming a groove for forming a wiring and a connection hole for connecting with a lower layer wiring in an insulating film, a conductor film for forming a wiring is deposited on the entire surface of the semiconductor substrate, and further, a region other than the groove is formed. By removing the conductive film by CMP, a buried wiring is formed in a wiring forming groove, and a plug is formed in a connection hole. In the case of this method, particularly in a semiconductor integrated circuit device having a multilayer wiring structure, the number of steps can be reduced, and the wiring cost can be reduced.
[0004]
The wiring forming technique using such a damascene method is described in, for example, (1). K. Abe et. al, in Extended Abstracts 1994 SSDM, pp937-940 (Oki Electric), (2). Valley M. Dubin et. al, in Proceedings 1997 VMIC, pp 69-74.
[0005]
The above-mentioned document (1) discloses a technique of forming a groove in an insulating film, depositing copper by a sputtering method, and further performing a heat treatment to satisfactorily fill the groove for forming a wiring. Further, the above-mentioned document (2) discloses a method in which copper is deposited by sputtering in grooves and connection holes formed in an insulating film, and then copper is buried by plating.
[0006]
Japanese Patent Application Laid-Open No. 8-78525 discloses a process of forming a connection hole such that a part of a semiconductor substrate is exposed in an insulating film attached on a semiconductor substrate, and forming a wiring layer on the insulating film. A general wiring forming technique of a semiconductor integrated circuit device including a step of forming by a sputtering method, a step of forming a metal layer on a wiring by a plating method, and a step of patterning the wiring layer and the metal layer is disclosed. .
[0007]
The technique described in this publication has a different application process from that of the present application which presupposes a damascene process, and applies plating to a low aspect connection hole having a relatively loose design rule. However, when applied to fine and high aspect ratio connection holes and damascene structures, the technology of the publication using a normal sputtering method has a low step coverage in the connection holes of the conductor film by the sputtering method. Even if it is applied, the conductor film for forming the wiring cannot be completely buried, and voids occur in the connection holes.
[0008]
[Problems to be solved by the invention]
However, the present inventor has found that the embedded wiring technology has the following problems with the miniaturization of wiring grooves and connection holes and the increase in aspect ratio.
[0009]
That is, it is difficult to embed the wiring groove or the connection hole by the sputtering method alone, the groove or the connection hole cannot be sufficiently buried, and the electric power is excellent in the buried wiring (including the wiring portion and the connection hole portion). Can not secure the proper characteristics.
[0010]
In addition, when the plating method is used, the embedding ability is high, but also in this case, a base metal film is required, and the embedding limit is determined by the coverage of the base metal film. And connection hole portions).
[0011]
An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film, It is an object of the present invention to provide a technique capable of satisfactorily embedding a conductive film for forming an embedded wiring.
[0012]
Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film, and to promote the miniaturization of the buried wiring. It is to provide the technology that can do it.
[0013]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0014]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0015]
That is, the present invention is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) forming a first conductive film made of copper or a conductive material containing copper on at least one of the wiring groove or the connection hole and on the insulating film, having directivity and particles of the first conductive film; Is deposited by physical vapor deposition under conditions that are difficult to scatter between the target and the semiconductor substrate,
(C) applying a second conductor film made of copper or a conductor material containing copper by a plating method after the formation of the first conductor film;
(D) forming a buried interconnect made of the first conductor film and the second conductor film in at least one of the interconnection groove and the connection hole by shaving the first conductor film and the second conductor film. Have
[0016]
Further, according to the present invention, the first conductive film contains at least one of platinum, palladium, nickel, chromium, gold or silver, or contains platinum, palladium, nickel, chromium, After depositing a third conductor film containing at least one of gold and silver, the second conductor film is deposited.
[0017]
Further, the present invention is to cool the semiconductor substrate before or during the deposition of the first conductor film.
[0018]
The present invention is also a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) During or during the deposition of a first conductor film made of copper or a conductor material containing copper on at least one of the wiring groove or the connection hole and on the insulation film by a physical vapor deposition method. Raising the temperature of the semiconductor substrate to move the first conductive film to the bottom of the wiring groove.
[0019]
The present invention is also a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) depositing a third conductor film containing at least one of platinum, palladium, nickel, chromium, gold or silver on at least one of the wiring groove or the connection hole and on the insulating film;
(C) applying a second conductor film made of copper or a conductor material containing copper by a plating method after the formation of the third conductor film;
(D) forming a buried interconnect made of the second conductor film and the third conductor film in at least one of the interconnection groove and the connection hole by shaving the second conductor film and the third conductor film. Have
[0020]
The present invention is also a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) forming a first conductive film made of copper or a conductive material containing copper on at least one of the wiring groove or the connection hole and on the insulating film by physical vapor deposition; Causing both the action and the etching action to take place;
(C) applying a second conductor film made of copper or a conductor material containing copper by a plating method after the formation of the first conductor film;
(D) forming a buried interconnect made of the first conductor film and the second conductor film in the wiring groove by shaving the first conductor film and the second conductor film.
[0021]
The following is a brief description of an outline of a typical one of the other means examined by the present inventors.
[0022]
That is, the means is a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) During or during the deposition of a first conductor film made of copper or a conductor material containing copper on at least one of the wiring groove or the connection hole and on the insulation film by a physical vapor deposition method. Raising the temperature of the semiconductor substrate later to move the first conductive film to the bottom of the wiring groove;
(C) After the step (b), at least one of copper, copper alloy, platinum, palladium, nickel, chromium, gold or silver is provided inside at least one of the wiring groove or the connection hole and on the first conductive film. Depositing a conductive film containing a by physical vapor deposition,
(D) after the step (c), applying a second conductive film made of copper or a conductive material containing copper by a plating method;
(E) After the step (d), the second conductor film and the first conductor film are shaved, and at least one of the wiring groove or the connection hole is filled with the first conductor film, the second conductor film, and the conductor film. And forming a built-in wiring. As a result, the aspect ratio of the wiring groove or the connection hole can be reduced, so that it is possible to satisfactorily embed the conductor film by the subsequent plating process.
[0023]
In addition, a conductive film made of copper or a copper alloy formed by a subsequent plating method can be satisfactorily applied by a catalytic action.
[0024]
Another means is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) During or during the deposition of a first conductor film made of copper or a conductor material containing copper on at least one of the wiring groove or the connection hole and on the insulation film by a physical vapor deposition method. Raising the temperature of the semiconductor substrate later to move the first conductive film to the bottom of the wiring groove;
(C) after the step (b), applying a second conductive film made of copper or a conductive material containing copper by a plating method;
(D) After the step (c), the second conductor film and the first conductor film are shaved, and at least one of the wiring groove and the connection hole is filled with the first conductor film, the second conductor film, and the conductor film. And forming a built-in wiring. As a result, the aspect ratio of the wiring groove or the connection hole can be reduced, so that it is possible to satisfactorily embed the conductor film by the subsequent plating process.
[0025]
Another means is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) During or during the deposition of a first conductor film made of copper or a conductor material containing copper on at least one of the wiring groove or the connection hole and on the insulation film by a physical vapor deposition method. Raising the temperature of the semiconductor substrate later to move the first conductive film to the bottom of the wiring groove;
(C) after the step (b), removing the first conductor film on the insulating film;
(D) After the step (c), copper or a second conductor film containing copper is selectively plated on the first conductor film left in the wiring groove by the step of removing the first conductor film by a plating method. Attaching step. As a result, the aspect ratio of the wiring groove or the connection hole can be reduced, so that it is possible to satisfactorily embed the conductor film by the subsequent plating process. Also, the embedded wiring can be formed without performing the conductor film removing step.
[0026]
Another means is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) depositing a first conductive film made of copper or a conductive material containing copper on at least one of the wiring groove or the connection hole and on the insulating film by a physical vapor deposition method;
(C) after the step (b), applying a second conductive film made of copper or a conductive material containing copper by a plating method;
(D) After the step (c), the second conductor film and the first conductor film are shaved, and at least one of the wiring groove and the connection hole is filled with the first conductor film, the second conductor film, and the conductor film. Forming a built-in wiring,
A step of performing a sputter etching process before or during the deposition of the first conductive film. Thereby, a taper is formed in the upper part of the wiring groove or the connection hole, so that the sputtered particles can easily reach the bottom of the wiring groove or the connection hole, or the first conductive film inside the wiring groove or the connection hole is re-sputtered. By doing so, step coverage can be improved.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Note that components having the same function are denoted by the same reference numerals throughout the drawings for describing the embodiments, and repetitive description thereof will be omitted.) Do).
[0028]
(Embodiment 1)
1 to 16 are cross-sectional views of a main part during a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 17 to 21 are explanatory diagrams for explaining setting of sputtering conditions of the present invention. 22 and 23 are enlarged cross-sectional views of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention during a manufacturing process, and FIGS. 49 and 50 illustrate defects at the time of forming embedded wiring studied by the present inventors. FIG.
[0029]
First, a method for manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.
[0030]
FIG. 1 is a cross-sectional view of a main part during a manufacturing process of a semiconductor integrated circuit device. As the semiconductor substrate 1, for example, an SOI substrate in which a semiconductor layer 1c for element formation is provided on a support substrate 1a via an insulating layer 1b is used.
[0031]
The support substrate 1a is made of, for example, silicon single crystal, and the insulating layer 1b is made of, for example, a silicon oxide film. The semiconductor layer 1c is made of, for example, p-type silicon single crystal, and a trench 2a extending from the main surface of the semiconductor layer 1c to the insulating layer 1b is dug in the element isolation region. An insulating film 2b made of, for example, a silicon oxide film is embedded in the trench 2a.
[0032]
In the semiconductor layer 1c, for example, an n-channel type MOSFET Q is formed. This MOS • FETQ has a pair of semiconductor regions 3a, a gate insulating film 3b, and a gate electrode 3c. For example, phosphorus or arsenic is introduced into the semiconductor layer 1c, and the pair of semiconductor regions 3a is set to be n-type. Note that the central semiconductor region 3a is a region shared by the adjacent MOSFETs Q.
[0033]
The gate insulating film 3b is made of, for example, a silicon oxide film. The gate electrode 3c is made of, for example, a single film of low-resistance polysilicon. However, the gate electrode 3c is not limited to a single film of low-resistance polysilicon and can be variously changed. For example, a so-called polycide structure in which a silicide film is formed on a low-resistance polysilicon film may be used. For example, a so-called polymetal structure in which a metal film such as tungsten is formed on a low-resistance polysilicon via a barrier metal film such as titanium nitride or tungsten nitride.
[0034]
The surface of the gate electrode 3c is covered with a cap insulating film 4a and a side wall 4b. The cap insulating film 4a and the side wall 4b are made of, for example, a silicon oxide film or a silicon nitride film. Note that by forming the cap insulating film 4a and the side walls 4b with a silicon nitride film and employing a selective etching process, the connection holes of the interlayer insulating film can be formed in a self-aligned manner.
[0035]
On the main surface of the semiconductor layer 1c, an interlayer insulating film 5a made of, for example, a silicon oxide film is applied. The interlayer insulating film 5a may be a coating film formed by an SOG (Spin On Glass) method, an organic film, a CVD oxide film doped with fluorine, a silicon nitride film, or a combination of various insulating films. A connection hole 6a is formed in the interlayer insulating film 5a such that a part of the semiconductor region 3a is exposed.
[0036]
First, in the first embodiment, as shown in FIG. 2, a barrier metal 7a is deposited on the upper surface of the interlayer insulating film 5a and in the connection hole 6a by a CVD method, a sputtering method, a plating method, or the like.
[0037]
The barrier metal 7a improves the adhesion between the interlayer insulating film 5a and the conductive film for forming the wiring, and suppresses the diffusion of the CVD source gas for forming the conductive film for forming the wiring, the constituent atoms of the conductive film, and silicon. It is made of other metals or compounds thereof, for example, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, titanium nitride silicide or tungsten nitride silicide.
[0038]
Subsequently, a conductor film 8a for forming a wiring which is relatively thicker than the barrier metal 7a is deposited on the barrier metal 7a by a CVD method or the like. Thereby, the connection hole 6a is buried. The conductor film 8a is made of, for example, tungsten or an alloy thereof.
[0039]
After that, by performing a CMP (Chemical Mechanical Polishing) process, the conductive film 8a and the barrier metal 7a are shaved until the upper surface of the interlayer insulating film 5a is exposed. Thereby, as shown in FIG. 3, a plug 9a composed of the barrier metal 7a and the conductor film 8a is formed in the connection hole 6a.
[0040]
Next, as shown in FIG. 5, an interlayer insulating film 5b made of, for example, a silicon oxide film or the like is deposited by a CVD method or the like, and after this is planarized, a wiring groove 10a is formed in the interlayer insulating film 5b by a photolithography technique. It is formed by a dry etching technique. The upper surface of the plug 9a is exposed at the bottom surface of the two left wiring grooves 10a in FIG. Further, the interlayer insulating film 5b may be formed in the same manner as the above-described interlayer insulating film 5a.
[0041]
The width of the wiring groove 10a is, for example, about 0.13 to 1.0 μm, and is not particularly limited. For example, about 0.25 μm, and the depth is, for example, about 0.15 to 1.0 μm. The wiring pitch is, for example, about 0.26 to 2.0 μm, and is not particularly limited, but is, for example, about 0.5 μm.
[0042]
Subsequently, as shown in FIG. 6, after a barrier metal (barrier conductor film) 7b is deposited on the upper surfaces of the interlayer insulating films 5a and 5b and in the wiring grooves 10a by a CVD method, a sputtering method, a plating method, or the like. As shown in FIG. 7, a conductive film (first conductive film) 8b made of, for example, copper or a copper alloy for forming a wiring is deposited on the barrier metal 7b by a sputtering method or the like.
[0043]
The function and constituent material of the barrier metal 7b are the same as those of the barrier metal 7a. The barrier metal 7b may not be required in some cases. The conductor film 8b for forming a wiring is a seed crystal layer of a conductor film to be deposited later by a plating method, and is deposited relatively thin so as not to fill the wiring groove 10a. The thickness of the conductor film 8b is, for example, about 500 to 1500 °.
[0044]
The sputtering process for depositing the conductor film 8b for forming the wiring is performed under such a condition that the incident angle of the sputtered particles to the wiring groove 10a is perpendicular or close to the value (directivity condition), and Is performed under such a condition that scattering between the main surface of the semiconductor substrate and the main surface (sputtering surface) of the target is difficult. The setting of the sputtering conditions will be described later in detail.
[0045]
By applying the conductor film 8b for forming a wiring under such conditions, the conductor film 8b is thinner and thinner in the wiring groove 10a with little or no overhang above the wiring groove 10a. Can be applied evenly. That is, the conductor film 8b can be applied with high step coverage. Note that the barrier metal 7b may be deposited under the same sputtering conditions.
[0046]
Further, for example, platinum, palladium, nickel, chromium, gold, silver or copper may be added to the barrier metal 7b. Further, for example, platinum, palladium, nickel, chromium, gold, or silver may be added to the conductor film 8b. Further, a thin conductive film made of, for example, platinum, palladium, nickel, chromium, gold, or silver may be formed on the upper surface (including the inside of the groove or the hole) of the conductive film 8b. By doing so, it becomes possible to satisfactorily apply a conductive film made of copper or a copper alloy by a subsequent plating method by a catalytic action. This method is particularly effective when using an electroless plating method.
[0047]
Thereafter, as shown in FIG. 8, a conductor film (second conductor film) 8c for forming a wiring made of, for example, copper or a copper alloy is applied on the conductor film 8b by a plating method or the like. Thereby, the fine wiring trench 10a having a high aspect ratio can be sufficiently buried.
[0048]
In this case, the plating method may be any of an electrolytic plating method, an electroless plating method, and a combination thereof (in this case, electroplating is basically performed after the electroless plating). On the upper surface of the interlayer insulating film 5b (a flat region other than the groove and the hole), the thickness of the conductor film 8c is larger than the thickness of the conductor film 8b. The thickness of the conductor film 8c is, for example, about 0.5 to 1.0 μm.
[0049]
Next, by performing a CMP process, the conductor films 8c and 8b and the barrier metal 7b are shaved until the upper surface of the interlayer insulating film 5b is exposed. As a result, as shown in FIG. 9, a buried wiring 11a composed of the barrier metal 7b and the conductor films 8b and 8c is formed in the wiring groove 10a. The buried wiring 11a extends in a direction perpendicular to the plane of FIG.
[0050]
Subsequently, as shown in FIG. 10, a barrier insulating film 12 made of, for example, a silicon nitride film or the like is deposited on the interlayer insulating film 5b and the embedded wiring 11a by a CVD method or the like. As shown, an interlayer insulating film 5c made of, for example, a silicon oxide film is deposited by a CVD method or the like. Note that the interlayer insulating film 5c may be formed in the same manner as the above-described interlayer insulating film 5a.
[0051]
Thereafter, a wiring groove 10b is formed on the interlayer insulating film 5c by a photolithography technique and a dry etching technique, and then reaches the buried wiring 11a from the bottom of the wiring groove 10b as shown in FIG. Is formed by photolithography and dry etching.
[0052]
The dimensions and the wiring pitch of the wiring groove 10b are the same as those of the wiring groove 10a. The diameter of the connection hole 6b is, for example, about 0.13 to 1.0 μm, and is not particularly limited, but is, for example, about 0.25 μm, and its depth is, for example, about 0.15 to 2.0 μm, but is not particularly limited. For example, it is about 0.6 μm.
[0053]
In forming the connection hole 6b, an etching process is performed under conditions that increase the etching selectivity between the silicon oxide film and the silicon nitride film. That is, first, the silicon oxide film is etched under the condition that the silicon oxide film is more easily etched than the silicon nitride film, and then, when the barrier insulating film 12 made of the silicon nitride film is exposed from the bottom of the connection hole 6b, the etching condition is changed. The etching process is performed under the condition that the silicon nitride film is more easily etched than the silicon oxide film. Thereby, it is possible to prevent the buried wiring 11a from being removed when the connection hole 6b is formed.
[0054]
Next, as shown in FIG. 13, after a barrier metal (barrier conductor film) 7b is deposited on the upper surface of the interlayer insulating film 5c, the wiring groove 10b and the connection hole 6b by a CVD method, a sputtering method, a plating method, or the like. As shown in FIG. 14, a conductor film (first conductor film) 8b made of, for example, copper or a copper alloy for forming a wiring is deposited on the barrier metal 7b by a sputtering method or the like.
[0055]
The function and constituent material of the barrier metal 7b are the same as those of the barrier metal 7a. The conductor film 8b for forming a wiring is a seed crystal layer of a conductor film to be deposited later by a plating method, and is deposited relatively thin so as not to fill the connection hole 6b and the wiring groove 10b. The thickness of the conductor film 8b is, for example, about 500 to 1500 °.
[0056]
The sputtering process for depositing the wiring-forming conductor film 8b is performed under conditions (directivity conditions) such that the incident angle of the sputtered particles with respect to the wiring groove 10b is perpendicular or a value close thereto. Is performed under such a condition that scattering between the main surface of the semiconductor substrate and the main surface (sputtering surface) of the target is difficult. The setting of the sputtering conditions will be described later in detail.
[0057]
By depositing the conductor film 8b for wiring formation under such conditions, the conductor film 8b is formed in the connection hole 6b and the wiring groove 10b with little or no overhang above the wiring groove 10b. It can be applied in a thin and even state. That is, the conductor film 8b can be applied with high step coverage. The barrier metal 7b may be applied under the same sputtering conditions.
[0058]
Also here, for example, platinum, palladium, nickel, chromium, gold, silver or copper may be added to the barrier metal 7b. Further, for example, platinum, palladium, nickel, chromium, gold or silver may be added to the conductor film 8b. Further, a thin conductive film made of, for example, platinum, palladium, nickel, chromium, gold, or silver may be formed on the upper surface (including the inside of the groove or the hole) of the conductive film 8b. By doing so, it becomes possible to satisfactorily apply a conductive film made of copper or a copper alloy by a subsequent plating method by a catalytic action. This method is particularly effective when using an electroless plating method.
[0059]
Thereafter, as shown in FIG. 15, a conductor film (second conductor film) 8c for forming a wiring made of, for example, copper or a copper alloy is deposited on the conductor film 8b by a plating method or the like. Thereby, the fine connection holes 6b and the wiring grooves 10b having a high aspect ratio can be sufficiently buried. In this case, the plating method may be any of an electrolytic plating method, an electroless plating method, and a combination thereof (in this case, electroplating is basically performed after the electroless plating). The thickness of the conductor film 8c is, for example, about 0.5 to 1.0 μm.
[0060]
Next, by performing a CMP process, the conductor films 8c and 8b and the barrier metal 7b are shaved until the upper surface of the interlayer insulating film 5c is exposed. As a result, as shown in FIG. 16, a buried wiring 11b including the barrier metal 7b and the conductor films 8b and 8c is formed in the connection hole 6b and the wiring groove 10b.
[0061]
The portion inside the wiring groove 10b of the embedded wiring 11b extends in a direction perpendicular to the plane of the paper of FIG. The portion inside the connection hole 6b of the embedded wiring 11b does not extend in the direction perpendicular to the plane of FIG. 16, but extends in the vertical direction in FIG. 16 to electrically connect the embedded wirings 11a and 11b. Connected to
[0062]
Next, after describing a problem in a case where a conductor film is deposited in a groove or a hole by a sputtering method, a technique of setting the sputtering conditions of the conductor film 8b for forming a wiring will be described.
[0063]
FIG. 49 is a cross-sectional view of the wiring groove 51 formed in the interlayer insulating film 50 when the film is formed by a normal sputtering method that does not have the above-described directivity and does not consider scattering of sputtered particles. I have.
[0064]
On the upper surface of the interlayer insulating film 50 and the surface of the wiring groove 51, a barrier metal 52 made of, for example, titanium nitride or the like is adhered. When the conductor film 53 made of copper or a copper alloy or the like is deposited by using the above-mentioned ordinary sputtering method, copper or copper alloy particles cannot enter the wiring groove 51, and the conductor film 53 is formed on the inner surface of the wiring groove 51. In this case, a discontinuous portion or insufficient coverage may occur, the coverage of the conductor film 53 may be insufficient at the bottom of the wiring groove 51, or the overhang due to the conductor film 53 above the wiring groove 51 may increase.
[0065]
In such a state, as shown in FIG. 50, when a conductive film 54 made of copper or a copper alloy is applied by plating, voids are formed on the inner surface of the wiring groove 51 due to the discontinuity and insufficient coverage described above. Or a large void is formed at the center of the wiring groove 51 due to the overhang described above. Such a problem similarly occurs not only in the wiring groove 51 but also in the connection hole and the like.
[0066]
Thus, in the present embodiment, the conductor film 8b is deposited under the following sputtering conditions.
[0067]
The first means will be described with reference to FIG. The condition here is that the distance TS between the main surface (sputtering surface) of the target TG and the main surface of the semiconductor substrate 1 in the sputtering apparatus is the sum of the effective radius R1 of the target TG and the radius R2 of the semiconductor substrate 1. At least the value obtained by dividing by the square root of 3, and the mean freedom of the sputtered particles of the conductor film 8b during discharge. line The length L1 = TS / COS (arctan (R1 + R2) / TS ) Less It is to be on.
[0068]
Thus, when the direction perpendicular to the main surface of the semiconductor substrate 1 is set to zero (0) degrees, the maximum angle of the angle at which the sputtered particles enter the semiconductor substrate 1 is limited to 30 degrees or less. By limiting the incident angle to about 30 degrees or less, it becomes possible for the sputtered particles that fly without scattering to reach the bottom center of a hole (or groove) with an aspect ratio of 1 with a probability of 100%. . In addition, it reaches the bottom corner of the hole (or groove) having the aspect ratio = 2 with a probability of 50%.
[0069]
Note that the incident angle is preferably strictly 26.6 degrees or less. In this case, the effect is obtained even at 30 degrees. Conversely, if the angle is 30 degrees, the sputtered particles for the aspect ratio of 0.87 are 100% at the center of the bottom of the hole (or groove), and the sputtered particles are for the aspect ratio of 1.73. It can be reached with a 50% probability around the bottom of the hole (or groove).
[0070]
Although not particularly limited, the TS in this case is, for example, about 300 mm, R1 is, for example, about 125 mm, R2 is, for example, about 62.5 mm, the pressure is, for example, about 0.025 Pa, and (R1 + R2) is The value divided by the square root of 3 is, for example, about 108 mm. Therefore, TS / COS (arctan ((R1 + R2) / TS)) is, for example, about 350 mm, and the mean free path is, for example, about 470 mm.
[0071]
The second means will be described with reference to FIGS. The condition here is that the distance TS between the main surface (sputtering surface) of the target TG and the semiconductor substrate 1 in the sputtering apparatus is equal to or larger than the radius (or diameter) of the semiconductor substrate 1.
[0072]
Here, in FIG. 18, when the direction perpendicular to the main surface of the semiconductor substrate 1 is set to zero (0) degrees, the maximum angle of the angle at which the sputtered particles enter the semiconductor substrate 1 is 30 degrees or less. Restrict to Thereby, the same effect as the first means is obtained.
[0073]
Here, the incident angle is preferably strictly set to 26.6 degrees or less, but is set to about 30 degrees or less for the same reason as described above. Conversely, if the angle is 30 degrees, the sputtered particles can reach 100% at the center of the bottom of the hole (or groove) and 50% at the periphery with respect to the aspect ratio of 0.87 / 1.73. it can.
[0074]
FIG. 19 shows a case where radius R1 = radius R2, and the incident angle is limited to be 45 degrees or less. By restricting the incident angle to about 45 degrees or less, it is possible for the sputtered particles that fly without scattering to reach the center of the bottom of the hole (or groove) with an aspect ratio of 0.5 with a probability of 100%. it can. In addition, it is possible to reach the corner of a hole (or groove) having an aspect ratio of 1 with a probability of 50%.
[0075]
Although not particularly limited, the TS in this case is, for example, about 170 mm, R1 is, for example, about 125 mm, R2 is, for example, about 62.5 mm, the pressure is, for example, about 0.025 Pa, and the diameter of the semiconductor substrate 1 is, For example, about 125 mm, and the mean free path is, for example, about 470 mm.
[0076]
The third means will be described with reference to FIGS. The condition here is that the distance between the main surface (sputtering surface) of the target TG and the semiconductor substrate 1 in the sputtering apparatus is equal to or larger than the diameter of the semiconductor substrate 1 × 2.
[0077]
Here, in FIG. 20, when the direction perpendicular to the main surface of the semiconductor substrate 1 is set to zero (0) degrees, the maximum angle at which the sputtered particles enter the semiconductor substrate 1 is 14 degrees or less. Restrict to By restricting the incident angle to about 14 degrees or less, the sputtered particles mainly fly from the center of the target TG to the main surface of the semiconductor substrate 1, and the non-scattered sputtered particles are formed into holes (with an aspect ratio = 2). Alternatively, it is possible to reach the bottom central portion of the groove with a probability of 100%. Also, it reaches the bottom corner of a hole (or groove) having an aspect ratio = 4 with a probability of 50%.
[0078]
In FIG. 21, the incident angle is limited to 30 degrees or less. Thereby, the same effect as the first means is obtained.
[0079]
The incident angle is preferably strictly 26.6 degrees or less, but is set to about 30 degrees or less for the same reason as described above. Conversely, if the angle is 30 degrees, the sputtered particles can reach 100% at the center of the bottom of the hole (or groove) and 50% at the periphery with respect to the aspect ratio of 0.87 / 1.73. it can.
[0080]
Further, although not particularly limited, TS, R1, R2, pressure, mean free path, and the like in this case are the same as those of the first means.
[0081]
As a fourth means, the pressure in the sputtering chamber is reduced during the sputtering process for applying the conductor film 8b (see FIG. 7 and the like). In the present embodiment, although not particularly limited, the pressure in the sputtering chamber is, for example, 0.1 Pa or less, preferably about 0.025 Pa when the TS is 300 mm. As a result, the scattering of sputtered particles can be further suppressed. In addition, it can be applied evenly. That is, the conductor film 8b can be applied with high step coverage.
[0082]
As a fifth means, in combination with at least one of the above-described first to fourth means, the semiconductor substrate 1 is cooled before or during the sputtering processing for applying the conductor film 8b. In the present embodiment, although not particularly limited, the temperature of the semiconductor substrate 1 is, for example, 30 ° C. or lower, preferably 0 ° C. Thus, the copper or copper alloy forming the conductor film 8b is in a solid state and the aggregation of the copper or copper alloy can be suppressed, so that the formation of a discontinuous portion in the conductor film 8b is suppressed. It is possible to do.
[0083]
FIG. 22 is a sectional view showing a case where the conductor film 8b is applied by the above-described means or a combination thereof. The conductor film 8b is thinly and uniformly applied in the wiring groove 10a. That is, a discontinuous portion of the conductor film 8b is not formed on the inner side surface (arrow A) and the bottom surface (arrow B) of the wiring groove 10a, and insufficient coverage does not occur. Also, no remarkable overhang is formed at the upper part (arrow C) of the wiring groove 10a.
[0084]
FIG. 23 shows a state in which a conductor film 8c made of copper or a copper alloy or the like is applied by plating in such a state. The inside of the wiring groove 10a is filled with the conductor film 8c, and no void is generated. Therefore, the incidence of embedded wiring failure can be significantly reduced, and the yield and reliability of the semiconductor integrated circuit device can be improved.
[0085]
As described above, according to the present embodiment, the following effects can be obtained.
[0086]
(1). The conductor films 8b and 8c can be filled without generating voids in the fine wiring grooves 10a and 10b or the connection holes 6b.
[0087]
(2). According to the above (1), it is possible to improve the setting accuracy of the electric resistance of the embedded wirings 11a and 11b.
[0088]
(3). For example, platinum, palladium, nickel, chromium, gold, silver, or copper is added to the barrier metal 7b. For example, platinum, palladium, nickel, chromium, gold, or silver is added to the conductive film 8b. To form a thin conductive film made of, for example, platinum, palladium, nickel, chromium, gold or silver, so that a conductive film 8c made of copper or a copper alloy can be satisfactorily deposited by a subsequent plating method. Becomes possible. Thus, the conductor films 8b and 8c can be filled without generating voids in the fine wiring grooves 10a and 10b or the connection holes 6b.
[0089]
(4). According to the above (1), (2) or (3), the occurrence rate of defects in the buried wirings (including the connection holes) 11a and 11b can be reduced, so that the yield and reliability of the semiconductor integrated circuit device can be improved. Becomes possible.
[0090]
(5). According to the above (1), miniaturization of the wiring grooves 10a, 10b or the connection holes 6b can be promoted. For this reason, the degree of element integration can be improved, and miniaturization and high functionality of the semiconductor integrated circuit device can be promoted.
[0091]
(Embodiment 2)
24 to 29 are main-portion cross-sectional views of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step.
[0092]
FIG. 24 shows the formation of a wiring groove 10a (or a wiring groove 10b, a connection hole 6b; hereinafter, typically represented by a wiring groove 10a) in an interlayer insulating film 5b (or an interlayer insulating film 5c; hereinafter, represented by an interlayer insulating film 5b). FIG.
[0093]
As shown in FIG. 25, a conductor film 8b1 made of, for example, copper or a copper alloy is formed on such an interlayer insulating film 5b by a sputtering method. In the second embodiment, the conductor film 8b1 is formed as a target film. The film forming process is interrupted when the film value has not been reached. In this case, the sputtering method may be a sputtering method with the sputtering conditions of the first embodiment added, or a normal sputtering method without the sputtering conditions. Note that the barrier metal described above may be applied prior to the application of the conductor film 8b1.
[0094]
Subsequently, heat treatment is performed while the upper portion of the wiring groove 10a remains open, so that the conductor film 8b1 on the inner side surface of the wiring groove 10a is caused to flow to the bottom of the wiring groove 10a as shown in FIG. The conductor film 8b on the inner surface of 10a is divided.
[0095]
Further, a conductor film 8b1 having a predetermined thickness is deposited on the bottom of the wiring groove 8b. Thereby, the wiring groove 10a can be made shallow. That is, since the aspect ratio of the wiring groove 10a can be reduced, the wiring groove 10a can be satisfactorily embedded with a conductive film formed by a subsequent plating method.
[0096]
Thereafter, by restarting the process of forming a conductive film made of copper or a copper alloy by the above-described sputtering method, the conductive film 8b2 is coated on the upper surface of the conductive film 8b1 and the side surfaces of the wiring groove 10a as shown in FIG. To wear.
[0097]
Also here, for example, platinum, palladium, nickel, chromium, gold, silver or copper may be added to the barrier metal. Also, for example, platinum, palladium, nickel, chromium, or the like may be added to the conductor film 8b2. Gold or silver may be added. Further, the conductor film 8b2 may be formed of a thin conductor film made of, for example, platinum, palladium, nickel, chromium, gold, or silver. By doing so, it becomes possible to satisfactorily apply a conductive film made of copper or a copper alloy by a subsequent plating method by a catalytic action. This method is particularly effective when using an electroless plating method.
[0098]
Thereafter, as shown in FIG. 28, a conductor film 8c is deposited on the conductor film 8b2 by plating or the like as in the first embodiment. Thereby, the fine wiring trench 10a having a high aspect ratio can be sufficiently buried. Note that on the upper surface of the interlayer insulating film 5b (substantially flat region other than the grooves and holes), the thickness of the conductor film 8c is larger than the sum of the thicknesses of the conductor films 8b1 and 8b2.
[0099]
Next, the conductor films 8c, 8b2, and 8b1 (and barrier metal if there is a barrier metal) are removed by performing a CMP process or the like on the center in the first embodiment, and as shown in FIG. The buried wiring 11a (or the buried wiring 11b) including the conductor films 8b1, 8b2, and 8c is formed.
[0100]
In the second embodiment as well, the following effects can be obtained in addition to the effects obtained in the first embodiment.
[0101]
(1). By depositing the conductor film 8b1 having a predetermined thickness on the bottom of the wiring groove 10b, the wiring groove 10a can be made shallower and the aspect ratio of the wiring groove 10a can be reduced. It is possible to satisfactorily bury the conductive film 8c by the plating method.
[0102]
(Embodiment 3)
FIG. 30 and FIG. 31 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to still another embodiment of the present invention.
[0103]
In the third embodiment, the processing up to FIG. 26 of the second embodiment is the same, and in the subsequent steps, the conductor film 8b2 (see FIG. 27) described in the second embodiment is not applied. As shown in FIG. 30, a conductor film 8c is deposited on the interlayer insulating film 5b (including the inside of the wiring groove 10a) by the same plating method as in the first and second embodiments. The inside of the wiring groove 10a is filled with a conductor film 8c.
[0104]
Thereafter, as shown in FIG. 31, the conductor films 8c and 8b1 (and barrier metal if there is a barrier metal) are removed by performing a CMP process or the like as in the first and second embodiments, as shown in FIG. Then, buried wiring 11a (or buried wiring 11b) formed of conductor films 8b1 and 8c is formed in wiring groove 10a.
[0105]
Further, as a modification of the third embodiment, the temperature of the semiconductor substrate 1 is increased while the conductor film 8b1 is formed by the sputtering method described in the first and second embodiments, and the conductor film 8b1 is formed. Is embedded to the middle of the wiring groove 10a, the aspect ratio of the wiring groove 10a is reduced, and then the conductive film 8c is applied by the same plating method as in the first and second embodiments to fill the wiring groove 10a. good.
[0106]
According to the third embodiment and the modification thereof, it is possible to obtain the same effects as those of the first and second embodiments.
[0107]
(Embodiment 4)
FIG. 32 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to still another embodiment of the present invention during a manufacturing step.
[0108]
In the fourth embodiment, the processing up to FIG. 26 of the second embodiment is the same, and thereafter, the upper surface (see FIG. 26) of the interlayer insulating film 5b in the conductor film 8b1 (see FIG. 26) described in the second embodiment. The conductor film 8b1 in the substantially flat region (excluding the inside of the wiring groove 10a) is removed by a CMP method or the like.
[0109]
After this processing step, as shown in FIG. 32, the conductor film 8b1 is left only at the bottom of the wiring groove 10a.
[0110]
Thus, since the conductor film 8b1 is not provided on the upper surface of the interlayer insulating film 5b (substantially flat region except inside the wiring groove 10a), the wiring groove 10a can be made shallower than in the case of the second and third embodiments. . That is, since the aspect ratio of the wiring groove 10a can be further reduced, the inside of the wiring groove 10a can be satisfactorily buried with a conductive film formed by a subsequent plating method.
[0111]
Subsequently, a conductor film for forming a wiring made of, for example, copper or a copper alloy is applied by the same plating method or the like as in the first to third embodiments, so that the conductor film is selectively provided only in the wiring groove 10a. It is possible to grow. Thereby, the fine wiring trench 10a having a high aspect ratio can be sufficiently buried. The completed drawing in the fourth embodiment is the same as FIG. 31, and the conductor film corresponds to the conductor film 8c.
[0112]
According to the fourth embodiment, in addition to the effects obtained in the first to third embodiments, the following effects can be obtained.
[0113]
(1). By depositing a conductive film 8b1 having a predetermined thickness on the bottom of the wiring groove 10a and removing the conductive film 8b1 on the interlayer insulating film 5b, the wiring groove 10a is removed to the extent that there is no conductive film on the interlayer insulating film 5b. Can be further reduced, so that the aspect ratio of the wiring groove 10a can be further reduced, and the wiring groove 10a can be satisfactorily buried with the conductor film 8c by the subsequent plating method.
[0114]
(2). By depositing the conductor film 8b1 only on the bottom of the wiring groove 10a, it is possible to selectively grow the conductor film 8c only in the wiring groove 10a during the subsequent deposition processing of the conductor film 8c by plating. It becomes.
[0115]
(Embodiment 5)
33 to 36 are main-portion cross-sectional views of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step.
[0116]
In the fifth embodiment, the steps up to FIG. 24 are the same as those in the first to fourth embodiments. In the subsequent step, for example, before or during formation of a conductor film made of copper or a copper alloy by a sputtering method, By performing the sputter etching process, as shown in FIG. 33, the interlayer insulating film 5b above the wiring groove 10a is etched, and the upper surface of the interlayer insulating film 5b and the inner surface of the wiring groove 10a above the fine wiring groove 10a. Is formed at the corner formed by the above.
[0117]
Thus, the opening area (width of the opening) of the fine wiring groove 10a can be increased, so that the step coverage of the conductor film made of copper or a copper alloy in the wiring groove 10a can be improved.
[0118]
As shown in FIG. 34, a conductor film 8b is formed on such an interlayer insulating film 5b by the same sputtering method as in the first and second embodiments, and then, as shown in FIG. Then, a conductive film 8c is applied by the same plating method as in the first to fourth embodiments. Thereby, the fine wiring trench 10a having a high aspect ratio can be sufficiently buried.
[0119]
Thereafter, the conductor films 8c and 8b1 (and barrier metal if there is a barrier metal) are removed by performing a CMP process or the like in the same manner as in the first embodiment and the like, and as shown in FIG. The buried wiring 11a (or the buried wiring 11b) including the films 8b and 8c is formed.
[0120]
In the fifth embodiment, in addition to the effects obtained in the first to fourth embodiments, the following effects can be obtained.
[0121]
(1). Before or during the formation of the conductor film 8b made of copper or a copper alloy by sputtering, sputter etching is performed to form a taper (inclination) at the upper corner of the fine wiring groove 10a, thereby providing fine wiring. Since the opening area above the groove 10a can be increased, the step coverage of the conductor film 8b in the wiring groove 10a can be improved. This makes it possible to satisfactorily fill the wiring groove 10a with the conductor film 8c formed by the subsequent plating method.
[0122]
(Embodiment 6)
37 to 40 are fragmentary cross-sectional views of a semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing steps thereof.
[0123]
In the sixth embodiment, the processing up to FIG. 24 of the second embodiment is the same, and in the subsequent steps, as shown in FIG. 37, a conductor film 8b made of, for example, copper or a copper alloy is formed by sputtering. At the time of film formation, a bias voltage is applied to the semiconductor substrate 1 side (the lower electrode of the sputtering apparatus) so that the film formation process is performed while causing both the film formation and the sputter etching. Bias sputtering is used).
[0124]
According to such a method, the overhang portion (portion shown by a broken line) of the conductor film 8b deposited on the upper portion of the opening of the wiring groove 10a can be removed by the sputter etching action, so that as shown in FIG. 8b can be thinly and evenly applied in the fine wiring groove 10a. That is, the step coverage of the conductor film 8b in the wiring groove 10a can be improved.
[0125]
However, the sputtering conditions described in the first embodiment may be added to the above-described bias sputtering method. Thereby, the step coverage of the conductor film 8b in the wiring groove 10a can be further improved. Further, the above-described barrier metal may be applied before the conductor film 8b is applied.
[0126]
Thereafter, as shown in FIG. 39, a conductor film 8c is deposited on the conductor film 8b by the same plating method as in the first to fifth embodiments. Thereby, the fine wiring trench 10a having a high aspect ratio can be sufficiently buried.
[0127]
Next, the conductor films 8c and 8b (and the barrier metal if there is a barrier metal) are removed by performing a CMP process in the same manner as in the first embodiment, and the conductor film 8b is formed in the wiring groove 10a as shown in FIG. , 8c (or embedded wiring 11b).
[0128]
In the sixth embodiment, in addition to the effects obtained in the first embodiment and the like, the following effects can be obtained.
[0129]
(1). By forming a conductive film 8b made of copper or a copper alloy by a bias sputtering method, an overhang portion of the conductive film 8b formed above the wiring groove 10a is removed, or a thin film is formed by re-sputtering. Since the additional film can be formed, the step coverage of the conductor film 8b in the wiring groove 10a can be improved. This makes it possible to satisfactorily fill the wiring groove 10a with the conductor film 8c formed by the subsequent plating method.
[0130]
(Embodiment 7)
41 to 43 are fragmentary cross-sectional views of a semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing process thereof.
[0131]
In the seventh embodiment, the processing up to FIG. 24 of the first and second embodiments is the same, and in the subsequent steps, as shown in FIG. 41, for example, platinum, palladium, nickel, chromium, gold or silver A thin conductor film 8d made of is deposited by a CVD method, a sputtering method, a plating method, or the like. By doing so, it becomes possible to satisfactorily apply a conductive film made of copper or a copper alloy by a subsequent plating method by a catalytic action.
[0132]
The conductor film 8d is a seed crystal layer of a conductor film to be deposited later by a plating method, and is deposited relatively thin so as not to fill the wiring groove 10a. When the conductive film 8d is formed by a sputtering method, the sputtering conditions of the first embodiment may be added. This makes it possible to improve the step coverage of the thin conductor film 8d.
[0133]
Prior to the deposition of the conductor film 8d, a barrier metal may be deposited on the upper surface of the interlayer insulating film 5b including the inside of the wiring groove 10a. The method may be applied in the same manner as in the first embodiment. Further, for example, platinum, palladium, nickel, chromium, gold, silver or copper may be added to the barrier metal.
[0134]
Subsequently, as shown in FIG. 42, after a conductor film 8c is deposited on the conductor film 8d by plating or the like in the first to sixth embodiments, the CMP is performed in the same manner as in the first to sixth embodiments. By performing processing or the like, the conductive films 8c and 8d and the barrier metal 7b are shaved, and as shown in FIG. 43, an embedded wiring 11a including the barrier metal 7b and the conductive films 8d and 8c is formed in the wiring groove 10a.
[0135]
According to the seventh embodiment, it is possible to obtain the same effects as those of the first embodiment.
[0136]
(Embodiment 8)
44 and 45 are fragmentary cross-sectional views of a semiconductor integrated circuit device according to still another embodiment of the present invention during the manufacturing steps thereof.
[0137]
In the eighth embodiment, as shown in FIG. 44, buried wiring 11a of the first layer includes barrier metal 7b, conductor film 8b (see FIG. 9), conductor film 8c, and conductor film 8d. . The conductor film 8d is made of, for example, platinum, palladium, nickel, chromium, gold, or silver, and is formed so as to cover the upper surface of the conductor film 8c, that is, over the embedded wiring 11a. The conductor film 8d is exposed from the bottom of the connection hole 6b. In such a structure, it is not necessary to consider step coverage when applying the conductor film 8d.
[0138]
By providing the conductor film 8d in this manner, a conductor film made of copper or a copper alloy by a subsequent plating method can be satisfactorily applied by a catalytic action. This method is particularly effective when a conductive film made of copper or a copper alloy or the like is formed by electroless plating.
[0139]
Thereafter, as shown in FIG. 45, a conductor film 8c is deposited on the conductor film 8d by the same plating method as in the fourth embodiment, so that the conductor film 8c is selectively formed in the connection hole 6b and the wiring groove 10a. The film 8c is formed. Thus, the fine wiring groove 10a having a high aspect ratio is sufficiently buried, and the buried wiring 11a made of the conductor film 8c is formed in the connection hole 6b and the wiring groove 10a.
[0140]
According to the eighth embodiment, the same effects as those of the first embodiment can be obtained.
[0141]
(Embodiment 9)
46 to 48 are fragmentary cross-sectional views of a semiconductor integrated circuit device according to still another embodiment of the present invention during the manufacturing steps thereof.
[0142]
In the ninth embodiment, as shown in FIG. 46, after a barrier metal 7b is deposited in the same manner as in the first embodiment, a conductive film 8b is deposited thereon in the same manner as in the first embodiment. However, the thickness of the conductor film 8b is made thicker than in the first embodiment, and the upper surface (substantially flat region) of the interlayer insulating film 5b is made of a conductive film made of copper or a copper alloy by a plating method described later. Also thicken. Here, the thickness of the conductor film 8b is, for example, about 5000 to 6000 °. However, the inside of the wiring groove 10a is not completely filled with the conductor film 8b. As a result, the conductor film 8b is thickly applied to the bottom of the wiring groove 10a.
[0143]
Subsequently, as shown in FIG. 47, a conductor film 8c is deposited on the conductor film 8b by the same plating method as in the first embodiment and the like. Thereby, the fine wiring trench 10a having a high aspect ratio is sufficiently buried. Note that, on the upper surface (substantially flat region) of the interlayer insulating film 5b, the thickness of the conductor film 8c is smaller than the thickness of the conductor film 8b. The thickness of the conductor film 8c is, for example, about 1000 to 2000 degrees. Further, prior to the deposition of the conductor film 8b, the conductor film 8d (see FIG. 41) described in the sixth embodiment or the like may be deposited.
[0144]
After that, the conductor films 8c and 8b are cut by performing a CMP process in the same manner as in the first embodiment and the like, and as shown in FIG. 48, the wiring trench 10a is filled with the barrier metal 7b and the conductor films 8b and 8c. The embedded wiring 11a is formed.
[0145]
According to the ninth embodiment, the same effects as those of the first embodiment can be obtained.
[0146]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0147]
For example, in the first to ninth embodiments, the case where the SOI substrate is used as the semiconductor substrate has been described. However, the present invention is not limited to this. For example, a normal semiconductor substrate including only a semiconductor alone may be used. Alternatively, an epitaxial substrate provided with a thin epitaxial layer on a semiconductor substrate may be used.
[0148]
Further, in the sixth embodiment, a method in which a conductive film made of copper or a copper alloy is formed by a bias sputtering method is employed. However, the present invention is not limited to this. For example, the conductive film may be formed by sputtering particles. The film may be formed by ionization or may be formed by an evaporation method.
[0149]
In the above description, the case where the invention made by the inventor is mainly applied to the semiconductor integrated circuit device technology which is the application field as the background has been described. However, the present invention is not limited thereto. And so on.
[0150]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0151]
(1). ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to fill a conductive film without generating a void inside a fine wiring groove or a connection hole.
[0152]
(2). According to the present invention, for example, platinum, palladium, nickel, chromium, gold, or silver is added to the first conductive film, or the first conductive film is formed of, for example, platinum, palladium, nickel, chromium, gold, or silver. By forming a thin conductor film or the like, it becomes possible to satisfactorily apply the second conductor film made of copper or a copper alloy by a subsequent plating method by a catalytic action. This makes it possible to fill the conductive film without generating voids in the fine wiring grooves or connection holes.
[0153]
(3). According to the present invention, by cooling the semiconductor substrate before or during the formation of the first conductor film, the film formation state of copper or a copper alloy constituting the first conductor film becomes a solid state, and Since the aggregation of the alloy can be suppressed, it is possible to suppress the formation of the discontinuous portion in the first conductor film.
[0154]
(4). According to the present invention, a first conductive film made of copper or a conductive material containing copper is deposited by physical vapor deposition on at least one of the wiring grooves or the connection holes and on the insulating film. By raising the temperature of the semiconductor substrate after the deposition and moving the first conductive film to the bottom of the wiring groove, the aspect ratio of the wiring groove or the connection hole can be reduced. Alternatively, it can be well embedded in the connection hole.
[0155]
(5). According to the present invention, the first conductor film is deposited in a state where both the film formation and the etching are applied, so that the overhang of the conductor film portion deposited on the wiring groove or the connection hole is reduced. Therefore, the subsequent conductive film can be satisfactorily embedded in the wiring groove or the connection hole.
[0156]
(6). According to the above (1), (2), (3), (4) or (5), the occurrence rate of defects in the embedded wiring (including the connection hole) can be reduced, so that the yield and reliability of the semiconductor integrated circuit device can be reduced. It is possible to improve the performance.
[0157]
(7). According to the above (1), (2), (3), (4) or (5), miniaturization of wiring grooves or connection holes can be promoted. For this reason, the degree of element integration can be improved, and miniaturization and high functionality of the semiconductor integrated circuit device can be promoted.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention during a manufacturing step thereof;
FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;
3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;
FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3;
5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4;
6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5;
7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6;
8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;
9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;
10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9;
11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 10;
12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 11;
13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;
14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13;
15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14;
16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 15;
FIG. 17 is an explanatory diagram for explaining sputtering condition setting of the present invention.
FIG. 18 is an explanatory diagram for explaining sputtering condition setting of the present invention.
FIG. 19 is an explanatory diagram for explaining sputtering condition setting of the present invention.
FIG. 20 is an explanatory diagram illustrating the setting of sputtering conditions according to the present invention.
FIG. 21 is an explanatory diagram for explaining sputtering condition setting of the present invention.
FIG. 22 is an essential part enlarged cross sectional view of the semiconductor integrated circuit device of one embodiment of the present invention during a manufacturing step;
FIG. 23 is an enlarged cross-sectional view of a main part during a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;
FIG. 24 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step thereof;
25 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 24;
26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 25;
27 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 26;
FIG. 28 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 27;
FIG. 29 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 28;
FIG. 30 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step thereof;
FIG. 31 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 30;
FIG. 32 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;
FIG. 33 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;
34 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 33;
FIG. 35 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 34;
36 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 35;
FIG. 37 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;
38 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 37;
39 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 38;
40 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 39;
FIG. 41 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;
42 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 41;
FIG. 43 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 42;
FIG. 44 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;
FIG. 45 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 44;
FIG. 46 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to still another embodiment of the present invention during a manufacturing step thereof;
FIG. 47 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 46;
FIG. 48 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;
FIG. 49 is an explanatory diagram for explaining a problem at the time of forming a buried wiring examined by the present inventors.
FIG. 50 is an explanatory diagram for explaining a problem at the time of forming a buried wiring examined by the present inventors.
[Explanation of symbols]
1 semiconductor substrate
1a Support substrate
1b Insulating layer
1c Semiconductor layer
2a groove
2b insulating film
3a Semiconductor area
3b Gate insulating film
3c Gate electrode
4a Side wall
4b Cap insulating film
5a Interlayer insulating film
5b Interlayer insulating film
5c interlayer insulating film
6a Connection hole
6b Connection hole
7a barrier metal
7b Barrier metal (barrier conductor film)
8a Conductive film
8b Conductive film (first conductive film)
8b1 Conductive film
8b2 Conductive film
8c Conductive film (second conductive film)
8d conductor film (third conductor film)
9a plug
10a, 10b Wiring groove
11a, 11b embedded wiring
12 Barrier insulating film
Q MOS ・ FET

Claims (7)

A method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) forming a first conductive film made of copper or a conductive material containing copper on at least one of the wiring groove or the connection hole and on the insulating film for forming the first conductive film on the main surface of the semiconductor substrate; distance TS between the main surface of the target, and a value obtained by dividing more than the sum of the square root of 3 of the radius R 2 of the effective radius R 1 and the semiconductor substrate of the target, and the first time of discharging Depositing by physical vapor deposition under the condition that the mean free path of the particles of the conductive film is not less than TS / COS (arctan (R 1 + R 2 ) / TS) ;
(C) applying a second conductor film made of copper or a conductor material containing copper by a plating method after the formation of the first conductor film;
(D) forming a buried interconnect made of the first conductor film and the second conductor film in at least one of the interconnection groove and the connection hole by shaving the first conductor film and the second conductor film. A method for manufacturing a semiconductor integrated circuit device, comprising: The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first conductive film contains at least one of platinum, palladium, nickel, chromium, gold, and silver, or on the first conductive film, A method for manufacturing a semiconductor integrated circuit device, comprising: depositing a third conductor film containing at least one of platinum, palladium, nickel, chromium, gold, and silver, and then depositing the second conductor film. A method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove and a connection hole in the insulating film;
(B) depositing a barrier conductor film inside at least one of the wiring groove or the connection hole and on the insulating film;
(C) forming a first conductive film made of copper or a conductive material containing copper on at least one of the wiring groove or the connection hole and on the insulating film for forming the first conductive film on the main surface of the semiconductor substrate; distance TS between the main surface of the target, and a value obtained by dividing more than the sum of the square root of 3 of the radius R 2 of the effective radius R 1 and the semiconductor substrate of the target, and the first time of discharging Depositing by physical vapor deposition under the condition that the mean free path of the particles of the conductive film is not less than TS / COS (arctan (R 1 + R 2 ) / TS) ;
(D) after forming the first conductive film, applying a second conductive film made of copper or a conductive material containing copper by a plating method;
(E) forming a buried interconnect made of the first conductor film and the second conductor film in at least one of the interconnection groove and the connection hole by shaving the first conductor film and the second conductor film. A method for manufacturing a semiconductor integrated circuit device, comprising: 4. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein said barrier conductor film contains at least one of platinum, palladium, nickel, chromium, gold and silver, or said first conductor film contains platinum, palladium and nickel. Containing at least one of chromium, gold or silver, or after depositing a third conductor film containing at least one of platinum, palladium, nickel, chromium, gold or silver on the barrier conductor film And a method of manufacturing a semiconductor integrated circuit device, comprising applying the first conductive film. The method for manufacturing a semiconductor integrated circuit device according to claim 1 or 3, wherein, the method of manufacturing a semiconductor integrated circuit device characterized by cooling the semiconductor substrate during deposition of the first conductive film. The method for manufacturing a semiconductor integrated circuit device according to claim 1, 2, 3, 4 or 5, wherein, by increasing the temperature of the semiconductor substrate after deposition during or deposition of the first conductive layer, the first conductive film A method for manufacturing a semiconductor integrated circuit device, comprising a step of moving to a bottom of a wiring groove. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein A method of manufacturing a semiconductor integrated circuit device, wherein a bias voltage is applied to the semiconductor substrate during the deposition of the first conductive film.

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