JP2006253729A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To excellently embed a conductor film for forming an embedding wiring in a wiring trench or connection hole formed in an insulating film. <P>SOLUTION: When an embedding wiring 11b is formed in a wiring trench 10b formed in an insulating film 5c on a semiconductor substrate 1, after a conductor film 8b constituting the embedding wiring 11b is coated by a sputtering method which has a directivity and in which a condition that sputtering particles are difficult to scatter is added, a conductor film 8c constituting the embedding wiring 11b is coated by a plating method. The conductor film 8b is composed of a conductor material containing copper adding at least one of platinum, palladium, nickel, chrome, gold and silver. A thickness of a coated film of the conductor film 8b is equal to a thickness of the coated film of the conductor film 8c, or is thicker than the coated film of the conductor film 8c. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a buried wiring technique formed by embedding a wiring conductor film in a groove or a connection hole formed in an insulating film. Is.

  As a wiring forming method for a semiconductor integrated circuit device, there is a process called a damascene method. In this method, after forming a trench for wiring formation in an insulating film, a conductor film for wiring formation is deposited on the entire surface of the semiconductor substrate, and the conductor film in a region other than the trench is further subjected to chemical mechanical polishing (CMP). A method of forming a buried wiring in a trench for forming a wiring by removing it by chemical mechanical polishing. This method is particularly suitable as a method for forming an embedded wiring made of a copper-based conductor material (copper or copper alloy) that is difficult to be finely etched.

  As an application of the damascene method, there is a dual-damascene method. In this method, after forming a wiring formation groove and a connection hole for connecting with a lower layer wiring in the insulating film, a wiring formation conductor film is deposited on the entire surface of the semiconductor substrate, and the region other than the groove is formed. In this method, the conductive film is removed by CMP to form a buried wiring in the wiring forming groove and to form a plug in the connection hole. In the case of this method, in particular, in a semiconductor integrated circuit device having a multilayer wiring structure, the number of steps can be reduced, and the wiring cost can be reduced.

  For example, (1). K. Abe et.al, in Extended Abstracts 1994 SSDM, pp937-940 (Oki Electric), (2). Valery M. Dubin et. .al, in Proceedings 1997 VMIC, pp 69-74.

  The above document (1) discloses a technique in which a groove is formed in an insulating film, copper is deposited by sputtering, and heat treatment is performed to satisfactorily fill the groove for wiring formation (non-patent document). 1). Further, the above document (2) discloses a method in which copper is deposited by sputtering in the grooves and connection holes formed in the insulating film, and then copper is embedded by plating (non-patent document). 2).

  Further, for example, Japanese Patent Laid-Open No. 8-78525 discloses a step of forming a connection hole in which a part of a semiconductor substrate is exposed in an insulating film deposited on the semiconductor substrate, and a wiring layer on the insulating film. An ordinary wiring formation technique for a semiconductor integrated circuit device is disclosed, which includes a step of forming a metal layer by sputtering, a step of forming a metal layer by plating on the wiring, and a step of patterning the wiring layer and the metal layer. Yes.

The technique described in this publication is different from the application process on the premise of the damascene process, and applies plating to the low-aspect connection hole having a relatively loose design rule. However, when applied to fine and high aspect ratio connection holes and damascene structures, the technique of this publication using the ordinary sputtering method has a low step coverage in the conductor film connection holes by the sputtering method. Even if it is applied, the conductor film for wiring formation cannot be completely embedded, and voids are generated in the connection holes (see Patent Document 1).
K.Abe et.al, in Extended Abstracts 1994 SSDM, pp937 −940 (Oki Electric) Valery M. Dubin et.al, in Proceedings 1997 VMIC, pp69 −74 JP-A-8-78525

  However, the inventor has found that the embedded wiring technology has the following problems as the wiring grooves and connection holes become finer and the aspect ratio increases.

  That is, it is difficult to embed a wiring groove or a connection hole by a sputtering method alone, and the groove or the connection hole cannot be embedded sufficiently, and a good electrical property is obtained in an embedded wiring (including a wiring part and a connection hole part). The special characteristics cannot be secured.

  In addition, when the plating method is used, the embedding ability is high, but in this case as well, a base metal film is necessary, and the limit of embedding is determined by the coverage of the base metal film. And the connection hole portion).

  An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film, and is provided inside at least one of the wiring groove or connection hole. An object of the present invention is to provide a technique capable of satisfactorily embedding a conductor film for forming an embedded wiring.

  Another object of the present invention is to promote miniaturization of embedded wiring in a method for manufacturing a semiconductor integrated circuit device having a structure in which embedded wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film. It is to provide technology that can.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

That is, the present invention is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) a first conductor made of a conductive material containing copper to which at least one of platinum, palladium, nickel, chromium, gold, or silver is added in at least one of the wiring groove or connection hole and on the insulating film; Depositing the film by physical vapor deposition;
(C) after forming the first conductor film, depositing a second conductor film made of copper or a conductor material containing copper by a plating method;
(D) forming a buried wiring composed of the first conductor film and the second conductor film in the wiring groove by cutting the first conductor film and the second conductor film,
The film thickness of the first conductor film on the insulating film is equal to the film thickness of the second conductor film or larger than the film thickness of the second conductor film.

  Of the inventions disclosed in this application, the outline of other representative ones will be briefly described as follows.

The present invention is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) A first conductor film made of a conductor material containing copper or copper is provided on at least one of the wiring groove or the connection hole and on the insulating film, and the particles of the first conductor film have directivity. Is deposited by physical vapor deposition under conditions where it is difficult to scatter between the target and the semiconductor substrate,
(C) after forming the first conductor film, depositing a second conductor film made of copper or a conductor material containing copper by a plating method;
(D) forming a buried wiring composed of the first conductor film and the second conductor film in at least one of the wiring groove or the connection hole by cutting the first conductor film and the second conductor film; It is what you have.

  In the present invention, the first conductor film may contain at least one of platinum, palladium, nickel, chromium, gold or silver, or platinum, palladium, nickel, chromium, After the third conductor film containing at least one of gold or silver is deposited, the second conductor film is deposited.

  The present invention also cools the semiconductor substrate before or during deposition of the first conductor film.

Further, the present invention is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) During or during deposition of a first conductor film made of copper or a conductor material containing copper on at least one of the wiring groove or connection hole and on the insulating film by physical vapor deposition And a step of raising the temperature of the semiconductor substrate later and moving the first conductor film to the bottom of the wiring trench.

Further, the present invention is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) depositing a third conductor film containing at least one of platinum, palladium, nickel, chromium, gold or silver on at least one of the wiring groove or the connection hole and on the insulating film;
(C) After forming the third conductor film, depositing a second conductor film made of copper or a conductor material containing copper by a plating method;
(D) forming a buried wiring composed of the second conductor film and the third conductor film in at least one of the wiring groove or the connection hole by cutting the second conductor film and the third conductor film; It is what you have.

Further, the present invention is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) Forming the first conductor film made of copper or a conductor material containing copper by physical vapor deposition on at least one of the wiring groove or connection hole and on the insulating film. A process for allowing both the action and the etching action to be performed;
(C) after forming the first conductor film, depositing a second conductor film made of copper or a conductor material containing copper by a plating method;
(D) forming a buried wiring made of the first conductor film and the second conductor film in the wiring groove by cutting the first conductor film and the second conductor film.

  Of the other means examined by the present inventors, the outline of typical ones will be briefly described as follows.

That is, the means is a method for manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) During or during deposition of a first conductor film made of copper or a conductor material containing copper on at least one of the wiring groove or connection hole and on the insulating film by physical vapor deposition Increasing the temperature of the semiconductor substrate later and moving the first conductor film to the bottom of the wiring trench;
(C) After the step (b), at least one of copper, copper alloy, platinum, palladium, nickel, chromium, gold, or silver is formed on at least one of the wiring groove or the connection hole and on the first conductor film. A step of depositing a conductive film containing a material by physical vapor deposition;
(D) After the step (c), a step of depositing a second conductive film made of copper or a conductive material containing copper by a plating method;
(E) After the step (d), the second conductor film and the first conductor film are shaved, and at least one of the wiring groove or the connection hole is filled with the first conductor film, the second conductor film, and the conductor film. Forming a buried wiring. As a result, the aspect ratio of the wiring groove or the connection hole can be reduced, so that it is possible to satisfactorily embed the conductor film by subsequent plating. It is also possible to satisfactorily deposit a conductor film made of copper or a copper alloy by a subsequent plating method by catalytic action.

Another means is a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) During or during deposition of a first conductor film made of copper or a conductor material containing copper on at least one of the wiring groove or connection hole and on the insulating film by physical vapor deposition Increasing the temperature of the semiconductor substrate later and moving the first conductor film to the bottom of the wiring trench;
(C) After the step (b), a step of depositing a second conductor film made of copper or a conductor material containing copper by a plating method;
(D) After the step (c), the second conductor film and the first conductor film are shaved, and at least one of the wiring groove or the connection hole is filled with the first conductor film, the second conductor film, and the conductor film. Forming a buried wiring. As a result, the aspect ratio of the wiring groove or the connection hole can be reduced, so that it is possible to satisfactorily embed the conductor film by subsequent plating.

Another means is a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) During or during deposition of the first conductor film made of copper or a conductor material containing copper on at least one of the wiring groove or the connection hole and on the insulating film by physical vapor deposition. Increasing the temperature of the semiconductor substrate later and moving the first conductor film to the bottom of the wiring trench;
(C) after the step (b), removing the first conductor film on the insulating film;
(D) After the step (c), a copper or copper-containing second conductor film is selectively formed by plating on the first conductor film left in the wiring groove by the first conductor film removal step. And a process of depositing. As a result, the aspect ratio of the wiring groove or the connection hole can be reduced, so that it is possible to satisfactorily embed the conductor film by subsequent plating. Further, the embedded wiring can be formed without performing the conductor film removal step.

Another means is a method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) depositing a first conductor film made of a conductor material containing copper or copper on at least one of the wiring groove or the connection hole and on the insulating film by a physical vapor deposition method;
(C) After the step (b), a step of depositing a second conductor film made of copper or a conductor material containing copper by a plating method;
(D) After the step (c), the second conductor film and the first conductor film are shaved, and at least one of the wiring groove or the connection hole is filled with the first conductor film, the second conductor film, and the conductor film. Forming a buried wiring,
A step of performing a sputter etching process before or during the deposition of the first conductor film. As a result, a taper is formed on the upper portion of the wiring groove or the connection hole so that the sputtered particles can easily reach the bottom of the wiring groove or the connection hole, or the first conductor film inside the wiring groove or the connection hole is re-sputtered. By doing so, step coverage can be improved.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
(1) According to the present invention, it is possible to fill a conductor film without generating voids in fine wiring grooves or connection holes.
(2) According to the present invention, for example, platinum, palladium, nickel, chromium, gold, or silver is added to the first conductor film, or platinum, palladium, nickel, chromium, gold, for example, is added to the first conductor film. Alternatively, by forming a thin conductor film made of silver, the second conductor film made of copper or a copper alloy by a subsequent plating method can be satisfactorily deposited by catalytic action. As a result, it is possible to fill the conductor film without generating voids in the fine wiring grooves or connection holes.
(3) According to the present invention, by cooling the semiconductor substrate before or during the formation of the first conductor film, the film formation state of the copper or copper alloy constituting the first conductor film becomes a solid state. Since aggregation of copper or a copper alloy can be suppressed, it is possible to suppress formation of a discontinuous portion in the first conductor film.
(4) According to the present invention, the first conductor film made of copper or a conductor material containing copper is deposited by physical vapor deposition on the inside of at least one of the wiring groove or the connection hole and on the insulating film. By increasing the temperature of the semiconductor substrate during or after deposition and moving the first conductor film to the bottom of the wiring groove, the aspect ratio of the wiring groove or connection hole can be reduced, so that the subsequent conductor The film can be satisfactorily embedded in the wiring groove or the connection hole.
(5). According to the present invention, the first conductor film is deposited in a state where both the film formation and the etching are applied, so that the conductor film portion deposited on the upper part of the wiring groove or the connection hole is formed. Since the overhang can be reduced, the subsequent conductor film can be satisfactorily embedded in the wiring groove or the connection hole.
(6). By the above (1), (2), (3), (4) or (5), the defect occurrence rate in the embedded wiring (including the connection hole) can be reduced, so that the semiconductor integrated circuit device Yield and reliability can be improved.
(7) By the above (1), (2), (3), (4) or (5), it is possible to promote the miniaturization of the wiring groove or the connection hole. Therefore, the degree of element integration can be improved, and it becomes possible to promote the miniaturization and high functionality of the semiconductor integrated circuit device.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail below with reference to the drawings. (In the drawings for explaining the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof is omitted.) To do).

(Embodiment 1)
1 to 16 are cross-sectional views of the main part of the semiconductor integrated circuit device according to one embodiment of the present invention during the manufacturing process, and FIGS. 17 to 21 are explanatory diagrams and diagrams for explaining the sputtering condition setting of the present invention. 22 and FIG. 23 are enlarged cross-sectional views of essential parts during the manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention, and FIGS. 49 and 50 illustrate defects in the formation of embedded wiring studied by the present inventors. It is explanatory drawing for doing.

  First, the manufacturing method of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

  FIG. 1 is a cross-sectional view of a main part during a manufacturing process of a semiconductor integrated circuit device. As the semiconductor substrate 1, for example, an SOI substrate in which a semiconductor layer 1c for element formation is provided on a support substrate 1a via an insulating layer 1b is used.

  The support substrate 1a is made of, for example, silicon single crystal, and the insulating layer 1b is made of, for example, a silicon oxide film. The semiconductor layer 1c is made of, for example, p-type silicon single crystal, and a trench 2a reaching the insulating layer 1b from the main surface of the semiconductor layer 1c is dug in the element isolation region. An insulating film 2b made of, for example, a silicon oxide film is buried in the groove 2a.

  Further, for example, an n channel type MOS • FET Q is formed in the semiconductor layer 1c. The MOS • FETQ has a pair of semiconductor regions 3a, a gate insulating film 3b, and a gate electrode 3c. For example, phosphorus or arsenic is introduced into the semiconductor layer 1c and the n-type semiconductor region 3a is set. The central semiconductor region 3a is a region shared by the adjacent MOS • FETQ.

  The gate insulating film 3b is made of, for example, a silicon oxide film. The gate electrode 3c is made of, for example, a single film of low resistance polysilicon. However, the gate electrode 3c is not limited to a single film of low resistance polysilicon and can be variously modified. For example, a so-called polycide structure in which a silicide film is formed on a low resistance polysilicon film may be used. For example, a so-called polymetal structure in which a metal film such as tungsten is formed on low-resistance polysilicon via a barrier metal film such as titanium nitride or tungsten nitride may be used.

  The surface of the gate electrode 3c is covered with a cap insulating film 4a and sidewalls 4b. The cap insulating film 4a and the sidewall 4b are made of, for example, a silicon oxide film or a silicon nitride film. By forming the cap insulating film 4a and the side walls 4b with silicon nitride films and employing a selective etching process, the connection holes of the interlayer insulating film can be formed in a self-aligning manner.

  An interlayer insulating film 5a made of, for example, a silicon oxide film is deposited on the main surface of the semiconductor layer 1c. The interlayer insulating film 5a may be a coating film by an SOG (Spin On Glass) method, an organic film, a CVD oxide film to which fluorine is added, a silicon nitride film, or a combination of various insulating films. In the interlayer insulating film 5a, a connection hole 6a is formed so that a part of the semiconductor region 3a is exposed.

  First, in the first embodiment, as shown in FIG. 2, the barrier metal 7a is deposited on the upper surface of the interlayer insulating film 5a and the connection hole 6a by the CVD method, the sputtering method, the plating method or the like.

  The barrier metal 7a improves adhesion between the interlayer insulating film 5a and the conductor film for wiring formation, and suppresses diffusion of CVD source gas for forming the conductor film for wiring formation, constituent atoms of the conductor film, and silicon For example, it is made of another metal such as titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, titanium nitride silicide or tungsten nitride silicide, or a compound thereof.

  Subsequently, a conductive film 8a for forming a wiring that is relatively thicker than the barrier metal 7a is deposited on the barrier metal 7a by a CVD method or the like. Thereby, the connection hole 6a is embedded. The conductor film 8a is made of, for example, tungsten or an alloy thereof.

  Thereafter, by performing CMP (Chemical Mechanical Polishing), the conductor film 8a and the barrier metal 7a are shaved until the upper surface of the interlayer insulating film 5a is exposed. Thereby, as shown in FIG. 3, a plug 9a made of the barrier metal 7a and the conductor film 8a is formed in the connection hole 6a.

  Next, as shown in FIG. 5, an interlayer insulating film 5b made of, for example, a silicon oxide film is deposited by a CVD method or the like, and is flattened. Then, a wiring trench 10a is formed in the interlayer insulating film 5b by photolithography technology and It is formed by dry etching technology. Note that the upper surface of the plug 9a is exposed on the bottom surfaces of the two left wiring grooves 10a in FIG. Further, the interlayer insulating film 5b may be formed in the same manner as the interlayer insulating film 5a.

  The width of the wiring groove 10a is not particularly limited, for example, about 0.13 to 1.0 μm. For example, the width is about 0.25 μm, and the depth is not particularly limited, for example, about 0.15 to 1.0 μm. The wiring pitch is about 0.26 to 2.0 μm, for example, and is not particularly limited, but is about 0.5 μm, for example.

  Subsequently, as shown in FIG. 6, after depositing a barrier metal (barrier conductor film) 7b on the upper surfaces of the interlayer insulating films 5a and 5b and in the wiring grooves 10a by a CVD method, a sputtering method, a plating method or the like, As shown in FIG. 7, a conductor film (first conductor film) 8b made of, for example, copper or a copper alloy is deposited on the barrier metal 7b by sputtering or the like.

  The function and constituent material of the barrier metal 7b are the same as those of the barrier metal 7a. In some cases, the barrier metal 7b may be omitted. The conductor film 8b for wiring formation is a seed crystal layer of a conductor film that is subsequently deposited by plating, and is deposited relatively thin so as not to fill the wiring groove 10a. The thickness of the conductor film 8b is, for example, about 500 to 1500 mm.

  The sputtering process for depositing the wiring forming conductor film 8b is performed under the conditions (directivity conditions) such that the incident angle of the sputtered particles with respect to the wiring grooves 10a is vertical or close to the value. It is performed under the condition that the particles are hardly scattered between the main surface of the semiconductor substrate and the main surface (sputtering surface) of the target. The setting of the sputtering conditions will be described later in detail.

  By depositing the conductor film 8b for wiring formation under such conditions, the conductor film 8b is thin in the wiring groove 10a, with little or no overhang in the upper part of the wiring groove 10a, and Can be applied without any unevenness. That is, the conductor film 8b can be deposited with high step coverage. The barrier metal 7b may also be deposited under similar sputtering conditions.

  Further, for example, platinum, palladium, nickel, chromium, gold, silver or copper may be added to the barrier metal 7b. Further, for example, platinum, palladium, nickel, chromium, gold or silver may be added to the conductor film 8b. Furthermore, a thin conductor film made of, for example, platinum, palladium, nickel, chromium, gold, or silver may be deposited on the upper surface (including the inside of the groove or hole) of the conductor film 8b. By doing in this way, it becomes possible to adhere | attach the conductor film which consists of copper or copper alloy by the subsequent plating method favorably by a catalytic action. This method is particularly effective when an electroless plating method is used.

  After that, as shown in FIG. 8, a conductor film (second conductor film) 8c made of, for example, copper or a copper alloy is deposited on the conductor film 8b by a plating method or the like. Thereby, the fine and high aspect ratio wiring trench 10a can be sufficiently filled.

  The plating method in this case may be any of an electrolytic plating method, an electroless plating method, or a combination thereof (in this case, basically, electroplating after electroless plating). Further, the thickness of the conductor film 8c is thicker than the thickness of the conductor film 8b on the upper surface of the interlayer insulating film 5b (flat region other than the grooves and holes). The thickness of the conductor film 8c is, for example, about 0.5 to 1.0 μm.

  Next, by conducting a CMP process, the conductor films 8c and 8b and the barrier metal 7b are shaved until the upper surface of the interlayer insulating film 5b is exposed. As a result, as shown in FIG. 9, a buried wiring 11a composed of the barrier metal 7b and the conductor films 8b and 8c is formed in the wiring groove 10a. The embedded wiring 11a extends in a direction perpendicular to the paper surface of FIG.

  Subsequently, as shown in FIG. 10, a barrier insulating film 12 made of, for example, a silicon nitride film or the like is deposited on the interlayer insulating film 5b and the embedded wiring 11a by the CVD method or the like, and on that, FIG. As shown, an interlayer insulating film 5c made of, for example, a silicon oxide film is deposited by a CVD method or the like. The interlayer insulating film 5c may be formed in the same manner as the interlayer insulating film 5a described above.

  Thereafter, a wiring trench 10b is formed on the interlayer insulating film 5c by photolithography and dry etching techniques, and then reaches the buried wiring 11a from the bottom of the wiring trench 10b as shown in FIG. A connection hole 6b in which a part of the contact hole 6b is exposed is formed by a photolithography technique and a dry etching technique.

  The dimensions and wiring pitch of the wiring groove 10b are the same as those of the wiring groove 10a. In addition, the diameter of the connection hole 6b is not particularly limited, for example, about 0.13-1.0 μm, for example, about 0.25 μm, and the depth is, for example, about 0.15-2.0 μm, although not particularly limited. For example, it is about 0.6 μm.

  In forming the connection hole 6b, an etching process is performed under the condition that the etching selection ratio between the silicon oxide film and the silicon nitride film is increased. That is, at first, when the barrier insulating film 12 made of the silicon nitride film is exposed from the bottom of the connection hole 6b after performing the etching process under the condition that the silicon oxide film is more easily etched than the silicon nitride film, the etching condition is set. In other words, the silicon nitride film is etched under conditions that make it easier to etch than the silicon oxide film. Thereby, it is possible to prevent the embedded wiring 11a from being removed when the connection hole 6b is formed.

  Next, as shown in FIG. 13, after depositing a barrier metal (barrier conductor film) 7b on the upper surface of the interlayer insulating film 5c, the wiring groove 10b, and the connection hole 6b by CVD, sputtering, plating, or the like. As shown in FIG. 14, a conductor film (first conductor film) 8b made of, for example, copper or copper alloy is deposited on the barrier metal 7b by sputtering or the like.

  The function and constituent material of the barrier metal 7b are the same as those of the barrier metal 7a. The conductor film 8b for wiring formation is a seed crystal layer of a conductor film that is subsequently deposited by a plating method, and is deposited relatively thin so as not to fill the connection hole 6b and the wiring groove 10b. The thickness of the conductor film 8b is, for example, about 500 to 1500 mm.

  The sputtering process for depositing the wiring forming conductor film 8b is performed under the conditions (directivity conditions) such that the incident angle of the sputtered particles with respect to the wiring groove 10b is vertical or a value close thereto. It is performed under the condition that the particles are hardly scattered between the main surface of the semiconductor substrate and the main surface (sputtering surface) of the target. The setting of the sputtering conditions will be described later in detail.

  By depositing the conductor film 8b for forming the wiring under such conditions, the conductor film 8b is formed in the connection hole 6b and the wiring groove 10b with little or no overhang in the upper part of the wiring groove 10b. It can be applied in a thin and uniform state. That is, the conductor film 8b can be deposited with high step coverage. The barrier metal 7b may also be deposited under similar sputtering conditions.

  Also here, for example, platinum, palladium, nickel, chromium, gold, silver or copper may be added to the barrier metal 7b. Further, for example, platinum, palladium, nickel, chromium, gold or silver may be added to the conductor film 8b. Furthermore, a thin conductor film made of, for example, platinum, palladium, nickel, chromium, gold, or silver may be deposited on the upper surface (including the inside of the groove or hole) of the conductor film 8b. By doing in this way, it becomes possible to adhere | attach the conductor film which consists of copper or copper alloy by the subsequent plating method favorably by a catalytic action. This method is particularly effective when an electroless plating method is used.

  Thereafter, as shown in FIG. 15, a conductor film (second conductor film) 8c made of, for example, copper or a copper alloy is deposited on the conductor film 8b by a plating method or the like. Thereby, the connection hole 6b and the wiring groove 10b which are fine and have a high aspect ratio can be sufficiently embedded. The plating method in this case may be any of an electrolytic plating method, an electroless plating method, or a combination thereof (in this case, basically, electroplating after electroless plating). The thickness of the conductor film 8c is, for example, about 0.5 to 1.0 μm.

  Next, by conducting a CMP process, the conductor films 8c and 8b and the barrier metal 7b are shaved until the upper surface of the interlayer insulating film 5c is exposed. Thereby, as shown in FIG. 16, a buried wiring 11b composed of the barrier metal 7b and the conductor films 8b and 8c is formed in the connection hole 6b and the wiring groove 10b.

  The portion of the embedded wiring 11b in the wiring groove 10b extends in a direction perpendicular to the paper surface of FIG. Further, the portion of the embedded wiring 11b in the connection hole 6b does not extend in the direction perpendicular to the paper surface of FIG. 16, but extends in the vertical direction of FIG. 16 to electrically connect the embedded wirings 11a and 11b. Connected to.

  Next, after describing the problem when the conductor film is deposited in the groove or hole by the sputtering method, a technique for setting the sputtering conditions for the above-described conductor film 8b for wiring formation will be described.

  FIG. 49 shows a cross-sectional view of the wiring trench 51 formed in the interlayer insulating film 50 when the film is formed by a normal sputtering method that does not have the above directivity and does not consider scattering of the sputtered particles. Yes.

  A barrier metal 52 made of, for example, titanium nitride is deposited on the upper surface of the interlayer insulating film 50 and the surface of the wiring trench 51. When the conductor film 53 made of copper or copper alloy or the like is deposited by using the above-described normal sputtering method, the copper or copper alloy particles cannot enter the wiring groove 51, and the conductor film 53 is formed on the inner surface of the wiring groove 51. In other words, the non-continuous portion or insufficient coverage occurs, the insufficient coverage of the conductive film 53 occurs at the bottom of the wiring groove 51, or the overhang due to the conductive film 53 increases at the upper portion of the wiring groove 51.

  In this state, as shown in FIG. 50, when a conductor film 54 made of copper or a copper alloy is deposited by plating, voids are formed on the inner surface of the wiring groove 51 due to the above discontinuity and insufficient coverage. Or a large void occurs in the center of the wiring groove 51 due to the overhang described above. Such a problem similarly occurs not only in the wiring groove 51 but also in the connection hole.

  Therefore, in the present embodiment, the conductor film 8b is deposited under the following sputtering conditions.

  The first means will be described with reference to FIG. The conditions here are the distance TS between the main surface (sputtering surface) of the target TG and the main surface of the semiconductor substrate 1 in the sputtering apparatus, and the sum of the effective radius R1 of the target TG and the radius R2 of the semiconductor substrate 1. And the average free path of the sputtered particles of the conductor film 8b at the time of discharge is set to a length L1 = TS / COS (arctan (R1 + R2) / TS) or more.

  Thus, when the direction perpendicular to the main surface of the semiconductor substrate 1 is set to zero (0) degrees, the maximum angle of the incident angle of the sputtering particles to the semiconductor substrate 1 is limited to 30 degrees or less. By limiting the incident angle to about 30 degrees or less, it becomes possible to allow the sputtering particles flying without scattering to reach the center of the bottom of the hole (or groove) having an aspect ratio = 1 with a probability of 100%. . Further, it reaches the corner portion at the bottom of the hole (or groove) having an aspect ratio = 2 with a probability of 50%.

  In addition, strictly speaking, the incident angle is preferably set to 26.6 degrees or less, but in this case, the effect can be obtained even at 30 degrees. Conversely, at 30 degrees, for an aspect ratio of 0.87, the sputtered particles are 100% at the center of the bottom of the hole (or groove), and for an aspect ratio of 1.73, It can be reached with a 50% probability around the bottom of the hole (or groove).

  Further, although not particularly limited, TS in this case is, for example, about 300 mm, R 1 is, for example, about 125 mm, R 2 is, for example, about 62.5 mm, and a pressure is, for example, about 0.025 Pa, and (R 1 + R 2) is 3 The value divided by the square root is, for example, about 108 mm. Therefore, TS / COS (arctan ((R1 + R2) / TS)) is, for example, about 350 mm, and the mean free path is, for example, about 470 mm.

  The second means will be described with reference to FIGS. The condition here is that the distance TS between the main surface (sputtering surface) of the target TG and the semiconductor substrate 1 in the sputtering apparatus is not less than the radius (or diameter) of the semiconductor substrate 1.

  Here, in FIG. 18, when the direction perpendicular to the main surface of the semiconductor substrate 1 is zero (0) degrees, the maximum angle of the incident angle of the sputtering particles to the semiconductor substrate 1 is 30 degrees or less. Limit to. Thereby, the same effect as a 1st means is acquired.

  In this case as well, strictly speaking, the incident angle is preferably 26.6 degrees or less, but is set to about 30 degrees or less for the same reason as described above. On the other hand, if the angle is 30 degrees, the sputtering particles can reach 100% at the center of the bottom of the hole (or groove) and 50% at the periphery with respect to the aspect ratio of 0.87 / 1.73. it can.

  FIG. 19 shows a case where radius R1 = radius R2, and the incident angle is limited to 45 degrees or less. By limiting the incident angle to about 45 degrees or less, it is possible to cause the sputtering particles flying without scattering to reach the center of the bottom of the hole (or groove) having an aspect ratio of 0.5 with a probability of 100%. it can. Further, the corner portion of the hole (or groove) having an aspect ratio = 1 can be reached with a probability of 50%.

  Although not particularly limited, TS is, for example, about 170 mm, R 1 is, for example, about 125 mm, R 2 is, for example, about 62.5 mm, and the pressure is, for example, about 0.025 Pa. The diameter of the semiconductor substrate 1 is, for example, The average free path is about 470 mm, for example, about 125 mm.

  The third means will be described with reference to FIGS. The condition here is that the distance between the main surface (sputtering surface) of the target TG and the semiconductor substrate 1 in the sputtering apparatus is not less than the diameter of the semiconductor substrate 1 × 2.

  Here, in FIG. 20, when the direction perpendicular to the main surface of the semiconductor substrate 1 is zero (0) degrees, the maximum angle of the incident angle of the sputtered particles to the semiconductor substrate 1 is 14 degrees or less. Limit to. By limiting the incident angle to about 14 degrees or less, the sputtered particles mainly fly from the center of the target TG to the main surface of the semiconductor substrate 1 and fly without scattering. It is possible to reach the center of the bottom of the groove) with a probability of 100%. Further, it reaches the corner portion at the bottom of the hole (or groove) having an aspect ratio = 4 with a probability of 50%.

  In FIG. 21, the incident angle is limited to 30 degrees or less. Thereby, the same effect as the first means can be obtained.

  Although the incident angle is preferably 26.6 degrees or less strictly, it is set to about 30 degrees or less for the same reason as described above. On the other hand, if the angle is 30 degrees, the sputtering particles can reach 100% at the center of the bottom of the hole (or groove) and 50% at the periphery with respect to the aspect ratio of 0.87 / 1.73. it can.

  Further, although not particularly limited, TS, R1, R2, pressure, mean free path, and the like in this case are the same as those of the first means.

  As a fourth means, in the sputtering process for depositing the conductor film 8b (see FIG. 7 and the like), the pressure in the sputtering chamber is lowered. In the present embodiment, although not particularly limited, the pressure in the sputtering chamber is set to, for example, 0.1 Pa or less, preferably about 0.025 Pa when the TS is 300 mm. Thereby, since scattering of the sputtered particles can be further suppressed, the conductor film 8b is thin in the connection hole 6b and the wiring grooves 10a and 10b with a small or no overhang in the upper part of the wiring grooves 10a and 10b. In addition, it can be applied without any unevenness. That is, the conductor film 8b can be deposited with high step coverage.

  As a fifth means, in combination with at least one of the first to fourth means described above, the semiconductor substrate 1 is cooled before or during the sputtering process for depositing the conductor film 8b. In the present embodiment, although not particularly limited, the temperature of the semiconductor substrate 1 is set to, for example, 30 ° C. or less, preferably 0 ° C. As a result, the film formation state of copper or copper alloy constituting the conductor film 8b becomes a solid state, and aggregation of copper or copper alloy can be suppressed, so that formation of discontinuous portions on the conductor film 8b is suppressed. It becomes possible to do.

  FIG. 22 shows a cross-sectional view when the conductor film 8b is deposited by the above-described means or a combination thereof. The conductor film 8b is deposited in the wiring groove 10a in a thin and uniform state. That is, the discontinuous portion of the conductor film 8b is not formed on the inner side surface (arrow A) and the bottom surface (arrow B) of the wiring groove 10a, and insufficient coverage does not occur. Further, no significant overhang is formed at the upper part (arrow C) of the wiring trench 10a.

  FIG. 23 shows a state in which the conductor film 8c made of copper or a copper alloy or the like is deposited by a plating method in such a state. The wiring groove 10a is filled with the conductor film 8c, and no void is generated. Therefore, the incidence of embedded wiring defects can be greatly reduced, and the yield and reliability of the semiconductor integrated circuit device can be improved.

Thus, according to the present embodiment, the following effects can be obtained.
(1) The conductive films 8b and 8c can be filled without generating voids in the fine wiring grooves 10a and 10b or the connection holes 6b.
(2) According to the above (1), it is possible to improve the accuracy of setting the electrical resistance of the embedded wirings 11a and 11b.
(3). For example, platinum, palladium, nickel, chromium, gold, silver or copper is added to the barrier metal 7b. For example, platinum, palladium, nickel, chromium, gold or silver is added to the conductor film 8b. By forming a thin conductor film made of, for example, platinum, palladium, nickel, chromium, gold or silver on the conductor film 8b, the conductor film 8c made of copper or a copper alloy by the subsequent plating method can be satisfactorily catalyzed. It becomes possible to adhere. This makes it possible to fill the conductor films 8b and 8c without generating voids in the fine wiring grooves 10a and 10b or the connection holes 6b.
(4) According to the above (1), (2) or (3), the defect occurrence rate in the embedded wiring (including the connection hole portion) 11a, 11b can be reduced, so that the yield and reliability of the semiconductor integrated circuit device can be reduced. Can be improved.
(5) By the above (1), it is possible to promote the miniaturization of the wiring grooves 10a, 10b or the connection holes 6b. Therefore, the degree of element integration can be improved, and it becomes possible to promote the miniaturization and high functionality of the semiconductor integrated circuit device.

(Embodiment 2)
24 to 29 are fragmentary cross-sectional views of the semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing process.

  In FIG. 24, a wiring groove 10a (or wiring groove 10b, connection hole 6b: hereinafter represented by wiring groove 10a) is formed in interlayer insulating film 5b (or interlayer insulating film 5c: hereinafter represented by interlayer insulating film 5b). Shows the state.

  As shown in FIG. 25, a conductor film 8b1 made of, for example, copper or a copper alloy is formed on such an interlayer insulating film 5b by sputtering. In the second embodiment, the conductor film 8b1 is a target film. The film forming process is interrupted when the film value is not reached. The sputtering method in this case may be a sputtering method to which the sputtering conditions of the first embodiment are added, or a normal sputtering method to which the sputtering conditions are not added. Prior to the deposition of the conductor film 8b1, the barrier metal described above may be deposited.

  Subsequently, by performing a heat treatment with the upper part of the wiring groove 10a being opened, as shown in FIG. 26, the conductor film 8b1 on the inner side surface of the wiring groove 10a is caused to flow to the bottom of the wiring groove 10a to thereby form the wiring groove. The conductor film 8b on the inner surface of 10a is divided.

  A conductor film 8b1 having a predetermined thickness is deposited on the bottom of the wiring groove 8b. Thereby, the wiring groove | channel 10a can be made shallow. That is, since the aspect ratio of the wiring groove 10a can be reduced, the wiring groove 10a can be satisfactorily filled with a conductor film formed by a subsequent plating method.

  Thereafter, by restarting the film forming process of the copper or copper alloy or the like by the sputtering method, the conductor film 8b2 is covered on the upper surface of the conductor film 8b1 and the side surface of the wiring groove 10a as shown in FIG. To wear.

  Also here, for example, platinum, palladium, nickel, chromium, gold, silver, or copper may be added to the barrier metal, and platinum, palladium, nickel, chromium, etc. may be added to the conductor film 8b2. Gold or silver may be added. Further, the conductor film 8b2 may be formed of a thin conductor film made of, for example, platinum, palladium, nickel, chromium, gold, or silver. By doing in this way, it becomes possible to adhere | attach the conductor film which consists of copper or copper alloy by the subsequent plating method favorably by a catalytic action. This method is particularly effective when an electroless plating method is used.

  After that, as shown in FIG. 28, the conductor film 8c is deposited on the conductor film 8b2 by the plating method or the like as in the first embodiment. Thereby, the fine and high aspect ratio wiring trench 10a can be sufficiently filled. Note that the thickness of the conductor film 8c is thicker than the sum of the conductor films 8b1 and 8b2 on the upper surface of the interlayer insulating film 5b (substantially flat region other than the grooves and holes).

  Next, the conductor films 8c, 8b2, and 8b1 (if there is a barrier metal) are removed by performing CMP processing or the like in the center of the first embodiment, and as shown in FIG. 29, in the wiring groove 10a. An embedded wiring 11a (or embedded wiring 11b) made of the conductor films 8b1, 8b2, 8c is formed.

In the second embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.
(1). By depositing a conductor film 8b1 having a predetermined thickness on the bottom of the wiring groove 10b, the wiring groove 10a can be made shallow, and the aspect ratio of the wiring groove 10a can be reduced. 10a can be satisfactorily embedded with the conductor film 8c by the subsequent plating method.

(Embodiment 3)
30 and 31 are fragmentary cross-sectional views of the semiconductor integrated circuit device according to still another embodiment of the present invention during the manufacturing process.

  In the third embodiment, the process up to FIG. 26 of the second embodiment is the same. In the subsequent steps, the conductor film 8b2 (see FIG. 27) described in the second embodiment is not deposited, As shown in FIG. 30, a conductor film 8c is deposited on the interlayer insulating film 5b (including the inside of the wiring trench 10a) by the same plating method as in the first and second embodiments. The wiring groove 10a is filled with a conductor film 8c.

  Thereafter, as shown in FIG. 31, the conductor films 8c and 8b1 (or the barrier metal if there is a barrier metal) are shaved by performing a CMP process or the like as in the first and second embodiments, as shown in FIG. Then, an embedded wiring 11a (or embedded wiring 11b) made of the conductor films 8b1 and 8c is formed in the wiring groove 10a.

  As a modification of the third embodiment, the temperature of the semiconductor substrate 1 is raised during the formation of the conductor film 8b1 by the sputtering method described in the first and second embodiments, so that the conductor film 8b1 is formed. After the aspect ratio of the buried wiring groove 10a is reduced to a middle position of the wiring groove 10a, the conductive film 8c is deposited by the same plating method as in the first and second embodiments so that the wiring groove 10a is buried. good.

  In the third embodiment and the modification thereof, it is possible to obtain the same effect as in the first and second embodiments.

(Embodiment 4)
FIG. 32 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to still another embodiment of the present invention during the manufacturing process.

  In the fourth embodiment, the processing up to FIG. 26 of the second embodiment is the same, and then the upper surface of the interlayer insulating film 5b in the conductor film 8b1 (see FIG. 26) described in the second embodiment (see FIG. 26). The conductor film 8b1 in a substantially flat region excluding the inside of the wiring trench 10a is removed by a CMP method or the like.

  After this processing step, as shown in FIG. 32, the conductor film 8b1 is left only at the bottom of the wiring groove 10a.

  As a result, the wiring groove 10a can be made shallower than in the second and third embodiments because the conductor film 8b1 is not present on the upper surface of the interlayer insulating film 5b (substantially flat region excluding the inside of the wiring groove 10a). . That is, since the aspect ratio of the wiring groove 10a can be further reduced, the wiring groove 10a can be more satisfactorily filled with a conductor film formed by plating.

  Subsequently, a conductive film for wiring formation made of, for example, copper or copper alloy is deposited by the same plating method as in the first to third embodiments, so that the conductive film is selectively placed only in the wiring groove 10a. It becomes possible to grow. Thereby, the fine and high aspect ratio wiring trench 10a can be sufficiently filled. The completed drawing in the fourth embodiment is the same as that in FIG. 31, and the conductor film corresponds to the conductor film 8c.

In the fourth embodiment as described above, the following effects can be obtained in addition to the effects obtained in the first to third embodiments.
(1) By depositing a conductor film 8b1 having a predetermined thickness on the bottom of the wiring trench 10a and removing the conductor film 8b1 on the interlayer insulating film 5b, there is no conductor film on the interlayer insulating film 5b. Since the wiring groove 10a can be made shallower, the aspect ratio of the wiring groove 10a can be further reduced, and the wiring groove 10a can be satisfactorily filled with the conductor film 8c by plating.
(2) By depositing the conductor film 8b1 only on the bottom of the wiring groove 10a, the conductor film 8c is selectively grown only in the wiring groove 10a during the subsequent deposition process of the conductor film 8c by plating. It becomes possible to make it.

(Embodiment 5)
33 to 36 are fragmentary cross-sectional views of the semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing process.

  In the fifth embodiment, the steps up to FIG. 24 are the same as those in the first to fourth embodiments, and in the subsequent process, for example, before or during the formation of a conductor film made of copper or a copper alloy by sputtering. By performing the sputter etching process, as shown in FIG. 33, the interlayer insulating film 5b above the wiring groove 10a is etched, and the upper surface of the interlayer insulating film 5b and the inner surface of the wiring groove 10a are formed above the fine wiring groove 10a. A taper (inclination) is formed at the corner formed by

  Thereby, since the opening area (width of the opening) of the fine wiring groove 10a can be increased, the step coverage of the conductor film made of copper or copper alloy in the wiring groove 10a can be improved.

  After the conductor film 8b is formed on the interlayer insulating film 5b by the sputtering method similar to the first and second embodiments as shown in FIG. 34, the conductor film 8b is formed on the interlayer insulating film 5b as shown in FIG. The conductor film 8c is deposited by the same plating method as in the first to fourth embodiments. Thereby, the fine and high aspect ratio wiring trench 10a can be sufficiently filled.

  Thereafter, the conductor films 8c and 8b1 (or the barrier metal if there is a barrier metal) are shaved by performing a CMP process or the like in the same manner as in the first embodiment, and the conductor is formed in the wiring groove 10a as shown in FIG. An embedded wiring 11a (or embedded wiring 11b) made of the films 8b and 8c is formed.

In the fifth embodiment as described above, the following effects can be obtained in addition to the effects obtained in the first to fourth embodiments.
(1) By performing a sputter etching process before or during the formation of the conductor film 8b made of copper or copper alloy by sputtering, and forming a taper (inclination) at the upper corner of the fine wiring groove 10a. Since the opening area of the upper part of the fine wiring groove 10a can be increased, the step coverage of the conductor film 8b in the wiring groove 10a can be improved. As a result, the wiring groove 10a can be satisfactorily filled with the conductor film 8c by the subsequent plating method.

(Embodiment 6)
37 to 40 are fragmentary cross-sectional views of the semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing process.

  In the sixth embodiment, the processing up to FIG. 24 of the second embodiment is the same. In the subsequent steps, as shown in FIG. 37, a conductor film 8b made of, for example, copper or a copper alloy is formed by sputtering. At the time of film formation, a bias voltage is applied to the semiconductor substrate 1 side (lower electrode of the sputtering apparatus), so that film formation processing is performed while causing both effects of film formation and sputter etching (so-called “so-called”). Bias sputtering method is used).

  According to such a method, an overhang portion (portion indicated by a broken line) of the conductor film 8b deposited on the upper portion of the opening of the wiring groove 10a can be removed by the sputter etching action. Therefore, as shown in FIG. 8b can be deposited in the fine wiring groove 10a in a thin and non-uniform state. That is, the step coverage of the conductor film 8b in the wiring groove 10a can be improved.

  However, the sputtering conditions described in the first embodiment may be added also in the bias sputtering method described above. Thereby, the step coverage of the conductor film 8b in the wiring groove 10a can be further improved. Further, the barrier metal described above may be deposited prior to the deposition of the conductor film 8b.

  Thereafter, as shown in FIG. 39, the conductor film 8c is deposited on the conductor film 8b by the same plating method as in the first to fifth embodiments. Thereby, the fine and high aspect ratio wiring trench 10a can be sufficiently filled.

  Next, by conducting a CMP process in the same manner as in the first embodiment, the conductor films 8c and 8b (if there is a barrier metal, the barrier metal) are shaved, and as shown in FIG. 40, the conductor film 8b is formed in the wiring groove 10a. , 8c (embedded wiring 11b) is formed.

In the sixth embodiment, in addition to the effects obtained in the first embodiment and the like, the following effects can be obtained.
(1). A conductor film 8b made of copper or a copper alloy is formed by bias sputtering, thereby removing an overhang portion of the conductor film 8b formed on the upper part of the wiring groove 10a or re-sputtering. Therefore, the step coverage of the conductor film 8b in the wiring groove 10a can be improved. As a result, the wiring groove 10a can be satisfactorily filled with the conductor film 8c by the subsequent plating method.

(Embodiment 7)
41 to 43 are fragmentary cross-sectional views of the semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing process.

  In the seventh embodiment, the processing up to FIG. 24 of the first and second embodiments is the same, and in the subsequent steps, as shown in FIG. 41, for example, platinum, palladium, nickel, chromium, gold or silver A thin conductor film 8d made of is deposited by CVD, sputtering, plating, or the like. By doing in this way, it becomes possible to adhere | attach the conductor film which consists of copper or copper alloy by the subsequent plating method favorably by a catalytic action.

  The conductor film 8d is a seed crystal layer of a conductor film that is subsequently deposited by a plating method, and is deposited relatively thinly so as not to fill the wiring groove 10a. When the conductor film 8d is formed by sputtering, the sputtering conditions of the first embodiment may be added. Thereby, the step coverage of the thin conductor film 8d can be improved.

  Prior to the deposition of the conductor film 8d, a barrier metal may be deposited on the upper surface of the interlayer insulating film 5b including the inside of the wiring trench 10a. The method may be applied in the same manner as in the first embodiment. Further, platinum, palladium, nickel, chromium, gold, silver or copper may be added to the barrier metal.

  Subsequently, as shown in FIG. 42, after the conductor film 8c is deposited on the conductor film 8d by the plating method or the like as in the first to sixth embodiments, the CMP is performed as in the first to sixth embodiments. The conductor films 8c and 8d and the barrier metal 7b are shaved by performing a treatment or the like, and as shown in FIG. 43, an embedded wiring 11a composed of the barrier metal 7b and the conductor films 8d and 8c is formed in the wiring groove 10a.

  According to the seventh embodiment, it is possible to obtain the same effects as those of the first embodiment.

(Embodiment 8)
44 and 45 are fragmentary cross-sectional views of the semiconductor integrated circuit device according to still another embodiment of the present invention during the manufacturing process.

  In the eighth embodiment, as shown in FIG. 44, the embedded wiring 11a in the first layer is composed of the barrier metal 7b, the conductor film 8b (see FIG. 9), the conductor film 8c, and the conductor film 8d. . The conductor film 8d is made of, for example, platinum, palladium, nickel, chromium, gold, or silver, for example, and is formed so as to cover the upper surface of the conductor film 8c, that is, on the embedded wiring 11a. The conductor film 8d is exposed from the bottom of the connection hole 6b. In such a structure, it is not necessary to consider step coverage when depositing the conductor film 8d.

  By providing the conductor film 8d in this manner, it is possible to satisfactorily deposit a conductor film made of copper or a copper alloy by a plating method by a catalytic action. This method is particularly effective when a subsequent conductive film made of copper or copper alloy is formed by an electroless plating method.

  Thereafter, as shown in FIG. 45, the conductor film 8c is deposited on the conductor film 8d by the same plating method as in the fourth embodiment, so that the conductor is selectively formed in the connection hole 6b and the wiring groove 10a. A film 8c is formed. Thus, the fine and high aspect ratio wiring trench 10a is sufficiently buried, and the buried wiring 11a made of the conductor film 8c is formed in the connection hole 6b and the wiring trench 10a.

  According to the eighth embodiment, it is possible to obtain the same effects as those of the first embodiment.

(Embodiment 9)
46 to 48 are fragmentary cross-sectional views of the semiconductor integrated circuit device according to still another embodiment of the present invention during the manufacturing process.

  In the ninth embodiment, as shown in FIG. 46, after barrier metal 7b is deposited in the same manner as in the first embodiment, a conductor film 8b is deposited thereon as in the first embodiment. However, the thickness of the conductor film 8b is made thicker than that in the first embodiment, and the upper surface (substantially flat region) of the interlayer insulating film 5b is made of a conductor film made of copper or a copper alloy by the plating method described later. Also thicken. The thickness of the conductor film 8b here is, for example, about 5000 to 6000 mm. However, the inside of the wiring groove 10a is not completely filled with the conductor film 8b. As a result, the conductor film 8b is deposited thickly on the bottom of the wiring groove 10a.

  Subsequently, as shown in FIG. 47, the conductor film 8c is deposited on the conductor film 8b by the same plating method as in the first embodiment. Thereby, the fine and high aspect ratio wiring trench 10a is sufficiently embedded. Note that, on the upper surface (substantially flat region) of the interlayer insulating film 5b, the thickness of the conductor film 8c is thinner than the thickness of the conductor film 8b. The thickness of the conductor film 8c is, for example, about 1000 to 2000 mm. Prior to the deposition of the conductor film 8b, the conductor film 8d (see FIG. 41) described in the sixth embodiment may be deposited.

  Thereafter, the conductor films 8c and 8b are shaved by performing the CMP process in the same manner as in the first embodiment, and as shown in FIG. 48, the wiring groove 10a is filled with the barrier metal 7b and the conductor films 8b and 8c. The buried wiring 11a is formed.

  According to the ninth embodiment, it is possible to obtain the same effect as that of the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to ninth embodiments, the case where the SOI substrate is used as the semiconductor substrate has been described. However, the present invention is not limited to this, and for example, a normal semiconductor substrate composed of only a single semiconductor may be used. An epitaxial substrate in which a thin epitaxial layer is provided on a semiconductor substrate may be used.

  In the sixth embodiment, a method of forming a conductor film made of copper or a copper alloy by a bias sputtering method is adopted. However, the present invention is not limited to this. For example, the conductor film is made of sputtered particles. The film may be formed by ionization or may be formed by vapor deposition.

  In the above description, the case where the invention made by the present inventor is applied to the semiconductor integrated circuit device technology, which is the field of use behind it, has been described. However, the present invention is not limited to this. Applicable to etc.

  The present invention can be applied to the manufacturing industry of semiconductor integrated circuit devices.

It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5; 7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6; FIG. FIG. 8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12; 14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13; FIG. FIG. 15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 15; It is explanatory drawing for demonstrating the sputtering condition setting of this invention. It is explanatory drawing for demonstrating the sputtering condition setting of this invention. It is explanatory drawing for demonstrating the sputtering condition setting of this invention. It is explanatory drawing for demonstrating the sputtering condition setting of this invention. It is explanatory drawing for demonstrating the sputtering condition setting of this invention. It is a principal part expanded sectional view in the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. It is a principal part expanded sectional view in the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 25 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 24; FIG. 26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 26; FIG. 28 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 28; It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 31 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 30; It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is further another embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is further another embodiment of this invention. FIG. 34 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 35; It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is further another embodiment of this invention. FIG. 38 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 37; FIG. 39 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 38; FIG. 40 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 39; It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is further another embodiment of this invention. FIG. 42 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process following that of FIG. 41; FIG. 43 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 42; It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is further another embodiment of this invention. FIG. 45 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 44; It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is further another embodiment of this invention. FIG. 47 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 46; It is principal part sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is further another embodiment of this invention. It is explanatory drawing for demonstrating the malfunction at the time of embedded wiring formation which this inventor examined. It is explanatory drawing for demonstrating the malfunction at the time of embedded wiring formation which this inventor examined.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Support substrate 1b Insulating layer 1c Semiconductor layer 2a Groove 2b Insulating film 3a Semiconductor region 3b Gate insulating film 3c Gate electrode 4a Side wall 4b Cap insulating film 5a Interlayer insulating film 5b Interlayer insulating film 5c Interlayer insulating film 6a Connection hole 6b Connection hole 7a Barrier metal 7b Barrier metal (barrier conductor film)
8a Conductor film 8b Conductor film (first conductor film)
8b1 conductor film 8b2 conductor film 8c conductor film (second conductor film)
8d Conductor film (third conductor film)
9a Plug 10a, 10b Wiring groove 11a, 11b Embedded wiring 12 Barrier insulating film Q MOS • FET

Claims (4)

A method of manufacturing a semiconductor integrated circuit device having a structure in which a buried wiring is provided in at least one of a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate,
(A) forming at least one of a wiring groove or a connection hole in the insulating film;
(B) a first conductor made of a conductive material containing copper to which at least one of platinum, palladium, nickel, chromium, gold, or silver is added in at least one of the wiring groove or connection hole and on the insulating film; Depositing the film by physical vapor deposition;
(C) after forming the first conductor film, depositing a second conductor film made of copper or a conductor material containing copper by a plating method;
(D) forming a buried wiring composed of the first conductor film and the second conductor film in the wiring groove by cutting the first conductor film and the second conductor film,
The semiconductor film characterized in that the deposited film thickness of the first conductor film on the insulating film is equal to or greater than the deposited film thickness of the second conductor film. A method for manufacturing an integrated circuit device.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the film thickness of the first conductor film is not less than 500 angstroms and not more than 1500 angstroms.   3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the insulating film is a coating film, an organic film, a fluorine-added CVD oxide film, a silicon nitride film, or a combination thereof. A method of manufacturing a semiconductor integrated circuit device.   4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor substrate is an SOI substrate or an epitaxial substrate. 5.

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