JP2012069846A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress embedding defects in a plating process.SOLUTION: The method of manufacturing a semiconductor device comprises: an opening part forming process in which the opening part is formed on an interlayer insulating film 320 provided on a semiconductor substrate 100; a barrier layer forming process for forming a barrier layer 340 on the upper face of the opening part; and a wiring seed layer forming process for forming a wiring seed layer on the barrier layer 340. In addition, the barrier layer forming process includes a selective film-forming process and a sputter etching process. During the selective film-forming process in the barrier layer 340, a film-forming is selectively performed only to a plane part 342 of the opening part in the barrier layer 340. Then, during the sputter etching process in the barrier layer 340, sputtering particles in the barrier layer 340 are laminated in a sidewall part 344 of the opening part while sputter etching is performed with respect to the barrier layer 340 of the plane part 342.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, as a wiring technology for semiconductor devices, a multilayer wiring structure using a combination of a copper wiring called a dual damascene method and a low dielectric constant interlayer insulating film has been adopted. As a problem of copper wiring in the dual damascene method, improvement of burying defects during plating and electromigration resistance are required.

  As a prior art for the purpose of improving electromigration resistance, Patent Document 1 and the like can be cited. In Patent Document 1, in the step of forming a barrier layer on the inner surface of the opening formed in the interlayer insulating film by sputtering, the barrier layer material deposited on the bottom of the opening is etched by sputtering, and the barrier layer is formed on the side wall of the opening. A method of depositing material is disclosed. According to this, since the barrier layer is not formed on the bottom surface of the opening, it is described that electromigration that has occurred between the upper and lower copper wirings when the barrier layer is interposed can be suppressed.

JP 2001-284449 A

  However, in the method described in Patent Document 1, an overhang portion is generated at the end portion where the flat portion of the opening and the side wall portion are in contact with each other when the barrier layer is formed. In this case, since the overhang portion grows and closes before all the openings are filled in the plating process, there is a possibility that voids are formed inside the wiring.

According to the present invention,
Forming an opening in an interlayer insulating film provided on the semiconductor substrate;
A barrier layer forming step of forming a barrier layer on the upper surface of the opening;
A wiring seed layer forming step of forming a wiring seed layer on the barrier layer;
The barrier layer forming step includes
A selective film forming step of selectively forming the barrier layer only on the flat surface of the opening;
A sputter etching step of depositing sputter particles of the barrier layer on the side wall of the opening while sputter etching the barrier layer of the planar portion;
A method for manufacturing a semiconductor device, comprising:

According to the present invention,
Forming an opening in an interlayer insulating film provided on the semiconductor substrate;
A barrier layer forming step of forming a barrier layer on the upper surface of the opening;
A wiring seed layer forming step of forming a wiring seed layer on the barrier layer;
The wiring seed layer forming step includes
A selective film formation step of selectively forming the wiring seed layer only on the flat surface of the opening;
A sputter etching step of depositing sputtered particles of the wiring seed layer on the side wall of the opening while sputter etching the wiring seed layer of the planar portion;
A method for manufacturing a semiconductor device, comprising:

  According to the present invention, the barrier layer or the wiring seed layer is formed by the selective film formation step and the sputter etching step, so that the end portion where the flat portion of the opening and the side wall are in contact with each other does not have an overhang shape. Therefore, in the subsequent plating step, no void is generated until all the openings are buried. As described above, it is possible to suppress an embedding defect in the plating process.

  According to the present invention, it is possible to suppress poor embedding in the plating process.

It is sectional drawing which shows the structure of the semiconductor device which concerns on this embodiment. 3 is a flowchart of a method for manufacturing a semiconductor device of the present embodiment. It is sectional drawing of the selective film-forming process of the barrier layer in a barrier layer formation process. It is sectional drawing of the sputter etching process of the barrier layer in a barrier layer formation process. It is sectional drawing after a barrier layer formation process. It is sectional drawing of the selective film-forming process of the wiring seed layer in a wiring seed layer formation process. It is sectional drawing after a wiring seed layer formation process. It is sectional drawing after a wiring formation process. It is sectional drawing in the plating process of a comparative example. It is sectional drawing after the wiring formation process of a comparative example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
The semiconductor device used in this embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the present embodiment. This semiconductor device includes a semiconductor substrate 100, a semiconductor element provided on the semiconductor substrate 100, an interlayer insulating film 320 provided on the semiconductor substrate 100, and a barrier formed in an opening formed in the interlayer insulating film 320. A layer 340; and a wiring 440 formed on the barrier layer 340. Further, the angle θ between the flat surface portion 342 and the side wall portion 344 of the barrier layer 340 is 90 degrees or more, and it is not in an overhang shape.

  As will be described later, in the method of manufacturing a semiconductor device according to the present embodiment, the barrier layer 340 or the wiring seed layer 420 (see FIG. 6) serving as the seed of the wiring 440 is formed by the selective film formation process and the sputter etching process. . According to this, the end part where the flat part 342 and the side wall part 344 of the opening part do not have an overhang shape. Therefore, in the subsequent plating step, no void is generated until all the openings are buried. Therefore, the embedding defect of a plating process can be suppressed.

  The opening here refers to a groove or a connection hole. In the following, either is acceptable unless otherwise specified.

  Next, referring to FIG. 1, the details of the semiconductor device used in this embodiment will be described. The semiconductor substrate 100 is, for example, a silicon substrate. The semiconductor substrate 100 includes, for example, a field effect transistor (FET) including a source region 42, a drain region 44, a gate insulating film 22 formed on the semiconductor substrate 100, and a gate electrode 20 formed on the gate insulating film 22. ) Is formed. Side wall insulating films 24 are formed on both side surfaces of the gate electrode 20. Each FET is isolated from other elements by an element isolation region 60 formed in the semiconductor substrate 100. Note that the source region 42 and the drain region 44 include an extension region (not shown).

  A base insulating film 220 is formed on the semiconductor substrate 100. In the base insulating film 220, a base layer 200 having contacts 210, a base barrier layer 240, and a base wiring 260 is formed. For example, as shown in FIG. 1, the contact 210 electrically connects the source region 42 and the drain region 44 to the underlying wiring 260 formed thereabove. Known materials can be used for the material, thickness, and the like constituting the underlayer 200 in the present embodiment.

  An interlayer insulating film 320 is provided on the base insulating film 220, and an opening is provided up to the base wiring 260. Note that an etching stopper film (not shown) may be provided between the via layer 300 and the wiring layer 400 shown in FIG.

  The thickness of the interlayer insulating film 320 in this embodiment is, for example, 100 to 300 nm. Further, the thickness of the via layer 300 is, for example, 40 to 100 nm, and the via diameter of the opening is, for example, 20 to 70 nm.

  In addition, a barrier layer 340 and a wiring 440 are provided in the opening of the interlayer insulating film 320, and the wiring 440 and the base wiring 260 are connected via the barrier layer 340.

  Examples of the material of the barrier layer 340 include Ta and TaN, and other examples include Ti, TiN, Hf, HfN, ZrN, ZrN, Ru, RuN, and Mn. The thickness of the barrier layer 340 is, for example, 3 to 15 nm. The barrier layer 340 may have a two-layer structure. For example, TaN may be formed from the interlayer insulating film 320 side to have a two-layer structure of Ta / TaN.

  Here, the barrier layer 340 has a flat surface portion 342 and a side wall portion 344, and an angle θ at which these contact each other is 90 degrees or more. That is, an end portion where the flat portion 342 and the side wall portion 344 of the opening are in an overhang shape is not formed, and no void is generated in the wiring 440.

  Next, the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIGS. The manufacturing method of the semiconductor device of this embodiment includes the following steps. A step of forming an opening in an interlayer insulating film 320 provided on the semiconductor substrate 100, a barrier layer forming step of forming a barrier layer 340 on the upper surface of the opening, and a wiring for forming a wiring seed layer 420 on the barrier layer 340 A seed layer forming step; The barrier layer forming process includes a selective film forming process and a sputter etching process. In the selective film formation step of the barrier layer 340, the barrier layer 340 is selectively formed only on the flat portion 342 of the opening. Next, in the sputter etching process of the barrier layer 340, sputter particles of the barrier layer 340 are deposited on the side wall part 344 of the opening while sputter etching the barrier layer 340 of the flat part 342. Details will be described below.

  FIG. 2 is a flowchart of the semiconductor device manufacturing method of the present embodiment. The outline of the semiconductor manufacturing method will be described with reference to FIG. The semiconductor device manufacturing method of the present embodiment includes a semiconductor element forming step (S100), a base layer forming step (S200), an interlayer insulating film forming step (S300), an opening forming step (S400), and a barrier layer forming step (S500). ), A wiring seed layer forming step (S600), and a wiring forming step (S700).

  First, for example, a semiconductor element forming step (S100) for forming the above-described FET is performed. After the element isolation region 60 is formed on the semiconductor substrate 100, the gate insulating film 22 is formed by, for example, thermal oxidation. Next, for example, a polycrystalline silicon film is formed, and the gate electrode 20 is formed using a lithography technique and a RIE (Reactive Ion Etching) technique. Ion implantation is performed using the gate electrode 20 as a mask, and extension regions (not shown) of the source region 42 and the drain region 44 are formed. Next, sidewall insulating films 24 are formed on both side surfaces of the gate electrode 20 by sequentially depositing and etching back a silicon nitride film or a silicon oxide film by, for example, CVD (Chemical Vapor Deposition). Next, ion implantation is performed using the gate electrode 20 and the sidewall insulating film 24 as a mask, and after activation annealing, a source region 42 and a drain region 44 are formed, thereby forming a semiconductor element (S100).

  In the base layer forming step (S200), the base insulating film 220 is formed by a CVD method or the like. A resist pattern is formed on the base insulating film 220, and an opening for the contact 210 is formed by RIE. Next, after removing the resist pattern, a conductor is embedded in the opening for the contact 210. Usually, the conductor is embedded by depositing a conductor by electrolytic plating after forming a seed film (not shown) by sputtering. Next, planarization is performed by CMP (Chemical Mechanical Polishing). Similarly, a base insulating film 220 is formed again, and an opening for the base wiring 260 is formed by RIE. Next, the base barrier layer 240 is formed, and the base wiring 260 is formed by a plating process. Next, the base layer 200 is formed by planarization by CMP (S200).

  Next, an interlayer insulating film 320 is formed on the base layer 220 by a film formation method similar to that of the base insulating film 220 (S300). Note that an etching stopper film (not shown) may be formed in the middle of the interlayer insulating film 320.

  Next, an opening is formed in the interlayer insulating film 320 by RIE (S400).

  Next, the barrier layer 340 is formed (S500). Next, a wiring seed layer 420 is formed (S600). Details of these steps will be described later with reference to FIGS.

  Next, a plating process is performed using the wiring seed layer 420 as a seed. Next, a planarization process by CMP is performed to form the wiring 440 (S700).

  Next, details of the barrier layer forming step (S500) will be described with reference to FIGS. Hereinafter, in FIGS. 3 to 5 and similar FIGS. 7 to 10, the semiconductor elements are omitted for simplification.

  3 is a cross-sectional view of a barrier layer selective film forming step in the barrier layer forming step, FIG. 4 is a cross-sectional view of a sputter etching process of the barrier layer in the barrier layer forming step, and FIG. 5 is a view after the barrier layer forming step. FIG.

  An opening is formed in the interlayer insulating film 320 by the opening forming step (S400). First, as shown in FIG. 3, the selective deposition of the barrier layer 340 is performed. As the selective film formation, for example, anisotropic sputtering, a coating method, a selective plating method, or the like is used.

  Anisotropic sputtering is a film forming method in which sputtered particles are linear in the direction of the film forming substrate, such as long throw sputtering, collimator sputtering, or ionized sputtering. Long throw sputtering is a method that can prevent the influence of the reflection angle and the collision with the background atoms by increasing the distance between the electrodes of the target and the deposition substrate and lowering the pressure. Collimator sputtering is a method that can remove particles with a certain angle or more by placing a slit between the electrodes. Ionized sputtering is a method in which ionized sputtered particles are attracted by a substrate bias to increase the component in the direction of the film formation substrate.

  The application method is, for example, a method of forming a film as shown in FIG. 3 by applying a liquid organic material by spin coating and heating at 100 to 400 ° C.

  The selective plating method is, for example, a method of selectively growing the barrier layer 340 by applying a catalyst to a portion that becomes the flat portion 342 of the barrier layer 340 as shown in FIG.

  In the selective film formation process of the barrier layer 340, the film formation on the side wall portion 344 causes an overhang shape. Therefore, it is preferable that the film is formed thin on the side wall portion 344 or is not formed at all. For example, the planar portion 342 of the barrier layer 340 in the selective film formation step is formed to have a thickness of 3 nm to 15 nm and a sidewall portion 344 of 1 nm or less. Alternatively, the planar portion 342 is formed so as not to form a film on the side wall portion 344 within the above range. Note that the planar portion 342 includes a planar portion on the interlayer insulating film 320, a layered planar portion in the interlayer insulating film 320, and a planar portion on the bottom surface of the opening (upper surface of the base wiring 260), and includes the via layer 300 and the wiring layer. The part used as the bottom face of 400 is included.

  Further, for example, the film is formed so that the thickness of the flat portion 342 in the barrier layer 340 is approximately twice the target thickness of the side wall portion 344 to be formed later by sputter etching. For example, the thickness of the flat portion 342 in the initial barrier layer 340 is 3 to 15 nm. When the barrier layer has a Ta / TaN two-layer structure, TaN is, for example, 1 to 10 nm, and Ta is, for example, 2 to 20 nm.

Next, as shown in FIG. 4, a sputter etching process of the barrier layer 340 is performed. The sputtering gas is, for example, Ar, and the barrier layer 340 material that scatters is Ta. Ar ⁺ ions generated between the electrodes collide toward the substrate (broken arrows in FIG. 4), and the barrier layer 340 is sputtered to scatter the sputtered barrier layer material (Ta particles in FIG. 4). (Solid arrow in FIG. 4). Thereby, the barrier layer 340 is formed on the side wall portion 344.

  In the sputter etching process, the thickness of the flat portion 342 of the barrier layer 340 is decreased by the sputter etching, and the thickness of the side wall portion 344 is increased by the deposition of the sputtered barrier layer material. For example, when the initial thickness of the planar portion 342 is 10 nm, the planar portion 342 is etched by 5 nm to have a thickness of 5 nm, and the sidewall portion 344 is formed to have a thickness of 5 nm. When the barrier layer 340 has a two-layer structure of Ta / TaN (5 nm / 5 nm), the sputter etching is performed only on Ta, and TaN (5 nm) remains on the flat surface portion 342, and the side wall portion 344. A film of Ta (5 nm) is formed.

  As shown in FIG. 5, the angle θ between the flat portion 342 and the side wall portion 344 of the opening is 90 degrees or more. That is, the end portion where the flat surface portion 342 and the side wall portion 344 contact each other is not in an overhang shape.

  Next, details of the wiring seed layer forming step (S600) will be described. The barrier layer 340 is formed by the barrier layer forming step (S500) of FIG. A wiring seed layer 420 is formed on the barrier layer 340. The wiring seed layer 420 is a layer that serves as a seed in the plating process. For example, if the wiring material is copper, it is a copper sputtered thin film.

  If a conventional method is used in the wiring seed layer forming step, it can be formed by isotropic sputtering. The thickness of the wiring seed layer 420 is, for example, 10 to 60 nm.

  Further, the wiring seed layer forming step may be formed by a selective film forming step and a sputter etching step, similarly to the above-described barrier layer forming step. Hereinafter, the case where this step is applied in the wiring seed layer forming step will be described. FIG. 6 is a cross-sectional view of a selective seeding process for a wiring seed layer in the wiring seed layer forming process, and FIG. 7 is a cross-sectional view after the wiring seed layer forming process.

  First, as shown in FIG. 6, selective film formation of the wiring seed layer 420 is performed. A method similar to the method of selective film formation in the barrier layer 340 is used.

  In the selective film formation step of the wiring seed layer 420, it is desirable that the film is formed on the side wall part 424, which causes an overhang shape. . For example, in the selective film formation step, the planar portion 422 of the wiring seed layer 420 is formed so as to have a thickness of 10 nm to 60 nm and the sidewall portion 424 has a thickness of 1 nm or less. Alternatively, the planar portion 422 is formed so as not to form a film on the side wall portion 424 within the above range.

  Further, for example, the wiring seed layer 420 is formed so that the thickness of the planar portion 422 is about twice as large as the target thickness of the side wall portion 424 to be formed later by sputter etching. For example, the thickness of the flat portion 422 in the initial wiring seed layer 420 is 10 to 60 nm, and in the present embodiment, it is 20 nm.

  Next, a sputter etching process of the wiring seed layer 420 is performed. A method similar to the method of sputter etching in the barrier layer 340 is used, and the same mechanism is used.

  As shown in FIG. 7, in this embodiment, for example, the flat portion 422 is etched by 10 nm to have a thickness of 10 nm and the sidewall portion 424 is formed to have a thickness of 10 nm.

  Further, as shown in FIG. 7, the angle θ between the flat surface portion 422 of the opening and the side wall portion 424 is 90 degrees or more. That is, the end portion where the flat surface portion 422 and the side wall portion 424 are in contact with each other does not have an overhang shape.

  FIG. 8 shows a cross-sectional view after the wiring formation step. As shown in FIG. 8, a semiconductor device in which no voids are generated can be manufactured by the steps (S100) to (S700). In the above description, the example in which the selective film forming process and the sputter etching process are applied only to the barrier layer 340 or both of the barrier layer 340 and the wiring seed layer 420 has been described. Is possible. Although the dual damascene structure has been described above, the present invention can also be applied to a single damascene structure.

  Next, the effects of the present embodiment will be described in comparison with a comparative example. FIG. 9 is a cross-sectional view during the plating process of the comparative example, and FIG. In the comparative example, since the barrier layer 340 is formed using, for example, isotropic sputtering in the barrier layer forming step, the film is also formed on the side wall portion 344. As a result, as shown in FIG. 9, an overhang portion 346 is generated at the end portion where the flat portion 342 and the side wall portion 344 of the opening are in contact with each other.

  When the plating process is performed in a state where there is an overhang portion 346, as shown in FIG. 9, the overhang portion grows and closes before the entire opening portion is filled. Accordingly, even if the plating process is continued thereafter, the wiring material does not grow inside the wiring, and a void 442 is generated as shown in FIG.

  On the other hand, in the present embodiment, in the selective film formation step of the barrier layer 340, as shown in FIG. 3, the film is selectively formed only on the flat portion 342, and only 1 nm or less is formed on the side wall portion 344, or not formed at all. Not filmed. Therefore, as shown in FIG. 5, even when the sidewall portion 344 is formed in the sputter etching process of the barrier layer 340, the end portion where the flat portion 342 and the sidewall portion 344 of the opening are not in an overhang shape. The same applies to the selective film formation step of the wiring seed layer 420 (FIG. 6) and the sputter etching step (FIG. 7).

  Therefore, as shown in FIG. 8, in the subsequent plating step, no void is generated until all the openings are buried. As described above, it is possible to suppress an embedding defect in the plating process.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

20 Gate electrode 22 Gate insulating film 24 Side wall insulating film 42 Source region 44 Drain region 60 Element isolation region 100 Semiconductor substrate 200 Underlayer 210 Contact 220 Underlayer insulating film 240 Underlayer barrier layer 260 Underlayer wiring 300 Via layer 320 Interlayer insulating film 340 Barrier layer 342 Barrier layer flat surface portion 344 Barrier layer side wall portion 346 Barrier layer overhang portion 400 Wiring layer 420 Wiring seed layer 422 Wiring seed layer flat surface portion 424 Wiring seed layer side wall portion 440 Wiring 442 Void

Claims (6)

Forming an opening in an interlayer insulating film provided on the semiconductor substrate;
A barrier layer forming step of forming a barrier layer on the upper surface of the opening;
A wiring seed layer forming step of forming a wiring seed layer on the barrier layer;
The barrier layer forming step includes
A selective film forming step of selectively forming the barrier layer only on the flat surface of the opening;
A sputter etching step of depositing sputter particles of the barrier layer on the side wall of the opening while sputter etching the barrier layer of the planar portion;
A method for manufacturing a semiconductor device, comprising: Forming an opening in an interlayer insulating film provided on the semiconductor substrate;
A barrier layer forming step of forming a barrier layer on the upper surface of the opening;
A wiring seed layer forming step of forming a wiring seed layer on the barrier layer;
The wiring seed layer forming step includes
A selective film formation step of selectively forming the wiring seed layer only on the flat surface of the opening;
A sputter etching step of depositing sputtered particles of the wiring seed layer on the side wall of the opening while sputter etching the wiring seed layer of the planar portion;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
After the barrier layer forming step, the wiring seed layer forming step,
The wiring seed layer forming step includes
A second selective film forming step of selectively forming the wiring seed layer only on the flat surface of the opening;
A second sputter etching step of depositing sputtered particles of the wiring seed layer on the side wall of the opening while sputter etching the wiring seed layer of the planar portion;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device as described in any one of Claims 1-3,
The method of manufacturing a semiconductor device, wherein the selective film forming step is anisotropic sputtering. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3,
The method of manufacturing a semiconductor device, wherein the selective film formation step is a coating method. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3,
The method of manufacturing a semiconductor device, wherein the selective film formation step is a selective plating method.

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