JP5213316B2 - Semiconductor device having barrier metal spacer and method of manufacturing the same - Google Patents

Semiconductor device having barrier metal spacer and method of manufacturing the same Download PDF

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JP5213316B2
JP5213316B2 JP2006214517A JP2006214517A JP5213316B2 JP 5213316 B2 JP5213316 B2 JP 5213316B2 JP 2006214517 A JP2006214517 A JP 2006214517A JP 2006214517 A JP2006214517 A JP 2006214517A JP 5213316 B2 JP5213316 B2 JP 5213316B2
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insulating film
metal line
barrier metal
via plug
layer
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JP2007049148A (en
JP2007049148A5 (en
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▲ブン▼周 李
憲宗 申
熙晟 姜
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Samsung Electronics Co Ltd
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

本発明は、半導体素子に係り、特にダマシン構造の金属配線構造を有する半導体素子及びその製造方法に関する。例えば、本発明による半導体素子は、メモリ素子、例えばＤＲＡＭ、ＳＲＡＭまたはフラッシュメモリ、または多様な集積回路を有するロジック素子を含みうる。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a damascene metal wiring structure and a method for manufacturing the same. For example, the semiconductor device according to the present invention may include a memory device, such as a DRAM, SRAM or flash memory, or a logic device having various integrated circuits.

高速度の半導体素子に対する需要が増加するにつれて、さらに低い抵抗を有する金属配線構造が要求されている。特に、半導体素子の集積化が高くなるにつれて、金属配線構造はさらに複雑になっている。例えば、金属ラインが多層に配置された多層金属配線構造が利用されうる。これにより、金属ラインの抵抗の低下がさらに要求され、また、多層の金属ライン間のＲＣ遅延を低下させるための層間絶縁膜の誘電率の低下が要求されている。   As the demand for high-speed semiconductor devices increases, a metal wiring structure having a lower resistance is required. In particular, as the integration of semiconductor elements increases, the metal wiring structure becomes more complicated. For example, a multilayer metal wiring structure in which metal lines are arranged in multiple layers can be used. This further requires a reduction in the resistance of the metal lines, and a reduction in the dielectric constant of the interlayer insulating film in order to reduce the RC delay between the multilayer metal lines.

例えば、比抵抗の低い銅（Ｃｕ）は、従来のアルミニウム（Ａｌ）を利用した金属配線を代替する代案として利用されている。しかし、Ｃｕは、通常的なフォトリソグラフィ及びエッチングを利用したパターニングが容易でないという短所を有する。これにより、ビアホール及びトレンチにメッキ方式を利用してＣｕを埋め込み、それを平坦化してビアプラグ及び金属ラインを形成するダマシン工程が利用される。また、ＲＣ遅延を低下させるために、低誘電率の絶縁膜が層間絶縁膜として利用されている。しかし、低誘電率の絶縁膜を利用したダマシン工程には、次のような問題が発生しうる。   For example, copper (Cu) having a low specific resistance is used as an alternative to replacing metal wiring using conventional aluminum (Al). However, Cu has a disadvantage that patterning using ordinary photolithography and etching is not easy. Accordingly, a damascene process is used in which Cu is embedded in the via hole and the trench using a plating method, and the via hole and the trench are planarized to form a via plug and a metal line. In order to reduce the RC delay, an insulating film having a low dielectric constant is used as an interlayer insulating film. However, the following problems may occur in the damascene process using an insulating film having a low dielectric constant.

図１及び図２を利用して、従来の半導体素子の配線構造の問題点を説明する。図１及び図２に示すように、下部金属ライン１１５及び上部金属ライン１４０は、ビアプラグ１３５を利用して電気的に連結されうる。下部金属ライン１１５は、第１低誘電率の絶縁膜１１０に埋め込まれており、ビアプラグ１３５及び上部金属ライン１４０の連結構造は、第２低誘電率の絶縁膜１３０を貫通するように形成されうる。   A problem of a conventional wiring structure of a semiconductor device will be described with reference to FIGS. As shown in FIGS. 1 and 2, the lower metal line 115 and the upper metal line 140 may be electrically connected using a via plug 135. The lower metal line 115 is embedded in the first low dielectric constant insulating film 110, and the connection structure of the via plug 135 and the upper metal line 140 may be formed so as to penetrate the second low dielectric constant insulating film 130. .

第１低誘電率の絶縁膜１１０と第２低誘電率の絶縁膜１３０との間には、エッチング停止膜１２０及び酸化膜１２５が介在されうる。第１及び第２障壁金属膜１４５，１５０は、第２低誘電率の絶縁膜１３０とビアプラグ１３５との間、及び、第２低誘電率の絶縁膜１３０と第２金属ライン１４０との間に介在されうる。第１障壁金属膜１４５と第２障壁金属膜１５０との間に介在された再蒸着部分１１５´は、第１金属ライン１１５が再蒸着されて形成されうる。   An etch stop layer 120 and an oxide layer 125 may be interposed between the first low dielectric constant insulating film 110 and the second low dielectric constant insulating film 130. The first and second barrier metal films 145 and 150 are formed between the second low dielectric constant insulating film 130 and the via plug 135 and between the second low dielectric constant insulating film 130 and the second metal line 140. Can be intervened. A redeposition portion 115 ′ interposed between the first barrier metal film 145 and the second barrier metal film 150 may be formed by redepositing the first metal line 115.

酸化膜１２５は、第２低誘電率の絶縁膜１３０の形成ステップで初期に形成されうる。例えば、第２低誘電率の絶縁膜１３０は、ＳｉＣＯＨを含み、この場合、ＳｉＣＯＨの形成初期ステップには、Ｃ及びＨが含有されていないか、または微量含有された酸化膜１２５が形成されうる。しかし、酸化膜１２５は、ビアプラグ１３５の形成前に、ビアホール（図示せず）内の下部金属ライン１１５の洗浄ステップでエッチングされうる。例えば、洗浄ステップは、下部金属ライン１１５の酸化膜を除去するために、酸化膜エッチング液を利用して行われうる。したがって、洗浄ステップで、露出された酸化膜１２５の側壁部分がエッチングされて半円状のアンダーカットが形成されうる。   The oxide film 125 may be initially formed in the step of forming the second low dielectric constant insulating film 130. For example, the second low dielectric constant insulating film 130 includes SiCOH. In this case, an oxide film 125 that does not contain C or H or contains a trace amount can be formed in the initial step of forming SiCOH. . However, the oxide film 125 may be etched in a cleaning step of the lower metal line 115 in the via hole (not shown) before the via plug 135 is formed. For example, the cleaning step may be performed using an oxide film etchant to remove the oxide film of the lower metal line 115. Therefore, in the cleaning step, the exposed sidewall portion of the oxide film 125 may be etched to form a semicircular undercut.

これにより、エッジの塗布性が不良な物理気相蒸着（Ｐｈｙｓｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ：ＰＶＤ）法により形成される第１障壁金属層１４５がアンダーカット部分に蒸着されないという問題がある。その結果、再蒸着部分１１５´の第１金属、例えばＣｕがアンダーカット部分を通じて、酸化膜１２５を通って（矢印方向）低誘電率の絶縁膜１３０に拡散により浸透しうる。   Accordingly, there is a problem that the first barrier metal layer 145 formed by the physical vapor deposition (PVD) method having poor edge coating properties is not deposited on the undercut portion. As a result, the first metal of the redeposition portion 115 ′, for example, Cu, can penetrate through the undercut portion, the oxide film 125 (in the direction of the arrow), and the low dielectric constant insulating film 130 by diffusion.

これにより、隣接して配置された上部金属ライン１４０の間に漏れ電流が発生するか、または上部金属ライン１４０／第２低誘電率の絶縁膜１３０の配線信頼性が低下しうる。例えば、第２低誘電率の絶縁膜１３０でＴＤＤＢ（Ｔｉｍｅ Ｄｅｐｅｎｄｅｎｔ Ｄｉｅｌｅｃｔｒｉｃ Ｂｒｅａｋｄｏｗｎ）欠陥が発生しうる。   Accordingly, a leakage current may be generated between the adjacent upper metal lines 140 or the wiring reliability of the upper metal line 140 / the second low dielectric constant insulating film 130 may be reduced. For example, a TDDB (Time Dependent Dielectric Breakdown) defect may occur in the second low dielectric constant insulating film 130.

本発明が解決しようとする課題は、前述した問題点を克服するためのものであって、金属ラインの間の漏れ電流を減少させ、金属ラインと層間絶縁膜との間の配線信頼性を向上させる半導体素子を提供するところにある。   SUMMARY OF THE INVENTION The problem to be solved by the present invention is to overcome the above-mentioned problems, reduce the leakage current between the metal lines, and improve the wiring reliability between the metal lines and the interlayer insulating film. The present invention provides a semiconductor device to be provided.

本発明が解決しようとする他の課題は、経済性を有する前記半導体素子の製造方法を提供するところにある。   Another problem to be solved by the present invention is to provide a method of manufacturing the semiconductor device having economy.

前記課題を解決するための本発明の一態様によれば、半導体素子は、半導体基板に形成された第１金属ライン、及び、前記第１金属ラインの一部分と電気的に連結されたビアプラグを備える。前記半導体素子は、前記第１金属ライン上に形成され、少なくとも前記第１金属ラインの一部分を露出するウィンドウを含むエッチング停止膜、及び、前記エッチング停止膜上に形成され、前記第１金属ラインの一部分を露出するように、前記ウィンドウと連結されたビアホールを含む層間絶縁膜をさらに備える。前記半導体素子は、前記ビアホール内の前記露出された層間絶縁膜の側壁を覆っており、前記第１金属ラインの一部分を露出し、前記ウィンドウ内の前記露出されたエッチング停止膜の少なくとも側壁の下端を露出する第１障壁金属スペーサをさらに備える。前記ビアプラグは、少なくとも前記ビアホール及び前記ウィンドウを埋め込み、前記第１金属ラインの一部分と電気的に連結され、前記層間絶縁膜と接触しない。   According to an aspect of the present invention for solving the above-described problem, a semiconductor device includes a first metal line formed on a semiconductor substrate and a via plug electrically connected to a portion of the first metal line. . The semiconductor device is formed on the first metal line, and includes an etching stop film including a window exposing at least a portion of the first metal line, and the semiconductor element is formed on the etching stop film. An interlayer insulating film including a via hole connected to the window is further provided to expose a portion. The semiconductor element covers a side wall of the exposed interlayer insulating film in the via hole, exposes a part of the first metal line, and at least a lower end of the side wall of the exposed etching stop film in the window. A first barrier metal spacer that exposes the substrate. The via plug fills at least the via hole and the window, is electrically connected to a part of the first metal line, and does not contact the interlayer insulating film.

前記課題を解決するための本発明の他の態様によれば、半導体基板上に形成された第１金属ラインと、前記第１金属ライン上に形成され、少なくとも前記第１金属ラインの一部分を露出するウィンドウを含むエッチング停止膜と、前記エッチング停止膜上に形成され、前記第１金属ラインの一部分を露出するように前記ウィンドウと連結されたビアホール、及び、前記ビアホールの上部を横切って形成され、少なくとも一部分が前記ビアホールと連結されたトレンチを備える層間絶縁膜と、前記ビアホール及び前記トレンチ内の前記露出された前記層間絶縁膜の側壁を覆っており、前記第１金属ラインの一部分を露出し、前記ウィンドウ内の前記露出されたエッチング停止膜の少なくとも側壁の下端を露出する第１障壁金属スペーサと、前記ビアホール及び前記ウィンドウを埋め込み、前記第１金属ラインの一部分と電気的に連結され、前記層間絶縁膜と接触しないビアプラグと、少なくとも前記トレンチを埋め込み、前記ビアプラグと電気的に連結され、前記層間絶縁膜と接触しない第２金属ラインと、を備える半導体素子が提供される。   According to another aspect of the present invention for solving the above-mentioned problem, a first metal line formed on a semiconductor substrate, and formed on the first metal line, at least a part of the first metal line is exposed. An etch stop layer including a window, a via hole formed on the etch stop layer and connected to the window so as to expose a portion of the first metal line, and an upper portion of the via hole. Covering at least a portion of the interlayer insulating film including a trench connected to the via hole; and the sidewall of the exposed interlayer insulating film in the via hole and the trench; exposing a portion of the first metal line; A first barrier metal spacer exposing at least a lower end of a side wall of the exposed etch stop layer in the window; A via plug embedded in the hole and the window and electrically connected to a portion of the first metal line and not in contact with the interlayer insulating film; and at least the trench embedded and electrically connected to the via plug; and the interlayer insulating film And a second metal line not in contact with the semiconductor device.

前記他の課題を解決するための本発明の一態様によれば、半導体基板上に第１金属ラインを形成するステップと、前記第１金属ライン上にエッチング停止層を形成するステップと、前記エッチング停止層上に電気的絶縁層を形成するステップと、前記電気的絶縁層上に層間絶縁層を形成するステップと、前記エッチング停止層の第１部分を露出する開口を形成するように、前記層間絶縁層及び前記電気的絶縁層を順次に選択的にエッチングするステップと、前記開口の側壁上及び前記エッチング停止層の第１部分の真上に第１障壁金属層を形成するステップと、前記エッチング停止層の第１部分から前記第１金属障壁層の一部分を選択的に除去するステップと、前記第１障壁金属層をエッチングマスクとして利用して、前記第１金属ラインの一部分の露出に十分な時間、前記エッチング停止層の第１部分を選択的にエッチングするステップと、前記開口内に第２金属ラインを形成するステップと、を含む半導体素子の製造方法が提供される。   According to one aspect of the present invention for solving the other problems, a step of forming a first metal line on a semiconductor substrate, a step of forming an etching stop layer on the first metal line, and the etching Forming an electrical insulation layer on the stop layer; forming an interlayer insulation layer on the electrical insulation layer; and forming an opening exposing the first portion of the etch stop layer. Selectively and sequentially etching an insulating layer and the electrically insulating layer; forming a first barrier metal layer on a sidewall of the opening and directly over a first portion of the etching stop layer; and Selectively removing a portion of the first metal barrier layer from the first portion of the stop layer; and using the first barrier metal layer as an etch mask. A method of manufacturing a semiconductor device is provided that includes selectively etching a first portion of the etch stop layer for a time sufficient to expose the portion, and forming a second metal line in the opening. .

前記他の課題を解決するための本発明の他の態様によれば、半導体基板上に第１金属ラインを形成するステップと、前記第１金属ライン上に異なる物質からなる第１及び第２電気的絶縁層を形成するステップと、前記第１電気的絶縁層の一部分を露出する開口を画定するように十分な時間、前記第２電気的絶縁層を選択的にエッチングするステップと、前記開口の側壁上及び前記第１電気的絶縁層の一部分の真上に第１障壁金属層を形成するステップと、前記第１電気的絶縁層の一部分から前記第１障壁金属層の一部分を選択的に除去するステップと、前記第１障壁金属層をエッチングマスクとして利用して、前記第１金属ラインの一部分の露出に十分な時間、前記第１電気的絶縁層の一部分を選択的にエッチングするステップと、前記開口内に第２金属ラインを形成するステップと、を含む半導体素子の製造方法が提供される。   According to another aspect of the present invention for solving the other problems, a step of forming a first metal line on a semiconductor substrate, and first and second electric materials made of different materials on the first metal line. Forming a conductive insulating layer; selectively etching the second electrically insulating layer for a time sufficient to define an opening exposing a portion of the first electrically insulating layer; and Forming a first barrier metal layer on a sidewall and directly over a portion of the first electrically insulating layer; and selectively removing a portion of the first barrier metal layer from a portion of the first electrically insulating layer. Selectively etching a portion of the first electrically insulating layer for a time sufficient to expose a portion of the first metal line using the first barrier metal layer as an etch mask; The opening The method of manufacturing a semiconductor device comprising forming a second metal line, there is provided a.

本発明による半導体素子によれば、第１絶縁膜には、従来のようなアンダーカットがなく、第１障壁金属スペーサは、第１絶縁膜の側壁を覆っている。これにより、ビアプラグ及び上部金属ラインの金属、例えばＣｕの第１絶縁膜及び第２絶縁膜への拡散浸透を防止できる。   According to the semiconductor device of the present invention, the first insulating film does not have a conventional undercut, and the first barrier metal spacer covers the side wall of the first insulating film. Thereby, diffusion penetration of the metal of the via plug and the upper metal line, for example, Cu into the first insulating film and the second insulating film can be prevented.

したがって、上部金属ラインの間の漏れ電流が減少しうる。さらに、第２層間絶縁膜の絶縁信頼性を保証できてＴＤＤＢ特性が向上し、その結果、第２層間絶縁膜／上部金属ラインの配線信頼性が向上する。   Therefore, the leakage current between the upper metal lines can be reduced. Furthermore, the insulation reliability of the second interlayer insulating film can be guaranteed and the TDDB characteristics are improved. As a result, the wiring reliability of the second interlayer insulating film / upper metal line is improved.

さらに、該半導体素子によれば、ビアプラグ及び金属ラインの金属成分、例えばＣｕの層間絶縁膜への浸透をさらに効果的に防止できる。   Furthermore, according to the semiconductor element, it is possible to more effectively prevent the penetration of metal components of via plugs and metal lines, such as Cu, into the interlayer insulating film.

本発明による半導体素子の製造方法によれば、第１障壁金属スペーサ及びウィンドウは、連続的なエッチングにより一つの装置で一回にインシチュで形成されうる。かかる方法は、ウィンドウを先に形成し、別途に第１障壁金属スペーサを形成することに比べて経済性である。   According to the method of manufacturing a semiconductor device according to the present invention, the first barrier metal spacer and the window may be formed in-situ at one time by one apparatus by continuous etching. This method is more economical than forming the window first and separately forming the first barrier metal spacer.

以下、添付した図面を参照して本発明による望ましい実施形態を説明することによって、本発明を詳細に説明する。しかし、本発明は、以下で開示される実施形態に限定されるものではなく、異なる多様な形態に具現され、単に本実施形態は、本発明の開示を完全にし、当業者に発明の範疇を完全に知らせるために提供されるものである。図面で、構成要素は、説明の便宜のためにその大きさが誇張されている。   Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms. The embodiments merely complete the disclosure of the present invention and make the scope of the invention to those skilled in the art. It is provided for complete notification. In the drawings, the size of components is exaggerated for convenience of explanation.

本発明の実施形態において、開口は、ビアホール及び／またはトレンチを含みうる。また、本発明の実施形態において、電気的絶縁層は、エッチング停止層及び層間絶縁層を含むと理解されうる。   In an embodiment of the present invention, the opening may include a via hole and / or a trench. In the embodiments of the present invention, the electrical insulation layer may be understood to include an etch stop layer and an interlayer insulation layer.

図３を参照して、本発明の第１実施形態による半導体素子３００を説明する。例えば、半導体素子３００は、多様な集積回路を備えるロジック素子でありうる。この場合、半導体素子３００は、半導体基板２０３内またはその上にソース（図示せず）、ドレイン（図示せず）及びゲート電極（図示せず）を有する複数のトランジスタ（図示せず）を備えうる。ソース、ドレイン及びゲート電極の構造は、本発明が属する技術分野で通常的に知られた構造であり、したがって、その詳細な説明は省略する。   A semiconductor device 300 according to the first embodiment of the present invention will be described with reference to FIG. For example, the semiconductor device 300 may be a logic device including various integrated circuits. In this case, the semiconductor device 300 may include a plurality of transistors (not shown) having a source (not shown), a drain (not shown), and a gate electrode (not shown) in or on the semiconductor substrate 203. . The structure of the source, drain, and gate electrode is a structure that is generally known in the technical field to which the present invention belongs, and therefore, detailed description thereof is omitted.

他の例として、半導体素子３００は、揮発性メモリ素子、例えばＤＲＡＭまたはＳＲＡＭ、または不揮発性メモリ素子、例えばフラッシュメモリ、強誘電体メモリまたは相転移メモリでありうる。この場合、半導体素子３００は、半導体基板２０３内またはその上に複数のトランジスタ及びストレージノード（図示せず）を備えうる。ストレージノードの構造は、本発明が属する技術分野で通常的に知られた構造であり、したがって、その詳細な説明は省略する。   As another example, the semiconductor device 300 may be a volatile memory device, such as a DRAM or SRAM, or a non-volatile memory device, such as a flash memory, a ferroelectric memory, or a phase change memory. In this case, the semiconductor device 300 may include a plurality of transistors and storage nodes (not shown) in or on the semiconductor substrate 203. The structure of the storage node is a structure generally known in the technical field to which the present invention belongs, and therefore a detailed description thereof is omitted.

図３に示すように、半導体基板２０３上の下部金属ライン２１０は、前述したトランジスタまたはストレージノードと電気的に連結されうる。下部金属ライン２１０は、ビアプラグ２５５ａを通じて上部金属ライン２５５ｂと電気的に連結されうる。すなわち、下部金属ライン２１０及び上部金属ライン２５５ｂは、前述したトランジスタ及びストレージノードに対する配線構造となりうる。金属ライン２１０，２５５ｂは、例示的なものであって、半導体素子３００は、複数の金属ライン２１０，２５５ｂをさらに備えることもできる。   As shown in FIG. 3, the lower metal line 210 on the semiconductor substrate 203 may be electrically connected to the above-described transistor or storage node. The lower metal line 210 may be electrically connected to the upper metal line 255b through the via plug 255a. That is, the lower metal line 210 and the upper metal line 255b may have a wiring structure for the transistor and the storage node described above. The metal lines 210 and 255b are exemplary, and the semiconductor device 300 may further include a plurality of metal lines 210 and 255b.

エッチング停止膜２１２は、下部金属ライン２１０上に形成され、少なくとも下部金属ライン２１０の一部分を露出するウィンドウ（図９の２１８）を含みうる。第２層間絶縁膜２２０は、エッチング停止膜２１２上に形成され、ビアホール（図７の２３０）及びトレンチ（図７の２３５）を含みうる。トレンチ（図７の２３５）は、ビアホール２３０の上部を横切って形成され、少なくとも一部分がビアホール（図７の２３０）と連結される。第１障壁金属スペーサ２４０は、ビアホール（図７の２３０）内の露出された第２層間絶縁膜２２０の側壁を覆っており、下部金属ライン２１０の一部分及びウィンドウ（図９の２１８）内の露出されたエッチング停止膜２１２の少なくとも側壁の下端を露出できる。ビアプラグ２５５ａは、少なくともビアホール（図７の２３０）及びウィンドウ（図９の２１８）を埋め込み、下部金属ライン２１０の一部分と電気的に連結されうる。   The etch stop layer 212 may be formed on the lower metal line 210 and may include a window (218 in FIG. 9) exposing at least a portion of the lower metal line 210. The second interlayer insulating layer 220 is formed on the etch stop layer 212 and may include a via hole (230 in FIG. 7) and a trench (235 in FIG. 7). The trench (235 in FIG. 7) is formed across the upper portion of the via hole 230 and is at least partially connected to the via hole (230 in FIG. 7). The first barrier metal spacer 240 covers the exposed sidewall of the second interlayer insulating film 220 in the via hole (230 in FIG. 7), and exposes a portion of the lower metal line 210 and the window (218 in FIG. 9). At least the lower end of the side wall of the etched stop film 212 can be exposed. The via plug 255a fills at least the via hole (230 in FIG. 7) and the window (218 in FIG. 9), and may be electrically connected to a part of the lower metal line 210.

上部金属ライン２５５ｂは、トレンチ（図７の２３５）を埋め込み、ビアプラグ２５５ａと電気的に連結されうる。ビアプラグ２５５ａ及び上部金属ライン２５５ｂは、第１障壁金属スペーサ２４０により第２層間絶縁膜２２０と分離され、下部金属ライン２１０は、下部障壁金属層２０７により第１層間絶縁膜２０５と分離されうる。   The upper metal line 255b fills the trench (235 in FIG. 7) and can be electrically connected to the via plug 255a. The via plug 255 a and the upper metal line 255 b may be separated from the second interlayer insulating film 220 by the first barrier metal spacer 240, and the lower metal line 210 may be separated from the first interlayer insulating film 205 by the lower barrier metal layer 207.

さらに具体的に説明すれば、第２層間絶縁膜２２０は、第１絶縁膜２１４及び第２絶縁膜２１６を備えうる。例えば、第１絶縁膜２１４は、酸化膜を備え、第２絶縁膜２１６は、低誘電率の絶縁膜を備えうる。低誘電率の絶縁膜は、シリコン酸化膜より低い誘電率を有する絶縁膜を指しうる。例えば、低誘電率の絶縁膜は、ＳｉＣＯＨであり、酸化膜は、ＣまたはＨが含有されないか、またはそれらが微量含有されたＳｉＯ２でありうる。第１絶縁膜２１４の厚さは、１００ないし５００Åでありうる。第１層間絶縁膜２０５は、第２層間絶縁膜２２０と同一または類似した物質で形成されうる。 More specifically, the second interlayer insulating film 220 may include a first insulating film 214 and a second insulating film 216. For example, the first insulating film 214 may include an oxide film, and the second insulating film 216 may include a low dielectric constant insulating film. The low dielectric constant insulating film may refer to an insulating film having a lower dielectric constant than the silicon oxide film. For example, the insulating film having a low dielectric constant is a SiCOH, oxide film may be a SiO 2 to C or H is either not contained, or they are contained trace amounts. The first insulating film 214 may have a thickness of 100 to 500 mm. The first interlayer insulating layer 205 may be formed of the same or similar material as the second interlayer insulating layer 220.

エッチング停止膜２１２は、第２層間絶縁膜２２０に対してエッチング選択比のある絶縁膜であることが望ましい。例えば、エッチング停止膜２１２は、ＳｉＣＮであり、その厚さは、２００ないし１０００Åでありうる。   The etching stop film 212 is preferably an insulating film having an etching selectivity with respect to the second interlayer insulating film 220. For example, the etch stop layer 212 may be SiCN and may have a thickness of 200 to 1000 mm.

金属ライン２１０，２５５ｂ及び金属プラグ２５５ａは、比抵抗の低い金属、例えばＣｕを含みうる。下部障壁金属層２０７及び第１障壁金属スペーサ２４０は、Ｃｕのような金属の拡散を防止できる物質で形成されることが望ましい。例えば、下部障壁金属層２０７及び第１障壁金属スペーサ２４０は、ＴａまたはＴａＮを含み、望ましくは、下部障壁金属層２０７はＴａを含み、第１障壁金属スペーサ２４０はＴａＮを含みうる。下部障壁金属層２０７及び第１障壁金属スペーサ２４０の厚さは、５００Å以内、例えば３０ないし１００Åの範囲でありうる。   The metal lines 210 and 255b and the metal plug 255a may include a metal having a low specific resistance, such as Cu. The lower barrier metal layer 207 and the first barrier metal spacer 240 are preferably formed of a material that can prevent diffusion of a metal such as Cu. For example, the lower barrier metal layer 207 and the first barrier metal spacer 240 may include Ta or TaN. Preferably, the lower barrier metal layer 207 may include Ta and the first barrier metal spacer 240 may include TaN. The thickness of the lower barrier metal layer 207 and the first barrier metal spacer 240 may be within 500 mm, for example, in the range of 30 to 100 mm.

半導体素子３００によれば、第１絶縁膜２１４には、従来のようなアンダーカットがなく、第１障壁金属スペーサ２４０は、第１絶縁膜２１４の側壁を覆っている。これにより、ビアプラグ２５５ａ及び上部金属ライン２５５ｂの金属、例えばＣｕの第１絶縁膜２１４及び第２絶縁膜２１６への拡散浸透が防止されうる。したがって、上部金属ライン２５５ｂの間の漏れ電流が減少しうる。さらに、第２層間絶縁膜２２０の絶縁信頼性を保証できてＴＤＤＢ特性が向上し、その結果、第２層間絶縁膜２２０／上部金属ライン２５５ｂの配線信頼性が向上しうる。   According to the semiconductor device 300, the first insulating film 214 has no undercut as in the prior art, and the first barrier metal spacer 240 covers the side wall of the first insulating film 214. Accordingly, diffusion and penetration of the metal of the via plug 255a and the upper metal line 255b, for example, Cu into the first insulating film 214 and the second insulating film 216 can be prevented. Therefore, the leakage current between the upper metal lines 255b can be reduced. Furthermore, the insulation reliability of the second interlayer insulating film 220 can be ensured and the TDDB characteristics can be improved. As a result, the wiring reliability of the second interlayer insulating film 220 / upper metal line 255b can be improved.

図４を参照して、本発明の第２実施形態による半導体素子４００を説明する。半導体素子４００は、第１実施形態による半導体素子３００に付加して、第２障壁金属スペーサ２４５をさらに備えうる。さらに、第１障壁金属スペーサ２４０の構造面で、二つの実施形態は差を有しうる。したがって、半導体素子４００は、図３及びその説明を参照できる。同じ参照符号は同一または類似した構成要素を表す。   A semiconductor device 400 according to the second embodiment of the present invention will be described with reference to FIG. The semiconductor device 400 may further include a second barrier metal spacer 245 in addition to the semiconductor device 300 according to the first embodiment. Further, the two embodiments may have a difference in the structure of the first barrier metal spacer 240. Therefore, the semiconductor element 400 can refer to FIG. 3 and the description thereof. The same reference signs represent the same or similar components.

第２障壁金属スペーサ２４５は、第１障壁金属スペーサ２４０とビアプラグ２５５ａとの間、及び、エッチング停止膜２１２の側壁とビアプラグ２５５ａとの間に介在されうる。さらに、第１障壁金属スペーサ２４０は、トレンチ（図７の２３５）の底部の第２層間絶縁膜２２０上には形成されず、この場合、第２障壁金属スペーサ２４５の一部分は、第２層間絶縁膜２２０とビアプラグ２５５ａとの間に介在されうる。第２障壁金属スペーサ２４５は、ＴａＮまたはＴａを含み、望ましくは、ＴａＮを含みうる。   The second barrier metal spacer 245 may be interposed between the first barrier metal spacer 240 and the via plug 255a and between the sidewall of the etch stop layer 212 and the via plug 255a. Further, the first barrier metal spacer 240 is not formed on the second interlayer insulating film 220 at the bottom of the trench (235 in FIG. 7), and in this case, a part of the second barrier metal spacer 245 is formed as the second interlayer insulating film. It can be interposed between the film 220 and the via plug 255a. The second barrier metal spacer 245 includes TaN or Ta, and may include TaN.

半導体素子４００は、前述した第１実施形態による半導体素子（図３の３００）の長所をいずれも有しうる。さらに、半導体素子４００によれば、ビアプラグ２５５ａ及び金属ライン２１０，２５５ｂの金属成分、例えばＣｕの層間絶縁膜２０５，２２０への浸透をさらに効果的に防止できる。例えば、ビアプラグ２５５ａとトレンチ（図７の２３５）の底部の第２層間絶縁膜２２０との間には、第１実施形態における第１障壁金属スペーサ２４０より厚い第２障壁金属スペーサ２４５が介在されうる。さらに、エッチング停止膜２１２の側壁とビアプラグ２５５ａとの間にも、第１実施形態とは異なり、第２障壁金属スペーサ２４５が介在されうる。   The semiconductor device 400 may have all of the advantages of the semiconductor device (300 in FIG. 3) according to the first embodiment described above. Furthermore, according to the semiconductor element 400, the penetration of the metal components of the via plug 255a and the metal lines 210 and 255b, for example, Cu into the interlayer insulating films 205 and 220 can be more effectively prevented. For example, a second barrier metal spacer 245 thicker than the first barrier metal spacer 240 in the first embodiment may be interposed between the via plug 255a and the second interlayer insulating film 220 at the bottom of the trench (235 in FIG. 7). . Further, unlike the first embodiment, a second barrier metal spacer 245 may be interposed between the sidewall of the etching stopper film 212 and the via plug 255a.

図５を参照して、本発明の第３実施形態による半導体素子５００を説明する。半導体素子５００は、第２実施形態による半導体素子４００に付加して、上部障壁金属層２５０をさらに備えうる。さらに、下部金属ライン２１０の構造において、第２実施形態と第３実施形態は差を有しうる。したがって、半導体素子５００は、図３、図４及び該当説明を参照できる。同じ参照符号は同一または類似した構成要素を表す。   A semiconductor device 500 according to a third embodiment of the present invention will be described with reference to FIG. The semiconductor device 500 may further include an upper barrier metal layer 250 in addition to the semiconductor device 400 according to the second embodiment. Furthermore, in the structure of the lower metal line 210, the second embodiment and the third embodiment may have a difference. Therefore, the semiconductor device 500 can refer to FIGS. 3 and 4 and the corresponding description. The same reference signs represent the same or similar components.

下部金属ライン２１０は、第２側壁金属スペーサ２４５の下端部に再蒸着による再蒸着部分２１０ａを備えうる。例えば、再蒸着部分２１０ａは、ウィンドウ（図９の２１８）の下部の下部金属ライン２１０の部分がスパッタリングされた後、第２側壁金属スペーサ２４５上に蒸着されて形成されうる。これにより、ウィンドウ（図９の２１８）の下部の下部金属ライン２１０の部分は、へこんでいる凹状になりうる。   The lower metal line 210 may include a redeposition portion 210 a by redeposition at the lower end of the second sidewall metal spacer 245. For example, the redeposition portion 210a may be formed by depositing on the second sidewall metal spacer 245 after the portion of the lower metal line 210 below the window (218 in FIG. 9) is sputtered. As a result, the portion of the lower metal line 210 below the window (218 in FIG. 9) can be recessed.

上部障壁金属層２５０は、ビアプラグ２５５ａと第２障壁金属スペーサ２４５との間、上部金属ライン２５５ｂと第２障壁金属スペーサ２４５との間、及び、下部金属ライン２１０とビアプラグ２５５ａとの間に介在されうる。例えば、上部障壁金属層２５０は、ＴａまたはＴａＮを含み、望ましくは、ビアプラグ２５５ａと下部金属ライン２１０との間にさらに優秀な接着力を提供できるＴａを含みうる。   The upper barrier metal layer 250 is interposed between the via plug 255a and the second barrier metal spacer 245, between the upper metal line 255b and the second barrier metal spacer 245, and between the lower metal line 210 and the via plug 255a. sell. For example, the upper barrier metal layer 250 may include Ta or TaN, and may preferably include Ta that can provide better adhesion between the via plug 255a and the lower metal line 210.

半導体素子５００は、第１及び第２実施形態による半導体素子（図３の３００、図４の４００）の長所を有しうる。さらに、ビアプラグ２５５ａと下部金属ライン２１０との接着力が向上する。金属ライン２１０，２５５ｂと層間絶縁膜２０５，２２０との間、及び、ビアプラグ２５５ａと第２層間絶縁膜２２０との間の金属、例えばＣｕの拡散をさらに効果的に防止できる。   The semiconductor device 500 may have the advantages of the semiconductor devices (300 in FIG. 3 and 400 in FIG. 4) according to the first and second embodiments. Furthermore, the adhesive force between the via plug 255a and the lower metal line 210 is improved. Diffusion of a metal, for example, Cu, between the metal lines 210 and 255b and the interlayer insulating films 205 and 220 and between the via plug 255a and the second interlayer insulating film 220 can be more effectively prevented.

図３ないし図５に示すように、本発明の実施形態による半導体素子３００，４００，５００は、当業者により修正されうる。例えば、第３実施形態による半導体素子５００は、第２側壁金属スペーサ２４５を備えないこともある。他の例として、第１及び第２実施形態による半導体素子３００，４００において、下部金属ライン２１０は、再蒸着部分２１０ａを含むこともできる。   As shown in FIGS. 3 to 5, the semiconductor devices 300, 400, and 500 according to the embodiment of the present invention can be modified by those skilled in the art. For example, the semiconductor device 500 according to the third embodiment may not include the second sidewall metal spacer 245. As another example, in the semiconductor devices 300 and 400 according to the first and second embodiments, the lower metal line 210 may include a redeposition portion 210a.

以下では、図６ないし図１３を参照して、本発明の実施形態による半導体素子の製造方法を説明する。半導体素子の構造は、前述した第１ないし第３実施形態による半導体素子（図３の３００、図４の４００、図５の５００）の説明を参照できる。同じ参照符号は同一または類似した構成要素を表す。   Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. For the structure of the semiconductor element, reference can be made to the description of the semiconductor elements (300 in FIG. 3, 400 in FIG. 4, 500 in FIG. 5) according to the first to third embodiments described above. The same reference signs represent the same or similar components.

図６に示すように、半導体基板２０３上に少なくとも一部分が第１金属絶縁層２０５内に埋め込まれた下部金属ライン２１０を形成する。下部金属ライン２１０と第１層間絶縁層２０５との間には、下部障壁金属層２０７が介在されうる。下部金属ライン２１０は、以後に形成される上部金属ライン（図１３の２５５ｂ）と同様に形成できる。したがって、下部金属ライン２１０の形成方法については、その詳細な説明を省略する。   As shown in FIG. 6, a lower metal line 210 is formed on the semiconductor substrate 203 so that at least a part thereof is embedded in the first metal insulating layer 205. A lower barrier metal layer 207 may be interposed between the lower metal line 210 and the first interlayer insulating layer 205. The lower metal line 210 can be formed in the same manner as the upper metal line (255b in FIG. 13) to be formed later. Therefore, the detailed description of the method of forming the lower metal line 210 is omitted.

下部金属ライン２１０を形成する前に、半導体基板２０３内またはその上には、トランジスタ（図示せず）またはストレージノード（図示せず）がさらに形成されうる。下部金属ライン２１０は、トランジスタまたはストレージノードと連結されうる。さらに、下部金属ライン２１０の下部の半導体基板２０３上には、他の下部金属ライン（図示せず）がさらに形成されうる。この場合、下部金属ライン２１０は、他の下部金属ラインと連結されることもある。   Prior to forming the lower metal line 210, a transistor (not shown) or a storage node (not shown) may be further formed in or on the semiconductor substrate 203. The lower metal line 210 may be connected to a transistor or a storage node. Further, another lower metal line (not shown) may be further formed on the semiconductor substrate 203 below the lower metal line 210. In this case, the lower metal line 210 may be connected to another lower metal line.

次いで、下部金属ライン２１０及び第１層間絶縁膜２０５上にエッチング停止層２１２´を形成する。エッチング停止層２１２´上には、第２層間絶縁層２２０´を形成し、第２層間絶縁層２２０´上には、ハードマスク層２２５´を形成する。例えば、エッチング停止層２１２´は、ＳｉＣＮを含み、化学気相蒸着（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ：ＣＶＤ）法を利用して形成できる。エッチング停止層２１２´の厚さは、２００ないし１０００Åでありうる。ハードマスク層２２５´は、ＣＶＤ法により形成でき、例えばシリコン酸化膜を備えうる。ハードマスク層２２５´の厚さは、２００ないし１５００Åでありうる。   Next, an etch stop layer 212 ′ is formed on the lower metal line 210 and the first interlayer insulating film 205. A second interlayer insulating layer 220 ′ is formed on the etching stopper layer 212 ′, and a hard mask layer 225 ′ is formed on the second interlayer insulating layer 220 ′. For example, the etch stop layer 212 ′ includes SiCN and can be formed using a chemical vapor deposition (CVD) method. The thickness of the etch stop layer 212 ′ may be 200 to 1000 mm. The hard mask layer 225 ′ can be formed by a CVD method, and can include, for example, a silicon oxide film. The thickness of the hard mask layer 225 ′ may be 200 to 1500 mm.

第２層間絶縁層２２０´は、第１絶縁層２１４´及び第２絶縁層２１６´を備えうる。例えば、第１絶縁層２１４´は、酸化膜を含み、第２絶縁層２１６´は、低誘電率の絶縁膜、例えばＳｉＣＯＨを含みうる。ＳｉＣＯＨを含む第２層間絶縁層２２０´は、ＣＶＤ法により形成でき、この場合、初期には、ＣまたはＨがほとんどない第１絶縁層２１４´が自然に形成され、次いで、連続的に第２絶縁層２１６´が形成されうる。第１絶縁層２１４´の厚さは、１００ないし５００Åでありうる。第２絶縁層２１６´は、２，０００ないし１０，０００Åでありうる。ただし、第２絶縁層２１６´の厚さは、必要に応じて適切に変形されうる。   The second interlayer insulating layer 220 ′ may include a first insulating layer 214 ′ and a second insulating layer 216 ′. For example, the first insulating layer 214 ′ may include an oxide film, and the second insulating layer 216 ′ may include a low dielectric constant insulating film, such as SiCOH. The second interlayer insulating layer 220 ′ containing SiCOH can be formed by a CVD method. In this case, the first insulating layer 214 ′ having almost no C or H is naturally formed in the initial stage, and then the second insulating layer is continuously formed. An insulating layer 216 ′ may be formed. The thickness of the first insulating layer 214 ′ may be 100 to 500 mm. The second insulating layer 216 ′ may be 2,000 to 10,000 inches. However, the thickness of the second insulating layer 216 ′ can be appropriately changed as necessary.

図７に示すように、第２層間絶縁層（図６の２２０´）の所定部分をエッチングして、ビアホール２３０及びトレンチ２３５を含む第２層間絶縁膜２２０を形成する。例えば、フォトリソグラフィ及びエッチング技術を利用してハードマスク層（図６の２２５´）をパターニングして、第１ハードマスクパターン（図示せず）を形成する。次いで、第１ハードマスクパターン（図示せず）をエッチング保護膜として第２層間絶縁層２２０´をエッチングして、エッチング停止層２１２´を露出するビアホール２３０を形成する。次いで、第１ハードマスクパターンをパターニングして、第２ハードマスクパターン２２５を形成する。第２ハードマスクパターン２２５をエッチング保護膜として第２層間絶縁層２２０´を所定深さほどエッチングして、ビアホール２３０の上部を横切るトレンチ２３５を形成する。変形された実施形態において、ビアホール２３０及びトレンチ２３５の形成順序が変わることもある。   As shown in FIG. 7, a predetermined portion of the second interlayer insulating layer (220 ′ in FIG. 6) is etched to form a second interlayer insulating film 220 including a via hole 230 and a trench 235. For example, the hard mask layer (225 ′ of FIG. 6) is patterned using photolithography and etching techniques to form a first hard mask pattern (not shown). Next, the second interlayer insulating layer 220 ′ is etched using the first hard mask pattern (not shown) as an etching protective film to form a via hole 230 exposing the etching stop layer 212 ′. Next, the first hard mask pattern is patterned to form a second hard mask pattern 225. Using the second hard mask pattern 225 as an etching protective film, the second interlayer insulating layer 220 ′ is etched to a predetermined depth to form a trench 235 that crosses the upper portion of the via hole 230. In the modified embodiment, the order of forming the via hole 230 and the trench 235 may change.

エッチング停止層２１２´は、第２層間絶縁層２２０´に対して高いエッチング選択比を有しうる。したがって、エッチング選択比によって、エッチング停止層２１２´の上端部分が小幅にエッチングされることも可能である。ビアホール２３０から第１絶縁膜２１４の側壁２１４１が露出されうる。ビアホール２３０及びトレンチ２３５から、第２絶縁膜２１６の側壁２１６１，２１６２及びトレンチ２３５の底部の第２絶縁膜２１６の部分２１６３が露出されうる。   The etch stop layer 212 ′ may have a high etch selectivity with respect to the second interlayer insulating layer 220 ′. Therefore, the upper end portion of the etching stop layer 212 ′ can be etched with a small width depending on the etching selectivity. The sidewall 2141 of the first insulating film 214 may be exposed from the via hole 230. From the via hole 230 and the trench 235, the side walls 2161 and 2162 of the second insulating film 216 and the portion 2163 of the second insulating film 216 at the bottom of the trench 235 can be exposed.

図８に示すように、ビアホール２３０及びトレンチ２３５が形成された結果物上に第１障壁金属層２４０´を形成する。第１障壁金属層２４０´は、ＰＶＤ法、例えばイオン金属スパッタリング法を利用して形成できる。例えば、第１障壁金属層２４０´は、ＴａまたはＴａＮを含み、望ましくは、ＴａＮで形成でき、その厚さは、５００Å以内となる。   As shown in FIG. 8, a first barrier metal layer 240 'is formed on the resultant structure in which the via hole 230 and the trench 235 are formed. The first barrier metal layer 240 ′ can be formed using a PVD method, for example, an ion metal sputtering method. For example, the first barrier metal layer 240 ′ may include Ta or TaN, and may be formed of TaN, and the thickness thereof may be 500 mm or less.

図９に示すように、第１障壁金属層（図８の２４０´）を異方性エッチングして、第１障壁金属スペーサ２４０を形成する。次いで、第１障壁金属スペーサ２４０をエッチング保護膜としてエッチング停止層（図８の２１２´）をエッチングして、ウィンドウ２１８を含むエッチング停止膜２１２を形成する。異方性エッチングは、例えばドライエッチングを利用して行える。第１障壁金属スペーサ２４０及びウィンドウ２１８は、連続的なエッチングにより一つの装置で一回にインシチュで形成されうる。かかる方法は、ウィンドウ２１８を先に形成し、別途に第１障壁金属スペーサ２４０を形成することに比べて、その工程ステップが単純であって経済性面で長所を有する。   As shown in FIG. 9, the first barrier metal layer 240 (240 ′ of FIG. 8) is anisotropically etched to form a first barrier metal spacer 240. Next, the etching stopper layer (212 ′ in FIG. 8) is etched using the first barrier metal spacer 240 as an etching protective film to form the etching stopper film 212 including the window 218. The anisotropic etching can be performed using, for example, dry etching. The first barrier metal spacer 240 and the window 218 may be formed in-situ at one time by one apparatus by continuous etching. This method has advantages in terms of economy and simple process steps as compared to forming the window 218 first and forming the first barrier metal spacer 240 separately.

ウィンドウ２１８から、エッチング停止膜２１２の側壁及び下部金属ライン２１０の一部分が露出されうる。第１障壁金属スペーサ２４０は、第２絶縁膜２１６の側壁２１６１，２１６２（図７）及び第１絶縁膜２１４の側壁２１４１を覆っており、エッチング停止膜２１２の側壁の少なくとも下端部は露出している。さらに、第１障壁金属スペーサ２４０は、トレンチ２３５の底部の第２層間絶縁膜２２０の部分２１６３（図７）上には形成されないこともある。   From the window 218, the sidewall of the etch stop layer 212 and a portion of the lower metal line 210 may be exposed. The first barrier metal spacer 240 covers the side walls 2161, 2162 (FIG. 7) of the second insulating film 216 and the side wall 2141 of the first insulating film 214, and at least the lower end of the side wall of the etching stop film 212 is exposed. Yes. Further, the first barrier metal spacer 240 may not be formed on the portion 2163 (FIG. 7) of the second interlayer insulating film 220 at the bottom of the trench 235.

次いで、選択によって、ウィンドウ２１８により露出された下部金属ライン２１０の一部分に形成された自然酸化膜及びエッチング残留物を除去するための洗浄を行える。洗浄は、酸化膜を除去できる洗浄液、例えば希釈されたＨＦ溶液を利用したウェットエッチングを利用して行える。この場合、酸化膜で形成された第１絶縁膜２１４は、第１障壁金属スペーサ２４０によりＨＦ溶液から保護されうる。これにより、第２絶縁膜２１４のアンダーカットの発生を防止できる。他の例として、洗浄は、スパッタエッチを利用して行われることもある。   Next, cleaning may be performed to remove a natural oxide film and an etching residue formed on a part of the lower metal line 210 exposed by the window 218 by selection. The cleaning can be performed by using a cleaning solution capable of removing the oxide film, for example, wet etching using a diluted HF solution. In this case, the first insulating film 214 formed of an oxide film can be protected from the HF solution by the first barrier metal spacer 240. Thereby, occurrence of undercut of the second insulating film 214 can be prevented. As another example, cleaning may be performed using a sputter etch.

図１０に示すように、第１障壁金属スペーサ２４０及びエッチング停止膜２１２の側壁を覆う第２障壁金属スペーサ２４５を形成する。さらに、第２障壁金属スペーサ２４５の一部分は、第２ハードマスクパターン２２５及びトレンチ２３５の底部の第２絶縁膜２１６の部分２１６３（図７）を覆うこともでき、その一部分の厚さは、第１障壁金属スペーサ２４０を覆っている他の部分より薄いことがある。   As shown in FIG. 10, a second barrier metal spacer 245 is formed to cover the sidewalls of the first barrier metal spacer 240 and the etch stop layer 212. Further, a portion of the second barrier metal spacer 245 may cover the second hard mask pattern 225 and the portion 2163 (FIG. 7) of the second insulating film 216 at the bottom of the trench 235, and the thickness of the portion may be the first thickness. One barrier metal spacer 240 may be thinner than other portions covering it.

例えば、第２障壁金属スペーサ２４５は、第２障壁金属層（図示せず）を形成した後、それを異方性エッチングして形成できる。ただし、下部金属ライン２１０上の第２障壁金属層の部分が、エッチング速度が速くて最も先に除去されうる。これにより、下部金属ライン２１０上の第２障壁金属層の部分は除去され、トレンチ２３５の底部の第２絶縁膜２１６上の第２障壁金属層の部分、及び、第２ハードマスクパターン２２５上の第２障壁金属層の部分は残留することが可能である。   For example, the second barrier metal spacer 245 may be formed by forming a second barrier metal layer (not shown) and then anisotropically etching it. However, the portion of the second barrier metal layer on the lower metal line 210 can be removed first because the etching rate is high. As a result, the portion of the second barrier metal layer on the lower metal line 210 is removed, and the portion of the second barrier metal layer on the second insulating film 216 at the bottom of the trench 235 and on the second hard mask pattern 225 are removed. A portion of the second barrier metal layer can remain.

さらに、下部金属ライン２１０はオーバーエッチングされうる。オーバーエッチングされた下部金属ライン２１０は、第２障壁金属スペーサ２４５の下端側壁に付着されて再蒸着部分２１０ａを形成できる。オーバーエッチング量は、例えば１０ないし３００Åでありうる。   Further, the lower metal line 210 can be over-etched. The over-etched lower metal line 210 may be attached to the lower sidewall of the second barrier metal spacer 245 to form a redeposition portion 210a. The overetching amount can be, for example, 10 to 300 mm.

図１１に示すように、第２障壁金属スペーサ２４５が形成された結果物上に上部障壁金属層２５０を形成する。上部障壁金属層２５０は、例えばＴａまたはＴａＮ、望ましくは、Ｔａを含み、その厚さは、５００Å以下でありうる。上部障壁金属層２５０は、ＰＶＤ法、例えばイオン金属スパッタリング法を利用して形成できる。   Referring to FIG. 11, an upper barrier metal layer 250 is formed on the resultant structure on which the second barrier metal spacer 245 is formed. The upper barrier metal layer 250 includes, for example, Ta or TaN, preferably Ta, and the thickness thereof may be 500 mm or less. The upper barrier metal layer 250 can be formed using a PVD method, for example, an ion metal sputtering method.

図１２に示すように、上部障壁金属層２５０が形成された結果物上に第２金属層２５５を形成する。例えば、第２金属層２５５は、ＰＶＤ法を利用してＣｕシード層（図示せず）を形成した後、シード層上にＣｕメッキ層（図示せず）を形成することによって形成できる。Ｃｕメッキ層は、電解メッキまたは無電解メッキ法を利用して形成できる。   Referring to FIG. 12, a second metal layer 255 is formed on the resultant structure on which the upper barrier metal layer 250 is formed. For example, the second metal layer 255 can be formed by forming a Cu seed layer (not shown) using the PVD method and then forming a Cu plating layer (not shown) on the seed layer. The Cu plating layer can be formed using electrolytic plating or electroless plating.

図１３に示すように、第２層間絶縁膜２２０が露出されるまで第２金属層２５５を平坦化して、ビアプラグ２５５ａ及び上部金属ライン２５５ｂを形成できる。例えば、平坦化は、化学的機械的研磨（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ：ＣＭＰ）法を利用して行える。このように、埋め込みと平坦化とを利用して、ビアプラグ２５５ａ及び上部金属ライン２５５ｂを形成する方法をダマシン法と呼び、さらに具体的には、ビアプラグ２５５ａ及び上部金属ライン２５５ｂを同時に形成するという点でデュアルダマシン法と呼ぶ。   As shown in FIG. 13, the second metal layer 255 is planarized until the second interlayer insulating film 220 is exposed, and the via plug 255a and the upper metal line 255b can be formed. For example, the planarization can be performed using a chemical mechanical polishing (CMP) method. As described above, the method of forming the via plug 255a and the upper metal line 255b using the embedding and planarization is called a damascene method, and more specifically, the via plug 255a and the upper metal line 255b are formed at the same time. This is called the dual damascene method.

しかし、本発明による半導体素子の製造方法は、デュアルダマシン法に制限されず、ビアプラグ２５５ａまたは上部金属ライン２５５ｂのうち一つのみをダマシン法で形成するシングルダマシン法にも適用できるということは、当業者に自明である。   However, the method of manufacturing a semiconductor device according to the present invention is not limited to the dual damascene method, and can be applied to a single damascene method in which only one of the via plug 255a or the upper metal line 255b is formed by the damascene method. It is obvious to the contractor.

発明の特定の実施形態についての以上の説明は、例示及び説明を目的として提供された。したがって、本発明は、前記実施形態に限定されず、当業者により前記実施形態を組み合わせて実施するなど色々な多くの修正及び変更が可能であるということは明白である。   The foregoing descriptions of specific embodiments of the invention have been provided for purposes of illustration and description. Therefore, it is apparent that the present invention is not limited to the above-described embodiment, and various modifications and changes can be made by those skilled in the art by combining the above-described embodiments.

本発明は、半導体素子関連の技術分野に適用可能である。   The present invention is applicable to a technical field related to semiconductor elements.

従来の半導体素子の配線構造を示す断面図である。It is sectional drawing which shows the wiring structure of the conventional semiconductor element. 図１の配線構造のＡ部分を拡大した断面図である。It is sectional drawing to which the A section of the wiring structure of FIG. 1 was expanded. 本発明の第１実施形態による半導体素子を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. 本発明の第２実施形態による半導体素子を示す断面図である。It is sectional drawing which shows the semiconductor element by 2nd Embodiment of this invention. 本発明の第３実施形態による半導体素子を示す断面図である。It is sectional drawing which shows the semiconductor device by 3rd Embodiment of this invention. 本発明の一実施形態による半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element by one Embodiment of this invention. 本発明の一実施形態による半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element by one Embodiment of this invention. 本発明の一実施形態による半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element by one Embodiment of this invention. 本発明の一実施形態による半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element by one Embodiment of this invention. 本発明の一実施形態による半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element by one Embodiment of this invention. 本発明の一実施形態による半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element by one Embodiment of this invention. 本発明の一実施形態による半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element by one Embodiment of this invention. 本発明の一実施形態による半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element by one Embodiment of this invention.

符号の説明Explanation of symbols

２０３ 半導体基板
２０５，２２０ 層間絶縁膜
２０７，２５０ 障壁金属層
２１０，２５５ｂ 金属ライン
２１２ エッチング停止膜
２１４ 第１絶縁膜
２１６ 第２絶縁膜
２４０，２４５ 障壁金属スペーサ
２５５ａ ビアプラグ
203 Semiconductor substrate 205, 220 Interlayer insulating film 207, 250 Barrier metal layer 210, 255b Metal line 212 Etching stop film 214 First insulating film 216 Second insulating film 240, 245 Barrier metal spacer 255a Via plug

Claims (11)

半導体基板上に形成された第１金属ラインと、
前記第１金属ライン上に形成され、少なくとも前記第１金属ラインの一部分を露出するウィンドウを含むエッチング停止膜と、
前記エッチング停止膜上に形成され、前記第１金属ラインの一部分を露出するように前記ウィンドウと連結されたビアホールを含む層間絶縁膜と、
前記ビアホール内の前記露出された層間絶縁膜の側壁を覆っており、前記第１金属ラインの一部分を露出し、前記ウィンドウ内の前記露出されたエッチング停止膜の少なくとも側壁の下端を露出する第１障壁金属スペーサと、
少なくとも前記ビアホール及び前記ウィンドウを埋め込み、前記第１金属ラインの一部分と電気的に連結され、前記層間絶縁膜と接触しないビアプラグと、
前記第１障壁金属スペーサと前記ビアプラグとの間、前記第１金属ラインの一部分と前記ビアプラグとの間、及び、前記エッチング停止膜の側壁と前記ビアプラグとの間に介在された第３障壁金属層と、
を備え、
前記第１金属ラインは、前記ビアプラグに対応した位置に形成された凸部を有しており、
前記凸部は、前記第３障壁金属層と前記エッチング停止膜の側壁との間に伸張していることを特徴とする半導体素子。 A first metal line formed on the semiconductor substrate;
An etch stop layer formed on the first metal line and including a window exposing at least a portion of the first metal line;
An interlayer insulating layer including a via hole formed on the etch stop layer and connected to the window to expose a portion of the first metal line;
Covering the sidewall of the exposed interlayer insulating film in the via hole, exposing a portion of the first metal line, and exposing at least a lower end of the exposed etching stop film in the window. A barrier metal spacer;
A via plug filling at least the via hole and the window, electrically connected to a portion of the first metal line, and not in contact with the interlayer insulating film;
A third barrier metal layer interposed between the first barrier metal spacer and the via plug, between a portion of the first metal line and the via plug, and between a sidewall of the etch stop layer and the via plug; When,
Equipped with a,
The first metal line has a convex portion formed at a position corresponding to the via plug,
The convex portion is a semiconductor element characterized that you have to stretch between a sidewall of the etch stop layer and the third barrier metal layer. 前記層間絶縁膜は、下部に第１絶縁膜及び上部に第２絶縁膜を備えることを特徴とする請求項１に記載の半導体素子。   The semiconductor device according to claim 1, wherein the interlayer insulating film includes a first insulating film at a lower portion and a second insulating film at an upper portion. 前記第１絶縁膜は、酸化膜であり、前記第２絶縁膜は、前記酸化膜より低い誘電率を有する低誘電率の絶縁膜であることを特徴とする請求項２に記載の半導体素子。   3. The semiconductor device according to claim 2, wherein the first insulating film is an oxide film, and the second insulating film is a low dielectric constant insulating film having a lower dielectric constant than the oxide film. 前記低誘電率膜は、ＳｉＣＯＨを含み、前記エッチング停止膜は、ＳｉＣＮを含むことを特徴とする請求項３に記載の半導体素子。   4. The semiconductor device according to claim 3, wherein the low dielectric constant film includes SiCOH, and the etching stop film includes SiCN. 前記第１障壁金属スペーサと前記ビアプラグとの間、及び、前記ビアプラグと前記エッチング停止膜の側壁との間に介在された第２障壁金属スペーサをさらに備えることを特徴とする請求項１から４の何れか一項に記載の半導体素子。   5. The semiconductor device according to claim 1, further comprising a second barrier metal spacer interposed between the first barrier metal spacer and the via plug and between the via plug and a sidewall of the etching stopper film. The semiconductor element as described in any one. 前記第１障壁金属スペーサは、ＴａＮを含み、前記第３障壁金属層は、Ｔａを含むことを特徴とする請求項１から５の何れか一項に記載の半導体素子。 The first barrier metal spacer comprises TaN, the third barrier metal layer, a semiconductor device according to claim 1, any one of 5, characterized in that it comprises a Ta. 前記第１金属ライン及び前記ビアプラグは、銅を含むことを特徴とする請求項１から６の何れか一項に記載の半導体素子。 The first metal lines and the via plug, the semiconductor device according to any one of claims 1 6, characterized in that it comprises copper. 半導体基板上に形成された第１金属ラインと、
前記第１金属ライン上に形成され、少なくとも前記第１金属ラインの一部分を露出するウィンドウを含むエッチング停止膜と、
前記エッチング停止膜上に形成され、前記第１金属ラインの一部分を露出するように前記ウィンドウと連結されたビアホール、及び、前記ビアホールの上部を横切って形成され、少なくとも一部分が前記ビアホールと連結されたトレンチを含む層間絶縁膜と、
前記ビアホール及び前記トレンチ内の前記露出された前記層間絶縁膜の側壁を覆っており、前記第１金属ラインの一部分を露出し、前記ウィンドウ内の前記露出されたエッチング停止膜の少なくとも側壁の下端を露出する第１障壁金属スペーサと、
前記ビアホール及び前記ウィンドウを埋め込み、前記第１金属ラインの一部分と電気的に連結され、前記層間絶縁膜と接触しないビアプラグと、
少なくとも前記トレンチを埋め込み、前記ビアプラグと電気的に連結され、前記層間絶縁膜と接触しない第２金属ラインと、
前記第１障壁金属スペーサと前記ビアプラグとの間、前記第１金属ラインの一部分と前記ビアプラグとの間、及び、前記エッチング停止膜の側壁と前記ビアプラグとの間に介在された第３障壁金属層と、
を備え、
前記第１金属ラインは、前記ビアプラグに対応した位置に形成された凸部を有しており、
前記凸部は、前記第３障壁金属層と前記エッチング停止膜の側壁との間に伸張していることを特徴とする半導体素子。 A first metal line formed on the semiconductor substrate;
An etch stop layer formed on the first metal line and including a window exposing at least a portion of the first metal line;
A via hole formed on the etch stop layer and connected to the window so as to expose a part of the first metal line, and a top part of the via hole, and at least a part of the via hole is connected to the via hole. An interlayer insulating film including a trench;
The sidewall of the exposed interlayer insulating film in the via hole and the trench is covered, a part of the first metal line is exposed, and at least a lower end of the exposed etching stopper film in the window An exposed first barrier metal spacer;
A via plug filling the via hole and the window, electrically connected to a portion of the first metal line, and not in contact with the interlayer insulating film;
A second metal line that fills at least the trench, is electrically connected to the via plug, and does not contact the interlayer insulating film;
A third barrier metal layer interposed between the first barrier metal spacer and the via plug, between a portion of the first metal line and the via plug, and between a sidewall of the etch stop layer and the via plug; When,
Equipped with a,
The first metal line has a convex portion formed at a position corresponding to the via plug,
The convex portion is a semiconductor element characterized that you have to stretch between a sidewall of the etch stop layer and the third barrier metal layer. 前記層間絶縁膜は、下部に第１絶縁膜及び上部に第２絶縁膜を備え、前記第１絶縁膜は、酸化膜であり、前記第２絶縁膜は、前記酸化膜より低い誘電率を有する低誘電率の絶縁膜であることを特徴とする請求項８に記載の半導体素子。 The interlayer insulating film includes a first insulating film at a lower portion and a second insulating film at an upper portion, the first insulating film is an oxide film, and the second insulating film has a dielectric constant lower than that of the oxide film. 9. The semiconductor element according to claim 8 , wherein the semiconductor element is an insulating film having a low dielectric constant. 前記第１障壁金属スペーサと前記ビアプラグとの間、前記ビアプラグと前記エッチング停止膜の側壁との間、及び、前記トレンチの底部の層間絶縁膜の部分と前記ビアプラグとの間に介在された第２障壁金属スペーサをさらに備えることを特徴とする請求項８または９に記載の半導体素子。 A second intervening between the first barrier metal spacer and the via plug, between the via plug and the sidewall of the etching stop film, and between the portion of the interlayer insulating film at the bottom of the trench and the via plug. the semiconductor device according to claim 8 or 9, further comprising a barrier metal spacer. 前記第２障壁金属スペーサと前記ビアプラグとの間、及び、前記第１金属ラインの一部分と前記ビアプラグとの間に介在された第３障壁金属層をさらに備えることを特徴とする請求項１０に記載の半導体素子。 Between the second barrier metal spacer via plug, and, to claim 1 0, characterized in that it further comprises a third barrier metal layer interposed between the a portion plug of the first metal line The semiconductor element as described.
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