KR20080114228A - Method of forming a metal wire in a semiconductor device - Google Patents

Method of forming a metal wire in a semiconductor device Download PDF

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KR20080114228A
KR20080114228A KR1020070063587A KR20070063587A KR20080114228A KR 20080114228 A KR20080114228 A KR 20080114228A KR 1020070063587 A KR1020070063587 A KR 1020070063587A KR 20070063587 A KR20070063587 A KR 20070063587A KR 20080114228 A KR20080114228 A KR 20080114228A
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film
forming
high density
hdp
density plasma
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KR1020070063587A
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Korean (ko)
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조직호
김태경
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

A method for forming a metal wire of a semiconductor device is provided to remove the protrusion of the metal layer selectively by a sputtering phenomenon when forming a high density plasma oxide. A metal layer(106) is formed on a semiconductor substrate(100). A first high density plasma oxide layer is formed on the metal layer. An insulating layer and a barrier metal layer are formed between the semiconductor substrate and the metal layer. The barrier metal layer is formed by laminating a Ti layer and a TiN layer. The metal layer is formed as a tungsten layer by using a chemical vapor deposition.

Description

반도체 소자의 금속 배선 형성방법{Method of forming a metal wire in a semiconductor device}Method of forming a metal wire in a semiconductor device

도 1a 내지 도 1c는 본 발명의 실시 예에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.

도 2는 고밀도 플라즈마(HDP) 산화막 형성 공정 시 스퍼터링 이온(즉, Ar 가스)의 입사각에 따른 스퍼터링 효과를 나타낸 그래프이다. FIG. 2 is a graph showing the sputtering effect according to the incident angle of sputtering ions (that is, Ar gas) in a high density plasma (HDP) oxide film forming process.

도 3은 웨이퍼에 인가되는 바이어스(bias)에 따라 스퍼터링 효과가 발생하는 비를 나타낸 그래프이다.  3 is a graph showing a ratio in which a sputtering effect occurs according to a bias applied to a wafer.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 102 : 절연막100 semiconductor substrate 102 insulating film

104 : 베리어 메탈막 106 : 금속막104: barrier metal film 106: metal film

108 : 하드 마스크막 A : 돌기108: hard mask film A: projection

본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히, 금속막( 특히, 텅스텐(W)막) 형성시 발생하는 웨이퍼 표면의 돌기를 개선하기 위한 반도체 소자의 금속 배선 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming metal wirings in semiconductor devices, and more particularly, to a method of forming metal wirings in semiconductor devices for improving the projection of the wafer surface generated when forming a metal film (especially a tungsten (W) film).

플래시 메모리 소자의 경우, CVD(Chemical Vapor Deposition) 방법을 이용한 금속막(특히, 텅스텐(W)막) 형성 공정을 실시하여 금속 배선을 형성하고 있다. 텅스텐(W)막 형성 공정 시 PVD(Physical Vapor Deposition) 방법에 비해 CVD 방법을 이용할 경우 증착 특성상 두께가 두꺼워질수록 표면 돌기가 악화되는 문제점이 발생한다. 표면 돌기가 악화될 경우, 금속 배선을 형성하기 위한 식각 공정 시 식각 특성 불량으로 인하여 원하는 피치(pitch)를 구현하기가 어렵다. 따라서, CVD 방법을 이용한 텅스텐(W)막 형성 공정 시 표면 돌기를 고려하여 식각 공정에 영향을 미치지 않는 낮은 증착 높이로 텅스텐(W)막을 형성하고 있다. In the case of a flash memory device, a metal film (particularly a tungsten (W) film) forming process using a CVD (Chemical Vapor Deposition) method is performed to form a metal wiring. In the case of the tungsten (W) film forming process, when the CVD method is used as compared to the PVD method, the thicker the thickness, the worse the surface protrusion. When the surface protrusion is deteriorated, it is difficult to achieve the desired pitch due to the poor etching characteristics in the etching process for forming the metal wiring. Therefore, the tungsten (W) film is formed at a low deposition height that does not affect the etching process in consideration of surface projections in the tungsten (W) film formation process using the CVD method.

반도체 소자가 고집적화되어 감에 따라 금속 배선의 선 폭이 감소하게 되고 이에 따라 텅스텐(W)막 증착 높이는 계속 감소시켜야 하는 문제가 발생하며, 텅스텐(W)막 증착 두께가 계속 감소될 경우 비저항이 증가하게 된다. 따라서, CVD 방법을 이용한 텅스텐(W)막 형성 공정 시 발생하는 표면 돌기를 개선하기 위해 많은 연구가 진행되고 있다. As semiconductor devices become more integrated, the line width of metal wirings decreases, which causes the problem that the tungsten (W) film deposition height must be continuously reduced, and the resistivity increases when the tungsten (W) film deposition thickness is continuously reduced. Done. Therefore, many studies have been conducted to improve surface protrusions generated during the tungsten (W) film formation process using the CVD method.

최근 들어, CVD 방법을 이용한 텅스텐(W)막 형성 공정 시 발생하는 표면 돌기를 개선하기 위해 LRW(Low Resistivity Tungsten) 공정을 도입하고 있다. LRW 공 정을 도입할 경우, B2H6 가스의 감소로 인해 텅스텐(W)막의 그레인 사이즈(grain size)가 기존 CVD 방법을 이용한 텅스텐(W)막 형성 공정 시보다 많이 증가하여 그레인 바운더리(grain boundary) 부분으로 전자(electron)를 스케터링(scattering)하는 것을 효과적으로 감소시켜 저항 특성을 개선할 수 있다. Recently, the Low Resistivity Tungsten (LRW) process has been introduced to improve the surface projections generated during the tungsten (W) film formation process using the CVD method. When the LRW process is introduced, the grain size of the tungsten (W) film is increased due to the reduction of B 2 H 6 gas than that of the tungsten (W) film forming process using the conventional CVD method. Scattering of electrons into the boundary portion can be effectively reduced to improve resistance properties.

그러나, 그레인 사이즈 증가에 따른 표면 돌기가 증가하여 금속 배선을 형성하기 위한 텅스텐(W)막 식각 공정 시 식각 불량의 문제로 적용하기가 어려워 현재 다마신(damascene) 구조에만 적용하고 있다. However, due to the increased surface size due to the increase in grain size, it is difficult to apply it as a problem of etching failure in the tungsten (W) film etching process for forming metal wiring, and is currently applied only to a damascene structure.

본 발명은 금속막(특히, 텅스텐(W)막) 형성시 발생하는 웨이퍼 돌기를 개선하기 위한 반도체 소자의 금속 배선 형성방법을 제공하는 데 있다. SUMMARY OF THE INVENTION The present invention provides a method for forming a metal wiring of a semiconductor device for improving wafer protrusions generated when forming a metal film (particularly, a tungsten (W) film).

본 발명의 실시 예에 따른 반도체 소자의 금속 배선 형성방법은, 반도체 기판상에 금속막을 형성한다. 금속막 상에 제1 고밀도 플라즈마(HDP) 산화막을 형성한다. In the method for forming metal wirings of a semiconductor device according to an embodiment of the present invention, a metal film is formed on a semiconductor substrate. A first high density plasma (HDP) oxide film is formed on the metal film.

상기에서, 반도체 기판과 금속막 사이에 절연막 및 베리어 메탈막을 더 형성한다. 베리어 메탈막은 티타늄(Ti)막과 티타늄 질화막(TiN)이 적층 된 구조로 형성한다. 금속막은 화학적 기상 증착법(Chemical Vapor Deposition; CVD)을 이용한 텅 스텐(W)막으로 형성한다. In the above, an insulating film and a barrier metal film are further formed between the semiconductor substrate and the metal film. The barrier metal film is formed in a structure in which a titanium (Ti) film and a titanium nitride film (TiN) are stacked. The metal film is formed of a tungsten (W) film using chemical vapor deposition (CVD).

제1 고밀도 플라즈마(HDP) 산화막은 증착 반응 가스에 의해 스퍼터링 및 증착 공정이 동시에 이루어진다. 스퍼터링 효과를 증가시키기 위한 증착 반응 가스는 Ar, Xe, Ne 또는 Kr 등이다. 스퍼터링 효과는 금속막 형성 공정 시 발생하는 돌기가 심할수록 커진다. The first high density plasma (HDP) oxide film is sputtered and deposited at the same time by a deposition reaction gas. Deposition reaction gases for increasing the sputtering effect are Ar, Xe, Ne or Kr and the like. The sputtering effect increases as the protrusions generated in the metal film forming process become severe.

제1 고밀도 플라즈마(HDP) 산화막을 형성한 후 제1 고밀도 플라즈마(HDP) 산화막을 제거하고, 금속막 상에 제2 고밀도 플라즈마(HDP) 산화막을 형성한다. 금속막 형성 공정 시 발생하는 돌기가 제거되지 않을 경우, 제1 고밀도 플라즈마(HDP) 산화막을 제거하는 공정과 제2 고밀도 플라즈마(HDP) 산화막을 형성하는 공정을 반복하여 금속막의 돌기를 완전히 제거한다. 제1 고밀도 플라즈마(HDP) 산화막 제거 공정은 습식 및 건식 식각 공정으로 실시한다. After forming the first high density plasma (HDP) oxide film, the first high density plasma (HDP) oxide film is removed, and a second high density plasma (HDP) oxide film is formed on the metal film. When the projections generated during the metal film formation process are not removed, the process of removing the first high density plasma (HDP) oxide film and the process of forming the second high density plasma (HDP) oxide film are repeated to completely remove the projections of the metal film. The first high density plasma (HDP) oxide film removing process is performed by wet and dry etching processes.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명의 일 실시 예에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of devices sequentially illustrated to explain a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 소자 분리막, 트랜지스터, 콘택 플러그 등 소정의 구조(미도시)가 형성된 반도체 기판(100)이 제공된다.Referring to FIG. 1A, a semiconductor substrate 100 having a predetermined structure (not shown), such as an isolation layer, a transistor, and a contact plug, is provided.

그런 다음, 반도체 기판(100) 상부에 절연막(102), 베리어 메탈막(104) 및 금속막(106)을 형성한다. 이때, 베리어 메탈막(104)은 티타늄(Ti)막과 티타늄 질화 막(TiN)이 적층 된 구조로 형성하고, 금속막(106)은 화학적 기상 증착법(Chemical Vapor Deposition; CVD)을 이용한 텅스텐(W)막으로 형성한다. 화학적 기상 증착법(CVD)을 이용하여 텅스텐(W)막 형성 공정 시 표면이 거칠어져 수많은 돌기가 형성된다(A). Next, an insulating film 102, a barrier metal film 104, and a metal film 106 are formed on the semiconductor substrate 100. At this time, the barrier metal film 104 is formed of a structure in which a titanium (Ti) film and a titanium nitride film (TiN) are stacked, and the metal film 106 is made of tungsten (W) using chemical vapor deposition (CVD). ) To form a film. In the tungsten (W) film formation process using chemical vapor deposition (CVD), the surface is roughened to form a number of protrusions (A).

도 1b를 참조하면, 금속막(106) 상부에 하드 마스크막(108)을 형성한다. 이때, 금속막(106) 표면의 돌기가 제거되어 금속막(106) 표면이 평탄화되도록 하드 마스크막(108)은 고밀도 플라즈마(High Density Plasma; HDP) 산화막으로 형성한다. 고밀도 플라즈마(HDP) 산화막은 증착 반응 가스에 의해 스퍼터링(sputtering) 및 증착(deposition) 공정이 동시에 이루어지는 특성이 있다. 고밀도 플라즈마(HDP) 산화막 형성 공정 중 스퍼터링 현상의 경우, 금속막(106)의 돌기에 대한 스퍼터링 이온의 입사각(θ)이 45도 내지 60도에서 가장 큰 효과가 발생하며, 이 경우 증착 공정도 동시에 진행된다. 금속막(106)에서 돌기가 없는 지역은 스퍼터링 이온의 입사각(θ)이 90도에 가깝기 때문에 스퍼터링 효과가 현저히 낮아지고 증착 공정만 이루어진다. 고밀도 플라즈마(HDP) 산화막 형성 공정 시 스퍼터링 효과를 증가시키기 위해 Ar, Xe, Ne 또는 Kr 등의 반응 가스를 이용한다. Referring to FIG. 1B, a hard mask film 108 is formed on the metal film 106. In this case, the hard mask film 108 is formed of a high density plasma (HDP) oxide film so that protrusions on the surface of the metal film 106 are removed to planarize the surface of the metal film 106. The high density plasma (HDP) oxide film is characterized in that the sputtering and deposition processes are simultaneously performed by the deposition reaction gas. In the case of the sputtering phenomenon during the high density plasma (HDP) oxide film forming process, the incident angle (θ) of the sputtering ions to the projections of the metal film 106 has the greatest effect at 45 degrees to 60 degrees, in which case the deposition process Proceed. In the region where there is no projection in the metal film 106, since the incident angle θ of the sputtering ions is close to 90 degrees, the sputtering effect is significantly lowered and only the deposition process is performed. In order to increase the sputtering effect in a high density plasma (HDP) oxide film forming process, a reaction gas such as Ar, Xe, Ne, or Kr is used.

또한, 화학적 기상 증착법(CVD)을 이용하여 텅스텐(W)막을 형성한 경우에 고밀도 플라즈마(HDP) 산화막 증착 시 스퍼터링 효과가 매우 크게 발생하며, 이러한 스퍼터링 효과의 경우 텅스텐(W)막의 돌기가 심할수록 더욱 더 커진다. In addition, when the tungsten (W) film is formed by chemical vapor deposition (CVD), the sputtering effect is very large when the high density plasma (HDP) oxide film is deposited. Getting bigger

따라서, 고밀도 플라즈마(HDP) 산화막 형성 공정 시 금속막(106)의 표면 돌기가 심한 지역의 경우에는 증착 공정 대비 스퍼터링 효과가 크기 때문에 금속 막(106)의 표면 돌기를 스퍼터링 현상에 의해 선택적으로 제거할 수 있다. 표면 돌기가 양호한 지역의 경우에는 스퍼터링 이온의 입사각(θ)이 90도에 가까운 관계로 증착 공정만 거의 이루어지고, 스퍼터링 현상은 거의 발생하지 않는다. Therefore, in the case of the region where the surface projections of the metal film 106 are severe during the high density plasma (HDP) oxide film formation process, the surface projections of the metal film 106 may be selectively removed by the sputtering phenomenon because the sputtering effect is greater than that of the deposition process. Can be. In the region where the surface projections are good, only the deposition process is almost performed and the sputtering phenomenon hardly occurs because the incident angle θ of the sputtering ions is close to 90 degrees.

도 1c를 참조하면, 하드 마스크막(108)인 고밀도 플라즈마(HDP) 산화막 형성 공정 시 스퍼터링 현상은 고밀도 플라즈마(HDP) 산화막 증착 공정 중 초기에 주로 발생하기 때문에 고밀도 플라즈마(HDP) 산화막 1회 증착 공정으로 금속막(106)의 표면 돌기가 제거되지 않을 경우, 습식 및 건식 식각 공정을 이용하여 금속막(106) 상부에 형성된 고밀도 플라즈마(HDP) 산화막을 제거한 후 다시 고밀도 플라즈마(HDP) 산화막을 형성하여 금속막(106)의 표면 돌기를 제거하는 공정을 반복하여 금속막(106)의 표면 돌기를 완전히 제거한다. Referring to FIG. 1C, the sputtering phenomenon occurs during the high density plasma (HDP) oxide film formation process, which is the hard mask film 108, mainly occurs early in the high density plasma (HDP) oxide film deposition process. When the surface protrusions of the metal film 106 are not removed, the high density plasma (HDP) oxide film formed on the metal film 106 is removed by using wet and dry etching processes, and then a high density plasma (HDP) oxide film is formed again. The process of removing the surface protrusions of the metal film 106 is repeated to completely remove the surface protrusions of the metal film 106.

그런 다음, 식각 공정으로 하드 마스크막(108), 금속막(106) 및 베리어 메탈막(104)을 식각하여 금속 배선을 형성한다.Then, the hard mask film 108, the metal film 106 and the barrier metal film 104 are etched by an etching process to form metal wires.

상기의 하드 마스크막(108)인 고밀도 플라즈마(HDP) 산화막 형성 공정으로 금속막(106)의 표면 돌기를 제거함으로써 금속 배선을 형성하기 위한 식각 공정 시 원하는 피치의 금속 배선을 형성할 수 있고, 후속 공정인 절연막 매립 공정을 안정적으로 실시할 수 있다. By removing the surface projections of the metal film 106 by the high density plasma (HDP) oxide film forming process, which is the hard mask film 108 described above, metal wirings having a desired pitch can be formed during an etching process for forming metal wirings. The insulating film embedding step, which is a step, can be stably performed.

도 2는 고밀도 플라즈마(HDP) 산화막 형성 공정 시 스퍼터링 이온(즉, Ar 가스)의 입사각(θ)에 따른 스퍼터링 효과를 나타낸 그래프이다. FIG. 2 is a graph illustrating a sputtering effect according to an incident angle θ of sputtering ions (ie, Ar gas) in a high density plasma (HDP) oxide film forming process.

곡선 a는 각각의 입사각(θ)에 따라 스퍼터링 효과가 발생하여 표면이 거칠 어져 발생하는 돌기가 제거되는 양을 나타낸 그래프로서, 입사각(θ)이 웨이퍼에서 0도 또는 90도일 경우 스퍼터링 효과가 거의 발생하지 않으며, 입사각(θ)이 웨이퍼에서 45도 내지 60도일 경우 스퍼터링 효과가 최대로 발생한다. Curve a is a graph showing the amount of sputtering effect generated according to each incident angle θ to remove the projections caused by roughness of the surface. When the incident angle θ is 0 degrees or 90 degrees on the wafer, the sputtering effect almost occurs. The sputtering effect is maximized when the incident angle θ is 45 degrees to 60 degrees on the wafer.

곡선 b는 각각의 입사각(θ)에 따른 스퍼터링 효과 발생 시 고밀도 플라즈마(HDP) 산화막의 두께가 감소하는 양을 나타낸 그래프로서, 스퍼터링 효과가 최대로 발생되는 입사각(θ)에서는 고밀도 플라즈마(HDP) 산화막의 두께가 감소되는 양이 많고, 스퍼터링 효과가 거의 발생되지 않는 입사각(θ)에서는 고밀도 플라즈마(HDP) 산화막의 두께가 감소하는 양이 적다. Curve b is a graph showing the amount of decrease in the thickness of the high density plasma (HDP) oxide film when the sputtering effect occurs according to each incident angle (θ), and the high density plasma (HDP) oxide film at the incident angle (θ) at which the sputtering effect is maximized. There is a large amount of reduced thickness, and a small amount of reduced thickness of the high-density plasma (HDP) oxide film is reduced at the incident angle [theta] where the sputtering effect hardly occurs.

도 3은 웨이퍼에 인가되는 바이어스(bias)에 따라 스퍼터링 효과가 발생하는 비를 나타낸 그래프로서, 웨이퍼에 바이어스가 많이 인가될수록 전압 차로 인해 아르곤(Ar) 이온이 가속이 붙어 스퍼터링 효과가 증가하게 된다. 3 is a graph illustrating a ratio in which a sputtering effect occurs according to a bias applied to a wafer. As the bias is applied to a wafer, argon (Ar) ions are accelerated due to a voltage difference, thereby increasing the sputtering effect.

본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었으나, 상기한 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명의 효과는 다음과 같다.As described above, the effects of the present invention are as follows.

첫째, 고밀도 플라즈마(High Density Plasma; HDP) 산화막 형성 공정 시 금속막의 돌기가 심한 지역의 경우에는 증착 공정 대비 스퍼터링(sputtering) 효과가 크기 때문에 금속막의 돌기를 스퍼터링 현상에 의해 선택적으로 제거할 수 있다. First, in the case of a high density plasma (HDP) oxide film forming process in the region where the metal film projections are severe, the sputtering effect is greater than the deposition process can be selectively removed by the sputtering phenomenon.

둘째, 금속막의 돌기를 제거함으로써 금속 배선을 형성하기 위한 식각 공정 시 원하는 피치의 금속 배선을 형성할 수 있고, 후속 공정인 절연막 매립 공정을 안정적으로 실시할 수 있다. Second, by removing the projections of the metal film can be formed a metal wiring of a desired pitch during the etching process for forming the metal wiring, it is possible to stably perform the insulating film filling process, a subsequent process.

Claims (10)

반도체 기판상에 금속막을 형성하는 단계; 및Forming a metal film on the semiconductor substrate; And 상기 금속막 상에 제1 고밀도 플라즈마(HDP) 산화막을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법.Forming a first high density plasma (HDP) oxide film on the metal film. 제1항에 있어서, The method of claim 1, 상기 반도체 기판과 상기 금속막 사이에 절연막 및 베리어 메탈막을 더 형성하는 반도체 소자의 금속 배선 형성방법.And forming an insulating film and a barrier metal film between the semiconductor substrate and the metal film. 제2항에 있어서, The method of claim 2, 상기 베리어 메탈막은 티타늄(Ti)막과 티타늄 질화막(TiN)이 적층 된 구조로 형성하는 반도체 소자의 금속 배선 형성방법.The barrier metal film is a metal wiring formation method of a semiconductor device to form a structure in which a titanium (Ti) film and a titanium nitride film (TiN) is laminated. 제1항에 있어서, The method of claim 1, 상기 금속막은 화학적 기상 증착법(Chemical Vapor Deposition; CVD)을 이용한 텅스텐(W)막으로 형성하는 반도체 소자의 금속 배선 형성방법.The metal film is formed of a tungsten (W) film using a chemical vapor deposition (CVD) method of forming a metal wiring of a semiconductor device. 제1항에 있어서, The method of claim 1, 상기 제1 고밀도 플라즈마(HDP) 산화막은 증착 반응 가스에 의해 스퍼터링 및 증착 공정이 동시에 이루어지는 반도체 소자의 금속 배선 형성방법.The first high density plasma (HDP) oxide film is a metal wiring formation method of the semiconductor device is a sputtering and the deposition process at the same time by the deposition reaction gas. 제5항에 있어서, The method of claim 5, 상기 스퍼터링 효과를 증가시키기 위한 상기 증착 반응 가스는 Ar, Xe, Ne 또는 Kr 등인 반도체 소자의 금속 배선 형성방법.And the deposition reaction gas for increasing the sputtering effect is Ar, Xe, Ne, Kr or the like. 제5항에 있어서,The method of claim 5, 상기 스퍼터링 효과는 상기 금속막 형성 공정 시 발생하는 돌기가 심할수록 커지는 반도체 소자의 금속 배선 형성방법.The sputtering effect is a metal wiring forming method of the semiconductor device is increased as the protrusions generated during the metal film forming process. 제1항에 있어서,The method of claim 1, 상기 제1 고밀도 플라즈마(HDP) 산화막을 형성한 후After forming the first high density plasma (HDP) oxide film 상기 제1 고밀도 플라즈마(HDP) 산화막을 제거하는 단계; 및Removing the first high density plasma (HDP) oxide film; And 상기 금속막 상에 제2 고밀도 플라즈마(HDP) 산화막을 형성하는 단계를 더 포함하는 반도체 소자의 금속 배선 형성방법. And forming a second high density plasma (HDP) oxide film on the metal film. 제7항 또는 제8항에 있어서,The method according to claim 7 or 8, 상기 금속막 형성 공정 시 발생하는 상기 돌기가 제거되지 않을 경우, 상기 제1 고밀도 플라즈마(HDP) 산화막을 제거하는 공정과 상기 제2 고밀도 플라즈마(HDP) 산화막을 형성하는 공정을 반복하여 상기 금속막의 돌기를 완전히 제거하는 반도체 소자의 금속 배선 형성방법. If the protrusions generated during the metal film forming process are not removed, the process of removing the first high density plasma (HDP) oxide film and the process of forming the second high density plasma (HDP) oxide film are repeated, thereby forming the protrusions of the metal film. Method of forming a metal wiring of the semiconductor device to completely remove. 제8항에 있어서,The method of claim 8, 상기 제1 고밀도 플라즈마(HDP) 산화막 제거 공정은 습식 및 건식 식각 공정으로 실시하는 반도체 소자의 금속 배선 형성방법. And removing the first high density plasma (HDP) oxide film by a wet and dry etching process.
KR1020070063587A 2007-06-27 2007-06-27 Method of forming a metal wire in a semiconductor device KR20080114228A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11908736B2 (en) 2017-08-30 2024-02-20 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11908736B2 (en) 2017-08-30 2024-02-20 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures

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