JP2525630B2 - Method for manufacturing thin film transistor - Google Patents

Description

The present invention relates to a method for manufacturing a thin film transistor (hereinafter referred to as TFT).

[Conventional technology]

In a conventional TFT, as shown in FIG. 2, a high concentration impurity region (first region) and a low concentration impurity region (second region) are formed.
Area) contacted each other. In the figure, 101 is an insulating substrate, 103 is a gate insulating film, and 105 is polycrystalline (amorphous).
Low-concentration impurity region in silicon (second region), 107 is a gate electrode, 108 is a high-concentration impurity region in polycrystalline (amorphous) silicon (first region), 109 is an interlayer insulating film, and 110 is It is a wiring material.

[Problems to be solved by the invention]

In order to control the threshold voltage of TFT (hereinafter referred to as Vth), impurities of about 10 ¹⁷ cm ⁻³ are mixed in the second region. In the case of NchTFT, impurities such as phosphorus and arsenic are mixed in the first region to form an N-type semiconductor. When impurities such as boron that become a P-type semiconductor are mixed in the second region, a potential barrier is formed between the first region and the second region when the gate is at zero bias (TFT is off). However, in the case of polycrystalline and amorphous silicon TFTs, there are many localized levels formed near the boundary surface between the first and second regions.
The leak current becomes large. On the other hand, when an impurity that becomes an N-type semiconductor is mixed in the second region, the leak current is large because of the reason described above and the potential barrier is further reduced.
After all, in order to reduce the leak current in the off state of the polycrystalline and amorphous silicon TFTs, it is preferable that the second region is close to the intrinsic semiconductor. However, in this case, the Vth of the TFT cannot be controlled, and as a result, the leak current may increase.

The present invention solves the above problems, and an object of the present invention is to realize a polycrystalline and amorphous silicon TFT in which Vth can be controlled and leakage current in the off state is small.

[Means for solving problems]

In order to solve the above problems, a method of manufacturing a thin film transistor according to the present invention includes (a) a step of forming a polycrystalline or amorphous silicon thin film on a substrate, and (b) the polycrystalline or amorphous silicon thin film. A step of forming a gate insulating film thereon, (c) a step of forming two first electrodes forming a part of a gate electrode of a thin film transistor on the gate insulating film with a space therebetween, (d) the first electrode Is used as a mask to introduce impurities into the polycrystalline or amorphous silicon thin film to form a channel between the first region to be a source / drain and the two first electrodes formed apart from each other. Forming a second region and a third region in which impurities are not introduced under the first electrode, (e) forming a second electrode that constitutes the gate electrode of the thin film transistor together with the first electrode, and forming the second region in the second region. Wherein the of the gate insulating film on the first
And (f) introducing impurities into the first region using the first electrode and the second electrode as a mask.

〔Example〕

1 (a) to 1 (e) are cross-sectional views of a TFT according to an embodiment of the present invention arranged in the order of manufacturing steps. FIG. 6F is a plan view of the state of FIG. FIG.
In, 101 is an insulating substrate, and 102 is a polycrystalline or amorphous silicon thin film formed on the insulating substrate 101. 103
Is a gate insulating film and is formed by a thermal oxidation method, a CVD method, or the like. Reference numeral 104 denotes a mask electrode (first electrode) for forming a low concentration impurity region, which becomes a part of the gate electrode. Mask electrode
A material such as polycrystalline silicon is used for 104. In FIG. 2B, 105 is a low concentration impurity region, and 106 is a further low concentration impurity region (third region). From the state shown in FIG. 1A, the low concentration impurity region 105 is formed by the ion implantation method or the thermal diffusion method. 106 is a state close to an intrinsic semiconductor.
In FIG. 7C, reference numeral 107 denotes a gate electrode, which is made of a material such as polycrystalline silicon. A plan view at this time is shown in FIG. In FIG. 3D, 108 is a high concentration impurity region. From the state shown in FIG. 3C, a high concentration impurity region (first region) 108 to be a source / drain region is formed by an ion implantation method or a thermal diffusion method. Since the impurity concentration of 108 is about three orders of magnitude higher than that of the low-concentration impurity region (second region) 105 that becomes a channel, even if the impurity that becomes an inverse type semiconductor initially exists in the first region, the step of forming 108 Thus, a desired type of semiconductor can be obtained. In FIG. 7E, 109 is an interlayer insulating film made of silicon oxide or the like, and 110 is a wiring material made of aluminum alloy or the like.

FIG. 3 shows the drain current-gate voltage characteristics of the TFT in the embodiment of the present invention. The drain voltage of FIG.
V, the figure (b) shows the case of a drain voltage of 16 V. In each figure, the structure of the present invention is
It has TFT characteristics. These are examples of polycrystalline silicon TFTs, which have a channel length L = 6 μm, a channel width W = 10 μm, phosphorus in the first region 1 × 10 ²⁰ cm ⁻³ , and boron in the second region 1 × 1.
0 ¹⁷ cm ^{-3 It is} mixed. As apparent from FIG. 3, by using the present invention, the leak current at the time of OFF is reduced by about two digits as compared with the conventional one. That is, the on / off ratio is improved by about two digits.

〔The invention's effect〕

As described above, by using the present invention, Vth can be controlled, and the leakage current in the off state is small, that is, polycrystalline and non-crystalline silicon having a large on / off ratio.
TFT has been realized.

Furthermore, since the size of the third region can be uniquely determined from the size of the mask electrode, the size of the third region can be formed with high accuracy.

[Brief description of drawings]

1A to 1F are manufacturing process diagrams of a TFT according to an embodiment of the present invention. FIG. 6F is a plan view in the state of FIG. Figure 2 is a sectional view of a conventional TFT. 3 (a) and 3 (b) are diagrams showing the drain current-gate voltage characteristics of the TFT in the embodiment of the present invention. 101 ... Insulating substrate 102 ... Polycrystalline (amorphous) silicon 103 ... Gate insulating film 104 ... Mask electrode (part of gate electrode) 105 ... Low-concentration impurity region (second region) 106 ... Region of lower concentration impurity than the second region 105 (third region) 107 ... Gate electrode 108 ... High concentration impurity region (first region) 109 ... Interlayer insulating film 110 ... Wiring material

Claims (1)

(57) [Claims] 1. A process of forming a polycrystalline or amorphous silicon thin film on a substrate, a process of forming a gate insulating film on the polycrystalline or amorphous silicon thin film, and a thin film transistor. Forming two first electrodes forming a part of the gate electrode on the gate insulating film at a distance from each other, (d) using the first electrode as a mask in the polycrystalline or amorphous silicon thin film By introducing impurities,
A first region serving as a source / drain, and a second region serving as a channel between the two first electrodes formed apart from each other,
Forming a third region in which impurities are not introduced under the first electrode, (e) forming a second electrode that constitutes a gate electrode of the thin film transistor together with the first electrode, the gate insulating film on the second region A method of manufacturing a thin film transistor, comprising: a step of forming over the first electrode and the first electrode; (f) a step of introducing an impurity into the first region using the first electrode and the second electrode as a mask.