JP4725544B2 - Manufacturing method of electro-optical device - Google Patents

Description

  The present invention relates to a method for manufacturing an electro-optical device having a multilayer structure.

  In general, an electro-optical device, for example, a liquid crystal device that performs predetermined display using liquid crystal as an electro-optical material has a configuration in which liquid crystal is sandwiched between a pair of substrates. Among these, in an electro-optical device such as an active matrix driving type liquid crystal device by TFT driving, TFD driving, etc., at each intersection of a large number of scanning lines (gate lines) and data lines (source lines) arranged vertically and horizontally. Correspondingly, a pixel electrode and a switching element are provided on a substrate (active matrix substrate).

  A switching element such as a TFT element is turned on by an on signal supplied to the gate line, and an image signal supplied via the source line is written to the pixel electrode (transparent electrode (ITO)). Thereby, a voltage based on the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode to change the arrangement of the liquid crystal molecules. In this way, the transmittance of the pixel is changed, and light passing through the pixel electrode and the liquid crystal layer is changed according to the image signal to perform image display.

  An element substrate constituting such a switching element is formed by laminating a semiconductor thin film, an insulating thin film (interlayer insulating film) or a conductive thin film having a predetermined pattern on a glass or quartz substrate. That is, a TFT substrate and the like are formed by repeating a film forming process of various films and a photolithography process.

  The TFT element includes a semiconductor layer, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film. In the semiconductor layer constituting the TFT element, a channel region, a source region, and a drain region are formed by ion implantation. Specifically, the semiconductor layer is subjected to channel doping for forming a channel, LDD (Lightly Doped Drain) ion implantation treatment, and two or three ion implantation treatments for forming source and drain regions. .

In channel doping, ion implantation is performed on the entire semiconductor layer. In LDD ion implantation performed after the gate electrode is formed, ion implantation is performed using the gate electrode as a mask. In ion implantation into the source and drain regions, ion implantation is performed only on a partial region of the semiconductor layer using a mask covering the LDD portion.
Japanese Patent Application No. 2002-190597

  By the way, the on-current characteristics of the transistor depend on the sheet resistance. The on-current can be increased by reducing the sheet resistance. In order to reduce the sheet resistance, the dose to the semiconductor layer may be increased. However, when the dose increases, lattice defects and junction leaks also increase and off-leakage increases. It is necessary to consider at the time of design the contradictory control of increasing the on-current of the transistor and reducing the off-leakage.

  The channel doping for controlling the threshold characteristics of the transistor is performed prior to the LDD ion implantation for forming the LDD structure. That is, the semiconductor layer has both the one conductivity type and the opposite conductivity type impurities, and has a disadvantage that the impurity concentration is high for the sheet resistance and the off-leakage is relatively high.

  Therefore, in Patent Document 1, the range of channel doping is limited, and the source / drain regions in the semiconductor layer are composed of three regions having different impurity concentrations, thereby reducing the sheet resistance and improving the on-current characteristics. Techniques for making them disclosed are disclosed.

  However, this proposal also has the problem that the sheet resistance cannot be sufficiently reduced because both of the three regions of the semiconductor layer are doped with impurities of one and opposite conductivity types in the region near the gate. It was.

  The present invention has been made in view of such a problem, and an object thereof is to provide a method for manufacturing an electro-optical device that can sufficiently reduce sheet resistance and also reduce off-leakage.

  The method of manufacturing an electro-optical device according to the present invention includes a step of forming a semiconductor layer on a substrate, a step of forming a gate insulating film on the semiconductor layer, and a region narrower than a region where a gate electrode is formed in a plane. A step of forming a channel region by introducing an impurity having a conductivity type opposite to that of a source region or a drain region into the semiconductor layer of the region, a step of forming the gate electrode, and the reverse conductivity after the formation of the gate electrode. A step of thermally diffusing an impurity of a type in a region overlapping with the gate electrode; and a step of introducing a impurity into the semiconductor layer adjacent to the channel region to form a source region and a drain region. To do.

  According to such a configuration, the semiconductor layer and the gate insulating film are formed on the substrate. A channel region is formed by introducing an impurity of a reverse conductivity type into a region narrower than the region where the gate electrode is formed in plan view of the semiconductor layer. A gate electrode is formed on the gate insulating film. After the formation of the gate electrode, the reverse conductivity type impurity is thermally diffused under the gate electrode. Thereby, for example, the channel region can be formed in the same region as the gate electrode formation region in plan view. A source region and a drain region are formed by introducing one conductivity type impurity into the semiconductor layer on both sides of the channel region. Thus, only one conductivity type impurity is introduced into the source region and the drain region, and the dose is small, so that the sheet resistance is low and the on-current can be increased. In addition, since the impurity dose is small, lattice defects can be reduced and off-leakage can be reduced.

  Further, in the thermal diffusion step, the reverse conductivity type impurity is diffused only in a region overlapping with a formation region of the gate electrode.

  Thus, only one conductivity type impurity is introduced into the source region and the drain region, and the dose is small, so that the sheet resistance is low and the on-current can be increased. In addition, since the impurity dose is small, lattice defects can be reduced and off-leakage can be reduced.

  Further, the step of forming the source region and the drain region may include a step of forming a first conductivity type having an impurity concentration lower than that of the source region and the drain region using the gate electrode as a mask after the formation of the gate electrode. Introducing impurities into the semiconductor layer to form a low-concentration impurity region, and using a mask covering a region wider than the formation region of the gate electrode, introducing one conductivity type impurity into the semiconductor layer And a step of forming a source region and a drain region.

  According to such a configuration, the low concentration impurity regions of the source region and the drain region can be formed without introducing reverse conductivity type impurities. A low concentration impurity region can be formed with a small dose, sheet resistance is low, and an on-current can be increased. In addition, since the impurity dose is small, lattice defects can be reduced and off-leakage can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing an electro-optical device manufactured by the method of manufacturing an electro-optical device according to the first embodiment of the invention. This embodiment is applied to a liquid crystal device using a TFT substrate as an electro-optical device, and FIG. 1 shows the liquid crystal device which is an electro-optical device as viewed from the counter substrate side together with each component formed thereon. It is a top view. FIG. 2 is a cross-sectional view of the liquid crystal device after the assembly process in which the element substrate and the counter substrate are bonded to each other and the liquid crystal is sealed is cut along the line HH ′ in FIG. FIG. 3 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels constituting the pixel region of the liquid crystal device of FIGS. FIG. 4 is an explanatory view showing the structure of a TFT element employed in the electro-optical device. FIG. 5 is a flowchart showing a method for manufacturing a TFT element. FIG. 6 is a process diagram showing the manufacturing process of the TFT element in the order of processes. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

First, an overall configuration of a liquid crystal device that is an electro-optical device according to the present embodiment will be described with reference to FIGS. 1 to 3.
As shown in FIGS. 2 and 3, the liquid crystal device includes a TFT substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and a counter substrate 20 made of, for example, a glass substrate or a quartz substrate. The liquid crystal 50 is sealed between the two. The TFT substrate 10 and the counter substrate 20 that are arranged to face each other are bonded together by a sealing material 52.

  On the TFT substrate 10, pixel electrodes (ITO) 9a constituting pixels are arranged in a matrix. A counter electrode (ITO) 21 is provided on the entire surface of the counter substrate 20. On the pixel electrode 9 a of the TFT substrate 10, an alignment film 16 that has been subjected to a rubbing process is provided. On the other hand, an alignment film 22 subjected to a rubbing process is also provided on the counter electrode 21 formed over the entire surface of the counter substrate 20. The alignment films 16 and 22 are made of a transparent organic film such as a polyimide film, for example.

  FIG. 3 shows an equivalent circuit of elements on the TFT substrate 10 constituting the pixel. As shown in FIG. 3, in the pixel region, a plurality of scanning lines 11 and a plurality of data lines 6a are wired so as to intersect with each other, and a pixel electrode is formed in an area partitioned by the scanning lines 11 and the data lines 6a. 9a are arranged in a matrix. A TFT 30 is provided corresponding to each intersection of the scanning line 11 and the data line 6 a, and the pixel electrode 9 a is electrically connected to the TFT 30.

  The TFT 30 is turned on by the ON signal of the scanning line 11, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50. A storage capacitor 70 is provided in parallel with the pixel electrode 9a. The storage capacitor 70 extends the holding time of the voltage applied to the liquid crystal 50. For example, the image signal is held for a period that is three orders of magnitude longer than the time supplied to the pixel electrode 9a. The voltage holding characteristic is improved, and an image display with a high contrast ratio is possible.

  The counter substrate 20 is provided with a light shielding film 53 as a frame for partitioning the display area. In a region outside the light shielding film 53, a sealing material 52 that encloses liquid crystal is formed between the TFT substrate 10 and the counter substrate 20. The sealing material 52 is disposed so as to substantially match the contour shape of the counter substrate 20, and fixes the TFT substrate 10 and the counter substrate 20 to each other. The sealing material 52 is missing at a part of one side of the TFT substrate 10, and a liquid crystal injection port 108 for injecting the liquid crystal 50 is formed in the gap between the TFT substrate 10 and the counter substrate 20 that are bonded together. The After the liquid crystal is injected from the liquid crystal injection port 108, the liquid crystal injection port 108 is sealed with a sealing material 109.

  In an area outside the sealing material 52, an image signal is supplied to the data line 6a at a predetermined timing to drive the data line 6a and an external connection terminal 102 for connection to an external circuit. Are provided along one side of the TFT substrate 10. A scanning line driving circuit 104 that drives the gate electrode 3a by supplying scanning signals to the scanning line 11 and the gate electrode 3a at a predetermined timing is provided along two sides adjacent to the one side. The scanning line driving circuit 104 is formed on the TFT substrate 10 at a position facing the light shielding film 53 inside the sealing material 52. On the TFT substrate 10, wiring 105 connecting the data line driving circuit 101, the scanning line driving circuit 104, the external connection terminal 102, and the vertical conduction terminal 107 is provided to face the three sides of the light shielding film 53. Yes.

  The vertical conduction terminals 107 are formed on the four TFT substrates 10 at the corners of the sealing material 52. Between the TFT substrate 10 and the counter substrate 20, there is provided a vertical conductive material 106 whose lower end is in contact with the vertical conduction terminal 107 and whose upper end is in contact with the counter electrode 21. 10 and the counter substrate 20 are electrically connected.

  Note that the transistors in the data line driving circuit 101 and the scanning line driving circuit 104 may also be configured by TFT elements having the same configuration as the TFT 30 in the pixel region 10a. FIG. 4 shows the configuration of the TFT element.

  As shown in FIG. 4, each TFT element includes a semiconductor layer 41, a gate insulating film 42, and a gate electrode 43. The semiconductor layer 41 has an LDD structure, a channel region 44 is provided below the gate electrode 43, an LDD region 45s and a source region 46s are provided on the source side, and an LDD region 45d and a drain region 46d are provided on the drain side. .

  In the present embodiment, the LDD regions 45s and 45d, which are low concentration impurity regions, are formed by introducing only one conductivity type impurity. The channel region 44 is configured by introducing a reverse conductivity type impurity. The source region 46s and the drain region 46d are regions into which high-concentration impurities are introduced.

  In the conventional TFT manufacturing method, a reverse conductivity type impurity implantation step is performed on the entire surface for channel doping, and then one conductivity type impurity is implanted using the gate electrode as a mask to form an LDD region. Therefore, the LDD region has a large dose amount with respect to the concentration and has many lattice defects. Also, the sheet resistance is high and the on-current is low.

  On the other hand, in the present embodiment, a mask is used for channel doping, and impurities are diffused by thermal diffusion, so that the channel region 44 can be formed only under the gate electrode 43, and the LDD regions 45s and 45d. Is formed with only one conductivity type impurity.

  This reduces the dose when forming the LDD regions 45s and 45d, which are low-concentration impurity regions, reduces lattice defects, reduces off-leakage, decreases sheet resistance, and increases on-current.

(Manufacturing process)
Next, a manufacturing method of the TFT element of the electro-optical device will be described with reference to FIGS. In FIG. 6, an arrow indicates impurity implantation, for example, ion implantation.

  In step S1 of FIG. 5, the semiconductor layer 41 is formed on the TFT substrate. The semiconductor layer 41 is formed by a plurality of processes. For example, low pressure CVD using a monosilane gas, disilane gas or the like at a flow rate of about 400 to 600 cc / min on a TFT substrate in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. (for example, a pressure of about 20 to An amorphous silicon film is formed by CVD (40 Pa). Next, by performing a heat treatment at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours in a nitrogen atmosphere, the p-Si (polysilicon) film has a thickness of about 50 to 200 nm. Preferably, solid phase growth is performed until the thickness becomes about 100 nm. As a method for solid phase growth, annealing using RTA or laser annealing using an excimer laser or the like may be used. Next, the semiconductor layer 41 having a predetermined pattern is formed by photolithography and etching.

  Next, in step S2, the semiconductor layer 41 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C., to form the gate insulating film 42. The gate insulating film 42 may be a multilayer film using, for example, a high temperature silicon oxide film (HTO film). FIG. 6A shows a state where the gate insulating film 42 is formed.

  Next, in step S3, a mask 61 for determining a channel dope region is formed (FIG. 6B). Originally, the channel dope should be formed only below the gate electrode 43. However, it is difficult to perform channel doping in the same plane region as the gate electrode 43 due to misalignment between the channel dope mask and the mask for patterning the gate electrode. For this reason, in this embodiment, channel doping is performed in a region narrower than the formation region of the gate electrode 43 in a plan view.

  That is, in the present embodiment, the mask 61 has an opening 62 in a region narrower than the region where the gate electrode 43 is formed. Next, in step S4, in order to control the threshold voltage Vth of the TFT element, channel doping is performed using a reverse conductivity type impurity (FIG. 6C). For example, when forming an N-channel transistor, boron, for example, is implanted as a reverse conductivity type impurity, and when forming a P-channel transistor, phosphorus, for example, is implanted as a reverse conductivity type impurity.

If an N-channel transistor is to be formed now, for example, boron ions are doped at a dose of 2 × 10 ¹² ions / cm ² . As indicated by the broken line in FIG. 6C, the reverse conductivity type impurity is implanted into the semiconductor layer 41 only in the region of the opening 62.

  Next, in step S5, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused to make this polysilicon film conductive. Instead of this thermal diffusion, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of this polysilicon film is about 100 to 500 nm, preferably about 350 nm.

  In the present embodiment, in the next step S6, annealing is performed to thermally diffuse the impurities implanted into the semiconductor layer 41. In FIG. 6, illustration of the state of impurity diffusion by this step is omitted. In the next step S7, a gate electrode 43 having a predetermined pattern is formed by photolithography and etching (FIG. 6D).

  In the present embodiment, annealing is performed in the next step S8. By this annealing treatment, the impurities implanted into the semiconductor layer 41 are thermally diffused. Since the thermal conductivity of the gate electrode 43 is higher than the thermal conductivity of the gate insulating film 42, the effect of thermal diffusion is high immediately below the gate electrode 43. Thereby, it is easy to suppress the thermal diffusion of impurities only directly below the gate electrode 43. This thermal diffusion is performed while controlling the temperature and time so that the impurity implanted by channel doping diffuses into the same region as the formation region of the gate electrode 43 in a plan view. In this way, in the formation region of the gate electrode 43, the channel region 44 made of the reverse conductivity type impurity is formed immediately below the gate electrode 43 (FIG. 6E).

  Note that, even when the diffusion control cannot be performed with high accuracy, the thermal diffusion is controlled so that the reverse-conductivity type impurity is planarly contained in the formation region of the gate electrode 43.

  Depending on the misalignment between the channel dope mask and the mask for patterning the gate electrode and the thermal diffusion control for the impurity, the impurity diffusion for one of the source side and the drain side may be larger than the impurity diffusion for the other. Can be considered. Even in this case, in this embodiment, the impurity diffusion in at least one direction is designed so as not to exceed the formation region of the gate electrode 43 in a plane.

Next, in step S9, in order to form the LDD regions 45s and 45d in the semiconductor layer 41, one conductivity type impurity is implanted. In this case, for example, phosphorus ions are implanted at a dose of 3 × 10 ¹³ ions / cm ^{2 using} the gate electrode 43 as a mask. By using the gate electrode 43 as a mask, the LDD regions 45s and 45d are formed in a self-aligned manner. In FIG. 6 (f), a region by this impurity implantation is indicated by a lower right oblique line indicated by a broken line.

Next, in step S10, in order to form the source region 46s and the drain region 46d, a mask 63 having a plane pattern wider than the gate electrode 43 is formed on the gate electrode 43 (FIG. 6G). Next, in step S11, a high-concentration one-conductivity type impurity, for example, phosphorus ions is doped at a dose of 2 × 10 ¹⁵ ions / cm ² . By this ion implantation, the impurity concentration in the regions on both ends of the semiconductor layer 41 is increased, and the source region 46s and the drain region 46d are formed. Further, impurities are introduced at the time of ion implantation in step S9, and regions where impurities are not introduced by the ion implantation in step S11 become low-concentration LDD regions 45s and 45d (FIG. 6 (h)). Finally, the mask 63 is removed to obtain a TFT element (FIG. 6 (i)).

  As described above, in this embodiment, in consideration of misalignment between the mask used for channel doping and the mask used for patterning the gate electrode, the channel doping is planarly narrower than the gate electrode formation region. To implement. Then, an annealing process is performed after the gate electrode material is formed, thereby thermally diffusing impurities due to channel doping to form a channel region that is the same region as the gate electrode in a plan view. That is, since the channel region is formed only directly under the gate electrode and does not extend to the LDD region, the LDD region can be formed only by one conductivity type impurity. Accordingly, an LDD region which is a low concentration impurity region can be formed with a small dose, and sheet resistance can be reduced and an on-current can be increased. In addition, since the impurity dose is small in the LDD region, lattice defects can be reduced and off-leakage can be reduced.

(Second Embodiment)
FIG. 7 is an explanatory view showing a second embodiment of the present invention. This embodiment is applied to a P-channel transistor.

  The P-channel transistor in this embodiment differs from the N-channel transistor in FIG. 4 only in that the conductivity type is different from that in which the LDD region does not exist. Note that when an N-channel transistor and a P-channel transistor are formed on the same substrate, the semiconductor layer 41 ′, the gate insulating film 42 ′, and the gate electrode 43 ′ are formed of the semiconductor layer 41, the gate insulating film 42, and the semiconductor layer 41 of FIG. It is formed in the same process as the gate electrode 43.

  The channel region 71 is formed of one conductivity type impurity, and in plan view, the channel electrode 71 is formed in the same region as the gate electrode 43 ′ or in at least one direction on the source side and the drain side. It is formed so as not to protrude. At both ends of the semiconductor layer 71, a source region 72s and a drain region 72d are formed by high-concentration impurities of opposite conductivity type.

(Manufacturing process)
Next, a manufacturing method of the TFT element in this embodiment will be described with reference to FIG. FIG. 8 is a process chart showing the manufacturing method of the TFT element in the order of processes. In the P-channel transistor manufacturing method, the impurity conductivity type is different from that of the N-channel transistor, and the impurity introduction step for forming the LDD region is omitted.

  The method for forming the semiconductor layer 41 ′ and the gate insulating film 42 ′ shown in FIG. 8A is the same as the method for forming the semiconductor layer 41 and the gate insulating film 42 in FIG. 6. Next, a mask 65 for determining a channel dope region is formed (FIG. 8B). Also in this embodiment, in consideration of misalignment between the channel dope mask and the mask for patterning the gate electrode, the mask 65 has an opening 66 only in a region narrower than the region where the gate electrode 43 ′ is formed. Use what you have.

  Next, in order to control the threshold voltage Vth of the TFT element, an impurity of one conductivity type is implanted (FIG. 8C). In the case of forming a P-channel transistor, phosphorus, for example, is implanted as one conductivity type impurity. In this case, as shown by the broken line in FIG. 8C, the one conductivity type impurity is injected into the semiconductor layer 41 ′ only in the region of the opening 66.

  Next, a gate electrode 43 ′ is formed by the same method as the gate electrode 43 in FIG. 6. At least one of the formation process of the gate electrode 43 ′ and the patterning of the gate electrode 43 ′ is performed with an annealing process for thermally diffusing channel-doped impurities.

  By this annealing treatment, the impurity implanted into the semiconductor layer 41 ′ is thermally diffused and diffused in the same region as the gate electrode 43 ′ in a plan view. Thus, in the formation region of the gate electrode 43 ', a channel region 71 made of one conductivity type impurity is formed immediately below the gate electrode 43' (FIG. 8E).

  Next, in order to form the source region 72s and the drain region 72d in the semiconductor layer 41 ', an impurity of the other conductivity type is implanted. In this case, for example, boron ions are implanted using the gate electrode 43 'as a mask. By using the gate electrode 43 'as a mask, the source region 72s and the drain region 72d are formed in a self-aligned manner.

  As described above, also in this embodiment, in consideration of misalignment between the mask used for channel doping and the mask used for patterning the gate electrode, the channel doping is planarly narrower than the gate electrode formation region. In the plan view, it is formed in the same region as the gate electrode by thermal diffusion. Thereby, also in this Embodiment, the effect similar to 1st Embodiment can be acquired.

(Electronics)
Next, the overall configuration of a projection color display device as an example of an electronic apparatus using the electro-optical device described in detail above as a light valve will be described. FIG. 9 is an explanatory diagram of a projection type color display device.

  In FIG. 9, a liquid crystal projector 1100, which is an example of a projection type color display device according to the present embodiment, prepares three liquid crystal modules including a liquid crystal device having a drive circuit mounted on a TFT array substrate. It is configured as a projector used as 100R, 100G, and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, the light components R, G, and R corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. The light is divided into B and led to the light valves 100R, 100G and 100B corresponding to the respective colors. In particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.

  Note that the present invention can be similarly applied to various active matrix liquid crystal panels (for example, liquid crystal display panels including TFTs (thin film transistors) and TFDs (thin film diodes) as switching elements). In addition to liquid crystal display panels, various devices such as electroluminescence devices, organic electroluminescence devices, plasma display devices, electrophoretic display devices, and devices using electron emission (Field Emission Display and Surface-Conduction Electron-Emitter Display, etc.) The present invention can be similarly applied to the electro-optical device.

1 is a plan view showing an electro-optical device manufactured by a method for manufacturing an electro-optical device according to a first embodiment of the invention. FIG. It is sectional drawing which cut | disconnects and shows the liquid crystal device after the assembly process which bonds an element substrate and a counter substrate together, and encloses a liquid crystal in the position of the HH 'line of FIG. FIG. 3 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels constituting a pixel region of the liquid crystal device of FIGS. 1 and 2. It is explanatory drawing which shows the structure of the TFT element employ | adopted in an electro-optical apparatus. 3 is a flowchart showing a method for manufacturing a TFT element. It is process drawing which shows the manufacturing process of a TFT element in order of a process. It is explanatory drawing which shows the 2nd Embodiment of this invention. It is explanatory drawing which shows the manufacturing method of the TFT element in this Embodiment. It is explanatory drawing of a projection type color display apparatus.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 41 ... Semiconductor layer, 42 ... Gate insulating film, 43 ... Gate electrode, 44 ... Channel region, 45s, 45d ... LDD region, 46s ... Source region, 46d ... Drain region.

Claims (3)

Forming a semiconductor layer on the substrate;
Forming a gate insulating film on the semiconductor layer;
A step of introducing a channel region by introducing an impurity having a conductivity type opposite to that of the source region or the drain region into the semiconductor layer in a region narrower than a region where the gate electrode is formed in a plane;
Forming the gate electrode;
Thermally diffusing the reverse conductivity type impurity in a region overlapping with the gate electrode after forming the gate electrode;
And a step of forming a source region and a drain region by introducing impurities into the semiconductor layer adjacent to the channel region.   2. The method of manufacturing an electro-optical device according to claim 1, wherein, in the thermal diffusion step, the reverse conductivity type impurity is diffused only in a region overlapping with a formation region of the gate electrode. The step of forming the source region and the drain region includes
After the formation of the gate electrode, using the gate electrode as a mask, one conductivity type impurity having an impurity concentration lower than the impurity concentration of the source region and the drain region is introduced into the semiconductor layer to form the low concentration impurity region. Forming, and
Using a mask covering a region wider than a region where the gate electrode is formed, and introducing one conductivity type impurity into the semiconductor layer to form the source region and the drain region;
The method of manufacturing an electro-optical device according to claim 1, wherein:

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