JP2520429B2 - Printed wiring board for mounting electronic components - Google Patents

Printed wiring board for mounting electronic components

Info

Publication number
JP2520429B2
JP2520429B2 JP62271072A JP27107287A JP2520429B2 JP 2520429 B2 JP2520429 B2 JP 2520429B2 JP 62271072 A JP62271072 A JP 62271072A JP 27107287 A JP27107287 A JP 27107287A JP 2520429 B2 JP2520429 B2 JP 2520429B2
Authority
JP
Japan
Prior art keywords
wiring board
opening
adhesive resin
printed wiring
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62271072A
Other languages
Japanese (ja)
Other versions
JPH01112739A (en
Inventor
徹 樋口
武司 加納
宗勇 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62271072A priority Critical patent/JP2520429B2/en
Publication of JPH01112739A publication Critical patent/JPH01112739A/en
Application granted granted Critical
Publication of JP2520429B2 publication Critical patent/JP2520429B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、ICなど電子部品を実装するために用いられ
るプリント配線板に関するものである。Description: TECHNICAL FIELD The present invention relates to a printed wiring board used for mounting an electronic component such as an IC.

［背景技術］ プリント配線板ＡにICなどの電子部品２を実装するに
あたって、プリント配線板Ａに実装用凹部９を設けるこ
とがなされる。すなわち、第７図に示すように配線基板
１に開口部７を設けた他の配線基板８を積層し、開口部
７によって実装用凹所９が設けられたプリント配線板Ａ
を形成するのである。そして配線基板１には配線基板８
との間の電気絶縁性を確保するために、絶縁樹脂等を塗
布硬化させるなどして電気絶縁層４が形成してあり、配
線基板1,8の間に接着樹脂層６を入れて加熱加圧する積
層成形をおこなうことによって、接着樹脂層６で配線基
板1,8を積層接着させることができるのである。[Background Art] When mounting an electronic component 2 such as an IC on the printed wiring board A, a mounting recess 9 is provided in the printed wiring board A. That is, as shown in FIG. 7, a printed wiring board A in which another wiring board 8 having an opening 7 is laminated on the wiring board 1 and a mounting recess 9 is provided by the opening 7 is laminated.
Is formed. The wiring board 1 has a wiring board 8
In order to ensure electric insulation between the wiring board 1 and the wiring board 1, an electric insulation layer 4 is formed by applying and curing an insulating resin or the like. By performing pressure-sensitive lamination molding, the wiring boards 1 and 8 can be laminated and adhered by the adhesive resin layer 6.

ここで、電気絶縁層４及び接着樹脂層６にもそれぞれ
実装用凹所９を形成するために開口部3,5が設けてあ
る。そして第７図のように電気絶縁層４の開口部３の大
きさが接着樹脂層６の開口部５の大きさよりも大きい
と、接着樹脂層６の開口部５の周縁部が電気絶縁層４の
開口部３内にはみ出し、第８図に示すように接着樹脂層
６のはみ出した部分において実装用凹所９内にくぼみ12
ができることになる。しかしこのようにくぼみ12ができ
るとプリント配線板Ａを洗浄するにあたって、くぼみ12
内に洗浄液が残留し、この残留した洗浄液が洗浄後に流
出してプリント配線板Ａの回路13を汚染したりするおそ
れがあり、また電子部品２を実装用凹部９内に封止する
ために封止樹脂を充填するにあたって、くぼみ12内にボ
イドが発生し易く封止が不十分になるおそれがある。特
に積層成形をおこなう際に接着樹脂層６のはみ出し部分
が第８図のように垂れて、この垂れ部分21でくぼみ12は
開口幅が狭まる状態になり、洗浄液の残留やボイドが発
生し易くなるものである。Here, the electric insulating layer 4 and the adhesive resin layer 6 are also provided with openings 3 and 5 for forming mounting recesses 9, respectively. When the size of the opening 3 of the electric insulating layer 4 is larger than the size of the opening 5 of the adhesive resin layer 6 as shown in FIG. Of the adhesive resin layer 6 as shown in FIG. 8, and a recess 12 is formed in the mounting recess 9 as shown in FIG.
You will be able to However, when cleaning the printed wiring board A, if the recess 12 is formed in this way, the recess 12
The cleaning liquid remains inside, and the remaining cleaning liquid may flow out after cleaning to contaminate the circuit 13 of the printed wiring board A. Further, the electronic component 2 is sealed in the mounting recess 9 for sealing. When filling the stop resin, voids are likely to be generated in the recesses 12 and sealing may be insufficient. In particular, when laminating is performed, the protruding portion of the adhesive resin layer 6 hangs as shown in FIG. 8, and the dent 12 has a narrowed opening width at the hanged portion 21, and cleaning liquid remains and voids easily occur It is a thing.

［発明の目的］ 本発明は、上記の点に鑑みて為されたものであり、実
装用凹部内にくぼみが生じるおそれのない電子部品実装
用プリント配線板を提供することを目的とするものであ
る。[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a printed wiring board for electronic component mounting in which a recess is not likely to occur in the mounting recess. is there.

［発明の開示］ しかして本発明は、配線基板１に電子部品２の実装箇
所を開口部３とした電気絶縁層４を介して、電子部品２
の実装箇所に開口部５を設けた接着樹脂層６によって同
様に電子部品２の実装箇所に開口部７を設けた配線基板
８を積層接着して形成され、各開口部3,5,7を上下に合
致して形成される実装用凹所９が設けられた電子部品実
装用プリント配線板Ａに関するものであり、電気絶縁層
４に設けた開口部３の大きさを接着樹脂層６の開口部５
よりも小さく設定して成ることを特徴とするものであっ
て、接着樹脂層６の開口部５の縁部が電気絶縁層４の開
口部３内にはみ出さないように両開口部3,5の大きさを
設定して、実装用凹部９内にくぼみが形成されないよう
にしたものである。DISCLOSURE OF THE INVENTION However, according to the present invention, the electronic component 2 is provided on the wiring board 1 via the electrical insulating layer 4 having the opening 3 at the mounting position of the electronic component 2.
The adhesive resin layer 6 having the openings 5 at the mounting positions is formed by laminating and bonding the wiring board 8 having the openings 7 at the mounting positions of the electronic component 2 in the same manner. The present invention relates to a printed wiring board A for mounting electronic components, which is provided with mounting recesses 9 which are formed so as to match with each other in the vertical direction. The size of the opening 3 provided in the electrical insulating layer 4 is set to the opening of the adhesive resin layer 6. Part 5
The opening portion 5 of the adhesive resin layer 6 is configured to be smaller than the opening portion 3 of the electrical insulating layer 4 so that the edge portion of the opening portion 5 does not protrude into the opening portion 3 of the electrical insulating layer 4. The size is set so that no recess is formed in the mounting recess 9.

以下本発明を実施例により詳述する。第１図は本考案
の一実施例を示すものであり、配線基板１は例えばガラ
ス基材エポキシ樹脂積層板など樹脂積層板で形成される
ものであって、その下面には銅箔などの金属箔14が積層
して張ってある。この配線基板１の上面には電気絶縁層
４が形成してある。この電気絶縁層４は、例えばエポキ
シ樹脂など電気絶縁性に優れた樹脂を塗布して硬化させ
たり、そのプリプレグを積層して硬化させたりして形成
することができるものであり、電子部品２を実装する箇
所においては配線基板１を露出させるように開口部３が
形成してある。また接着樹脂層６としては、例えばガラ
ス基材等にエポキシ樹脂等を含浸して乾燥させて調整し
たボンディング用プリプレグなどを用いることができ、
電子部品２を実装する箇所においては開口部５が形成し
てある。さらに配線基板８としては上記した配線基板１
と同じように形成したもの、例えばガラス基材エポキシ
樹脂積層板など樹脂積層板で形成されるものであって、
その上面には銅箔などの金属箔14が積層して張ってあ
り、また電子部品２を実装する箇所においては開口部７
が形成してある。ここで、各開口部3,5,7はそれぞれ四
角形など同じ平面形状で形成されているものであり、電
気絶縁層４の開口部３の大きさ（すなわちその内径）は
接着樹脂層６の開口部５の大きさ（すなわちその内径）
より小さくなるように形成してある。また接着樹脂層６
の開口部５の大きさと配線基板８の開口部７の大きさと
は等しくなるように形成してある。Hereinafter, the present invention will be described in detail with reference to Examples. FIG. 1 shows an embodiment of the present invention, in which a wiring board 1 is formed of a resin laminated board such as a glass base epoxy resin laminated board, and a metal such as copper foil is formed on the lower surface thereof. Foil 14 is laminated and stretched. An electrical insulating layer 4 is formed on the upper surface of the wiring board 1. The electric insulation layer 4 can be formed by applying a resin having an excellent electric insulation property such as an epoxy resin and curing it, or by laminating and curing the prepreg thereof. An opening 3 is formed so as to expose the wiring board 1 at a mounting position. As the adhesive resin layer 6, for example, a bonding prepreg prepared by impregnating a glass substrate or the like with an epoxy resin or the like and drying it can be used.
An opening 5 is formed at a place where the electronic component 2 is mounted. Further, as the wiring board 8, the wiring board 1 described above is used.
Formed in the same manner as, for example, a resin laminated plate such as a glass-based epoxy resin laminated plate,
A metal foil 14 such as a copper foil is laminated and stretched on the upper surface thereof, and the opening 7 is provided at a place where the electronic component 2 is mounted.
Is formed. Here, each of the openings 3, 5, 7 is formed in the same planar shape such as a quadrangle, and the size of the opening 3 of the electric insulating layer 4 (that is, its inner diameter) is the opening of the adhesive resin layer 6. Size of part 5 (ie its inner diameter)
It is formed to be smaller. Also, the adhesive resin layer 6
The size of the opening 5 is equal to the size of the opening 7 of the wiring board 8.

しかして第１図（ａ）に示すように配線基板１の上に
電気絶縁層４を介して接着樹脂層６を、その上に配線基
板８をそれぞれ重ねると共に各開口部3,5,7を上下に合
致させ、この状態で加熱加圧して積層成形をおこなうこ
とによって、第１図（ｂ）のように接着樹脂層６で配線
基板1,8を積層一体化することができ、また各開口部3,
5,7によって実装用凹部９を形成することができる。こ
こで、電気絶縁層４の表面を粗面化しておくことによっ
て、電気絶縁層４と接着樹脂層６との接着性を高めるこ
とができる。粗面化加工は、液体ホーニング、サンドブ
ラスト、サンドペーパーなどを用いた機械的粗面化ある
いは、重クロム酸類による処理など化学的粗化を単独で
あるいは併用することによっておこなうことができる。
そしてさらに各配線基板1,8の金属箔14をエッチング加
工などして回路13を形成することによって、プリント配
線板Ａとして仕上げることができ、実装用凹部９内にIC
などの電子部品２を搭載して回路13とワイヤー15などで
ボンディングすることによって、プリント配線板Ａに電
子部品２を実装することができる。このものにあって、
接着樹脂層６の開口部５は電気絶縁層４の開口部３より
も大きく形成されているために、接着樹脂層６の開口部
５の周縁部が電気絶縁層４の開口部３の内方へはみ出す
ことはなく、従って接着樹脂層６のはみ出しでくぼみが
実装用凹部９内に形成されるようなことはないものであ
る。Then, as shown in FIG. 1A, the adhesive resin layer 6 is overlaid on the wiring board 1 with the electrical insulating layer 4 interposed therebetween, and the wiring board 8 is overlaid thereon, and the openings 3, 5, 7 are formed. By aligning vertically and heating and pressing in this state to perform lamination molding, the wiring boards 1 and 8 can be laminated and integrated with the adhesive resin layer 6 as shown in FIG. Part 3,
5 and 7, the mounting recess 9 can be formed. Here, by roughening the surface of the electric insulating layer 4, the adhesiveness between the electric insulating layer 4 and the adhesive resin layer 6 can be improved. The roughening treatment can be performed by mechanical roughening using liquid honing, sandblasting, sandpaper, or the like, or by chemical roughening such as treatment with dichromic acid alone or in combination.
Further, by forming the circuit 13 by etching the metal foil 14 of each wiring board 1 and 8, the printed wiring board A can be finished, and the IC can be mounted in the mounting recess 9.
The electronic component 2 can be mounted on the printed wiring board A by mounting the electronic component 2 such as and bonding it to the circuit 13 with the wire 15. In this thing,
Since the opening 5 of the adhesive resin layer 6 is formed larger than the opening 3 of the electric insulating layer 4, the peripheral edge of the opening 5 of the adhesive resin layer 6 is located inside the opening 3 of the electric insulating layer 4. There is no protrusion, and therefore no protrusion is formed in the mounting recess 9 by the protrusion of the adhesive resin layer 6.

第２図及び第３図の実施例では、配線基板１として少
なくとも上面側に回路13を予め形成した回路板を用いる
ようにして、配線基板1,8間に内層の回路13が設けられ
るようにしてあり、実装用凹部９内に実装した電子部品
２を配線基板８の回路13の他に内層回路となる配線基板
１の回路13にもワイヤー15でボンディングするようして
ある。第２図において16はスルーホールである。第４図
の実施例は、配線基板１として実装用凹部９の底部の位
置において放熱用の金属板17を設けたものを用いるよう
にしたものであり、この配線基板１は金属板17をはめ込
んだ下層基板1aに接着樹脂層18で上層基板1bを積層した
構造に形成してある。第５図の実施例は配線基板１に貫
通孔19を形成するようにしたものを示す。第６図の実施
例は配線基板１として金属板20をコアとして積層したも
のを用いるようにしたものである。In the embodiment shown in FIGS. 2 and 3, a circuit board in which a circuit 13 is preformed on at least the upper surface side is used as the wiring board 1 so that the inner layer circuit 13 is provided between the wiring boards 1 and 8. The electronic component 2 mounted in the mounting recess 9 is bonded to the circuit 13 of the wiring board 8 as well as the circuit 13 of the wiring board 1 serving as an inner layer circuit by the wire 15. In FIG. 2, 16 is a through hole. In the embodiment shown in FIG. 4, the wiring board 1 is provided with a metal plate 17 for heat radiation at the bottom of the mounting recess 9, and the wiring board 1 is fitted with the metal plate 17. It is formed in a structure in which the upper layer substrate 1b is laminated with the adhesive resin layer 18 on the lower layer substrate 1a. The embodiment shown in FIG. 5 shows a wiring board 1 having through holes 19 formed therein. In the embodiment shown in FIG. 6, a wiring board 1 in which metal plates 20 are laminated as a core is used.

［発明の効果］ 上述のように本発明にあっては、電気絶縁層に設けた
開口部の大きさを接着樹脂層の開口部よりも小さく設定
したので、接着樹脂層の開口部の周縁部が電気絶縁層の
開口部の内方へはみ出すようなことがなく、接着樹脂層
のはみ出しでくぼみが実装用凹部内に形成されるような
ことはないものであって、くぼみに洗浄水が残留したり
樹脂封止の際にボイドが発生したりする問題をなくすこ
とができるものである。[Advantages of the Invention] As described above, in the present invention, the size of the opening provided in the electrical insulating layer is set to be smaller than the opening of the adhesive resin layer. Does not protrude into the opening of the electrical insulation layer, and the protrusion of the adhesive resin layer does not form a recess in the mounting recess, and cleaning water remains in the recess. It is possible to eliminate the problem that a void is generated during resin encapsulation.

【図面の簡単な説明】 第１図（ａ）（ｂ）は本発明の一実施例の断面図、第２
図は他の実施例の断面図、第３図は同上の一部の拡大断
面図、第４図、第５図、第６図はさらに他の実施例の断
面図、第７図は従来例の断面図、第８図は同上の一部の
拡大断面図である。 １は配線基板、２は電子部品、３は電気絶縁層の開口
部、４は電気絶縁層、５は接着樹脂層の開口部、６は接
着樹脂層、７は配線基板の開口部、８は配線基板、９は
実装用凹部である。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) and (b) are sectional views of an embodiment of the present invention, and FIG.
FIG. 4 is a sectional view of another embodiment, FIG. 3 is an enlarged sectional view of a part of the same, FIG. 4, FIG. 5, and FIG. 6 are sectional views of still another embodiment, and FIG. FIG. 8 is a partially enlarged sectional view of the above. 1 is a wiring board, 2 is an electronic component, 3 is an opening of an electric insulating layer, 4 is an opening of an electric insulating layer, 5 is an opening of an adhesive resin layer, 6 is an adhesive resin layer, 7 is an opening of a wiring board, and 8 is The wiring board 9 is a mounting recess.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭58−32440（ＪＰ，Ａ) 特開 昭59−125645（ＪＰ，Ａ) 特開 昭58−111350（ＪＰ，Ａ) 特開 昭63−233547（ＪＰ，Ａ) 実開 昭54−55267（ＪＰ，Ｕ) ─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-58-32440 (JP, A) JP-A-59-125645 (JP, A) JP-A-58-111350 (JP, A) JP-A-63- 233547 (JP, A) Actually opened 54-55267 (JP, U)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】配線基板に電子部品の実装箇所を開口部と
した電気絶縁層を介して、電子部品の実装箇所に開口部
を設けた接着樹脂層によって同様に電子部品の実装箇所
に開口部を設けた配線基板を積層接着して形成され、各
開口部を上下に合致して形成される実装用凹所が設けら
れた電子部品実装用プリント配線板において、電気絶縁
層に設けた開口部の大きさを接着樹脂層の開口部よりも
小さく設定して成ることを特徴とする電子部品実装用プ
リント配線板。1. A wiring board is also provided with an opening at an electronic component mounting location by an adhesive resin layer having an opening at the electronic component mounting location via an electrical insulating layer having an opening at the electronic component mounting location. In a printed wiring board for mounting electronic components, which is formed by laminating and adhering wiring boards provided with, and is provided with mounting recesses formed by vertically matching the openings, the openings provided in the electrically insulating layer Is set to be smaller than the opening of the adhesive resin layer, and a printed wiring board for mounting electronic parts is provided.
JP62271072A 1987-10-27 1987-10-27 Printed wiring board for mounting electronic components Expired - Lifetime JP2520429B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62271072A JP2520429B2 (en) 1987-10-27 1987-10-27 Printed wiring board for mounting electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62271072A JP2520429B2 (en) 1987-10-27 1987-10-27 Printed wiring board for mounting electronic components

Publications (2)

Publication Number Publication Date
JPH01112739A JPH01112739A (en) 1989-05-01
JP2520429B2 true JP2520429B2 (en) 1996-07-31

Family

ID=17494994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62271072A Expired - Lifetime JP2520429B2 (en) 1987-10-27 1987-10-27 Printed wiring board for mounting electronic components

Country Status (1)

Country Link
JP (1) JP2520429B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529747A (en) * 1991-07-19 1993-02-05 Akai Electric Co Ltd Printed wiring board
JP2005109268A (en) * 2003-09-30 2005-04-21 Mitsui Chemicals Inc Magnetic sheet metal

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5551344A (en) * 1978-10-11 1980-04-15 Mitsubishi Electric Corp Humidity detector
JPS60253291A (en) * 1984-05-29 1985-12-13 イビデン株式会社 Electronic part placing substrate and method of producing same
JPS61172393A (en) * 1985-01-26 1986-08-04 イビデン株式会社 Substrate for carrying electronic component and manufacture thereof
JPS62216250A (en) * 1985-11-06 1987-09-22 Shinko Electric Ind Co Ltd Manufacture of printed substrate type pga package

Also Published As

Publication number Publication date
JPH01112739A (en) 1989-05-01

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