JPS62114247A - Manufacture of chip carrier for electronic element - Google Patents
Manufacture of chip carrier for electronic elementInfo
- Publication number
- JPS62114247A JPS62114247A JP25531785A JP25531785A JPS62114247A JP S62114247 A JPS62114247 A JP S62114247A JP 25531785 A JP25531785 A JP 25531785A JP 25531785 A JP25531785 A JP 25531785A JP S62114247 A JPS62114247 A JP S62114247A
- Authority
- JP
- Japan
- Prior art keywords
- metal plate
- board
- chip
- electronic component
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は、ＩＣパッケージなどのような電子素子の実ｉ
ｋ基板として用いられる電子素子用チップキャリアに関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to the actual implementation of electronic devices such as IC packages.
The present invention relates to a chip carrier for electronic devices used as a k-substrate.
［背景技術１
１Ｃパツケージなどのような電子素子は、半導体チップ
などの電子部品チップをリードフレームに取り付けた状
態で樹脂封止や気密封止してパフケーソングすることに
よって行われる。そしてこのような電子素子にあって、
端子数の増加に伴って電子部品チップを支持するキャリ
アとしてのり一ド７レームの替わりにプリント配線板を
用いる試みがなされている。[Background Art 1] Electronic devices such as 1C packages are manufactured by attaching an electronic component chip such as a semiconductor chip to a lead frame, sealing it with a resin or hermetically, and then puffing it. And in such electronic devices,
With the increase in the number of terminals, attempts have been made to use printed wiring boards as carriers for supporting electronic component chips instead of glue boards.
ここにおいて、近時の電子部品チップの高密度化は発熱
を伴い、この熱を逃がす工夫が必要とされる。しかしキ
ャリアとして用いられるプリント配線板は〃ラス布エポ
キシ樹脂積層板など樹脂積層板で形成されており、この
ようなプリント配線板は熱の伝導性が悪（て放熱を良好
になすことができず、電子部品チップのキャリアとして
プリント配線板を用いることについての難、嶽になって
いるものである。Here, the recent increase in the density of electronic component chips is accompanied by heat generation, and it is necessary to devise ways to dissipate this heat. However, printed wiring boards used as carriers are made of resin laminates such as laminated cloth epoxy resin laminates, and such printed wiring boards have poor thermal conductivity (and are unable to dissipate heat well). This is one of the difficulties in using printed wiring boards as carriers for electronic component chips.
［発明の目的１
本発明は、上記の点に鑑みて為されたものであり、基板
の一部に金属板を用いることにより放熱性を良好なもの
とし、しかも金属板と電子部品チップとの接着信頼性、
電気的接続信頼性に優れた電子素子用チップキャリアを
提供することを目的とするものである。[Objective of the Invention 1] The present invention has been made in view of the above points, and improves heat dissipation by using a metal plate as a part of the board, and also improves heat dissipation between the metal plate and the electronic component chip. Adhesion reliability,
It is an object of the present invention to provide a chip carrier for electronic devices with excellent electrical connection reliability.
［発明の開示Ｊ
しかして本発明に係る電子素子用チップキャリアは、絶
縁基板１と絶縁基板１の一部に置鯵換えられる金属板２
とで基板３を形成し、基板３の表裏面に絶縁接着層１１
を介して金属Ｍ１０をＷｔＭして積層板２０を作製し、
次いで積層板２０の片側表面を穴加工して金属板２を露
出させると共にこの露出面にメッキを施してメッキ層１
８を形成し、次に積層板２０の他方の片側表面を穴加工
して金属板２を露出させた後上記メッキ層１８に通電す
ることにより、露出した金属板２の表面にメッキ層１７
を設け、その後このメッキ層１７の表面に電子部品チッ
プ６を実装することを特徴とするものであり、プリント
配線［５の基板３の一部を熱伝導率に優れる金属板２で
形成すると共にこの金属板２の露出面にメッキ層１７を
設けてメッキ層１７に電子部品チップ６を実装すること
により、電子部品チップ６の発熱が金属板２がら放熱で
きるようにすると共に金属板２の両面を露出させること
で内部の熱がこもらないようにし、また金属板２の露出
面にメッキ層１７を設けることにより金属板２の表面が
酸化するのを防止したものである。[Disclosure of the Invention J] However, the chip carrier for electronic devices according to the present invention includes an insulating substrate 1 and a metal plate 2 that is replaced with a part of the insulating substrate 1.
to form a substrate 3, and insulating adhesive layers 11 are formed on the front and back surfaces of the substrate 3.
A laminate plate 20 is produced by WtMing metal M10 through
Next, a hole is formed on one surface of the laminate plate 20 to expose the metal plate 2, and this exposed surface is plated to form a plating layer 1.
8 is formed, and then the other side surface of the laminated board 20 is drilled to expose the metal plate 2, and then the plated layer 18 is energized to form a plated layer 17 on the surface of the exposed metal plate 2.
is formed, and then an electronic component chip 6 is mounted on the surface of this plating layer 17, and a part of the substrate 3 of the printed wiring [5 is formed of a metal plate 2 having excellent thermal conductivity. By providing a plating layer 17 on the exposed surface of the metal plate 2 and mounting the electronic component chip 6 on the plating layer 17, the heat generated by the electronic component chip 6 can be radiated through the metal plate 2, and both sides of the metal plate 2 can be dissipated. By exposing the metal plate 2, internal heat is not trapped, and by providing a plating layer 17 on the exposed surface of the metal plate 2, the surface of the metal plate 2 is prevented from being oxidized.
以下本発明を実施例により詳述する。基板３は絶縁基板
１を主体として形成されるもので、この絶縁基板１は電
気絶縁性に優れた樹脂積層板によって形成することがで
き、ガラス布などの基材にエポキシ樹脂、フェノール樹
脂、不飽和ポリエステル樹脂などの熱硬化性樹脂の液や
樹脂フェスを含浸させて加熱乾燥することによって得ら
れるプリプレグを複数枚重ねて加熱加圧成形することに
よって作成することができる。そして、第２図（ａ）に
示すように、この絶縁基板１の一部を切欠して表裏に貫
通する闇ロアを設け、この閏ロア内に絶縁基板１と厚み
が等しくかつ開ロアとほぼ同じ大きさに形成された金属
板２をはめ込んで固着し、絶縁基板１と金属板２とで一
枚板の基板３を作成するようにするものである。この金
属板２は半導体チップなどの電子部品チップ６を実装す
るに十分な面積に形成されればよく、絶縁基板１に設け
るスルーホール９の位置に影響を及ぼさない大きさに設
定される。また金属板２としては、例えば銅板、銅合金
板、銅−インパー−ｔ！４（Ｃｕ−１ｎｖ−Ｃｕ）合金
板、鉄−ニッケル合金板、その他鋼板、鉄板、アルミニ
ウム板などを使用することができる。The present invention will be explained in detail below with reference to Examples. The substrate 3 is formed mainly from the insulating substrate 1. The insulating substrate 1 can be formed from a resin laminate with excellent electrical insulation, and is made of a base material such as glass cloth, epoxy resin, phenol resin, or non-woven fabric. It can be created by stacking a plurality of prepregs obtained by impregnating them with a liquid thermosetting resin such as saturated polyester resin or a resin face and drying them by heating and molding them under heat and pressure. Then, as shown in FIG. 2(a), a part of this insulating substrate 1 is cut out to provide a dark lower portion penetrating the front and back sides, and inside this lower portion, the thickness is equal to that of the insulating substrate 1 and is approximately the same as that of the open lower portion. A metal plate 2 formed to the same size is fitted and fixed, and a single board 3 is created from the insulating substrate 1 and the metal plate 2. This metal plate 2 only needs to be formed to have an area sufficient to mount an electronic component chip 6 such as a semiconductor chip, and is set to a size that does not affect the position of the through hole 9 provided in the insulating substrate 1. Further, as the metal plate 2, for example, a copper plate, a copper alloy plate, a copper-imper-t! 4 (Cu-1nv-Cu) alloy plate, iron-nickel alloy plate, other steel plates, iron plates, aluminum plates, etc. can be used.
そして、この絶縁基板１と金属板２とで形成される基板
３の両側表面に第２図（ｂ）のようにプリプレグ８を介
して銅箔などの金属箔１０を重ね、これを加熱加圧成形
することによって、第２図（Ｃ）のようにプリプレグ８
の含浸樹脂が硬化することによって形成される絶縁接着
層１１で金属ｇｉ。Then, as shown in FIG. 2(b), metal foils such as copper foils 10 such as copper foils are layered on both surfaces of the substrate 3 formed by the insulating substrate 1 and the metal plate 2, and heated and pressed. By molding, prepreg 8 is formed as shown in Fig. 2 (C).
The insulating adhesive layer 11 is formed by curing the impregnated resin of the metal GI.
を基板３の両面に接着させて積層板２０を作成するもの
である。次いで、第３図（１＋）に示すように金属板２
に対応ｒる位置において積層板２０の片側面を座ぐり加
工などして金属箔１０と絶縁接着層１１とを除去し、金
属板２の片側面を露出させると共に絶縁基板１の位置に
おいて積層板２０にスルーホール９を設ける０次に、第
３図（ｃ）のようにスルーホール９の内周面に銅、ニッ
ケル、金等でスルーホールメッキを施してスルーホール
メッキＮ１２を形成すると同時に金属板２の露出面も銅
、ニッケル、金等でメッキしてメッキ／１ｌ１８を形成
するものである。ここにおいて、メッキ層１８の端部に
メッキ用のリード線１９を設けておくものである１次に
、印廟配線などの常用手段で金属箔１０をエツチングし
て回路導体４を積層板２０の両側表面に形成さｉでスル
ーホールメッキ層１２にて両面の回路導体４，４を接続
させプリント配線板５を作成するものである。次いで、
金属板２に対応する位置において積層板２０の他方の片
側面にも同様に座ぐり加工して凹所１３を形成すると共
に金属板２の片側面を露出させ、そして上記リード線１
９に通電することにより金属板２の露出面に金、服、ロ
ジウムなどの防蝕性に優れた金属をメッキしてメッキ層
１７を形成するものである。The laminated board 20 is created by adhering these to both sides of the substrate 3. Next, as shown in FIG. 3 (1+), the metal plate 2
The metal foil 10 and the insulating adhesive layer 11 are removed by counterboring one side of the laminate 20 at a position corresponding to r, thereby exposing one side of the metal plate 2, and removing the laminate at the position of the insulating substrate 1. 20. Next, as shown in FIG. 3(c), through-hole plating is applied to the inner peripheral surface of through-hole 9 with copper, nickel, gold, etc. to form through-hole plating N12. The exposed surface of the plate 2 is also plated with copper, nickel, gold, etc. to form plating/1l18. Here, a lead wire 19 for plating is provided at the end of the plating layer 18.The first step is to etch the metal foil 10 by a common method such as inma wiring to connect the circuit conductor 4 to the laminate 20. A printed wiring board 5 is created by connecting circuit conductors 4, 4 on both sides with through-hole plating layers 12 formed on both surfaces. Then,
The other side of the laminated plate 20 is also counterbored at a position corresponding to the metal plate 2 to form a recess 13 and one side of the metal plate 2 is exposed, and the lead wire 1 is
By energizing the metal plate 9, the exposed surface of the metal plate 2 is plated with a metal having excellent corrosion resistance such as gold, iron, rhodium, etc., thereby forming a plating layer 17.
そして、このように金属板２の露出面に７フキＮ１７，
１８が設けられたプリント配線板５において、その片側
の凹所１３に半導体チップなどの電子部品チップ６を搭
載し、さらに第１図に示すようにワイヤーボンディング
１４などを電子部品チップ６と回路導体４との間に施す
ことによって、プリント配線板５への電子部品チップ６
の実装を行うものである。このようにしてプリント配線
板５をチップキャリアとして電子部品チップ６を保持さ
せ、そしてこれをパッケージングすることによって電子
素子として仕上げるものである。ここで、ＰＧＡ（ピン
グリッド アレー）型の電子素子として仕上げるよう
にしたり、ＬＣＣ（リードレスチップキャリア）型の電
子素子として仕上げるようにしたりすることができるが
、ＰＧＡ型に仕上げる場合にはプリント配線板５に設け
た各スルーホール９．９・・・に電子ピンを下方乃至上
方に突出させるように取り付けるようにする。Then, on the exposed surface of the metal plate 2, 7 balloons N17,
18, an electronic component chip 6 such as a semiconductor chip is mounted in the recess 13 on one side, and as shown in FIG. 4, the electronic component chip 6 is attached to the printed wiring board 5.
This is the implementation of In this way, the printed wiring board 5 is used as a chip carrier to hold the electronic component chip 6, and by packaging it, it is finished as an electronic device. Here, it is possible to finish it as a PGA (pin grid array) type electronic device or an LCC (leadless chip carrier) type electronic device, but when finishing it in a PGA type, it is possible to finish it as a printed wiring. Electronic pins are attached to each of the through holes 9, 9, . . . provided in the plate 5 so as to project downwardly or upwardly.
上記のようにプリント配線板５に電子部品チップ６を取
り付けて電子素子を形成するようにしたものにあって、
電子部品チップ６は金属板２の位置においてそのメッキ
層１７表面に実装されていて、電子部品チップ６の発熱
は金属板２に吸収されて熱伝導性に優れた金属板２から
良好に放熱されるものであり、しかもこのプリント配線
板５において電子部品チップ６を実装した面と反対側の
面で金属板２は片面が金属のメッキ層１８で露出された
状態にあるため、熱が金属板２内にこもるようなことな
く空気中に放散されることになって、電子部品チップ６
の発熱を抑制することができ、電子部品子ツブ６の高密
度化が可能になるものである。また、電子部品チップ６
が実装された金属板２表面にはメッキ層１７が形成され
ていて金属板２の酸化が防止されるために、この金属板
２が酸化し易い金属で形成されている場合でも電子部品
チップ６と金属板２どの接着信頼性が低下することがな
く、また電気的接続信頼性が向上できるものである。さ
らに、電子部品チップ６を実装した面と反対側の面にお
いて金属板２の露出表面から絶縁接着層１１の表面に至
るように銅やニッケル、金等のメッキで金属層１５が形
成されるようにすることにより、この金属層１５を回路
導体４の一部とすることができると共に金属板２の露出
表面は絶縁接着層１１にまで至る広い面積の金属層１５
に接続されることになって電子部品チップ６から金属板
２に伝えられた熱を広い面積の金属層１５から効率良く
放散させることができるものである。As described above, in the electronic component chip 6 attached to the printed wiring board 5 to form an electronic element,
The electronic component chip 6 is mounted on the surface of the plating layer 17 at the position of the metal plate 2, and the heat generated by the electronic component chip 6 is absorbed by the metal plate 2 and is effectively radiated from the metal plate 2, which has excellent thermal conductivity. Moreover, since one side of the metal plate 2 is exposed with the metal plating layer 18 on the opposite side of the printed wiring board 5 from the side on which the electronic component chip 6 is mounted, the heat is transferred to the metal plate. 2, the electronic component chip 6 is dissipated into the air without being trapped inside the
This makes it possible to suppress heat generation and increase the density of the electronic component parts 6. In addition, electronic component chip 6
A plating layer 17 is formed on the surface of the metal plate 2 on which the electronic component chip 6 is mounted to prevent the metal plate 2 from being oxidized. The reliability of adhesion between the metal plate 2 and the metal plate 2 does not deteriorate, and the reliability of electrical connection can be improved. Furthermore, a metal layer 15 is formed by plating copper, nickel, gold, etc. from the exposed surface of the metal plate 2 to the surface of the insulating adhesive layer 11 on the surface opposite to the surface on which the electronic component chip 6 is mounted. By doing so, this metal layer 15 can be made a part of the circuit conductor 4, and the exposed surface of the metal plate 2 has a wide area of the metal layer 15 extending up to the insulating adhesive layer 11.
The heat transferred from the electronic component chip 6 to the metal plate 2 can be efficiently dissipated from the metal layer 15 having a wide area.
［発明の効果］
上述のように本発明にあっては、絶縁基板と絶縁基板の
一部に置き換えられる金属板とで基板を形成し、基板の
表裏面に絶縁接着層を介して金属箔を１層して積層板を
作製し、次いで積層板の片側表面を穴加工して金属板を
露出させると共にこの露出面にメッキを施してメッキ層
を形成し、次に積層板の他方の片側表面を穴加工して金
属板を露出させた後メッキ層に通電することにより、露
出した金属板の表面にメッキ層を設け、その後このメッ
キ層の表面に電子部品チップを実装するようにしたので
、電子部品チップの発熱は金属板に吸収されて熱伝導性
に優れた金属板から良好に放熱されるものであり、しか
も金属板内に熱がこもるようなことなくメッキ層の露出
面から良好に放散されることになって、この結果電子部
品チップの発熱を抑制して電子部品チップの高密度化を
可能にすることができるものである。さらに、金属板の
露出面にメッキ層を形成するようにしたので、電子部品
チップと金属板との接着信頼性及び電気的接続信頼性を
向上させることがで柊るものであり、またこのようにメ
ッキ工法をとることにより導電ペースト等を印刷塗布す
る場合と異なり、金属露出面が漏れなくメッキで被覆で
きるものである。 ・[Effects of the Invention] As described above, in the present invention, a substrate is formed by an insulating substrate and a metal plate that replaces a part of the insulating substrate, and a metal foil is applied to the front and back surfaces of the substrate via an insulating adhesive layer. A laminate is produced by forming one layer, then holes are formed on one side of the laminate to expose the metal plate, and this exposed surface is plated to form a plated layer, and then the other side of the laminate is formed into a plated layer. After drilling holes to expose the metal plate, electricity is applied to the plated layer to form a plated layer on the surface of the exposed metal plate, and then electronic component chips are mounted on the surface of this plated layer. The heat generated by electronic component chips is absorbed by the metal plate and is well radiated from the metal plate, which has excellent thermal conductivity.Moreover, heat is not trapped inside the metal plate and is effectively dissipated from the exposed surface of the plating layer. As a result, the heat generation of the electronic component chips can be suppressed and the density of the electronic component chips can be increased. Furthermore, since a plating layer is formed on the exposed surface of the metal plate, it is possible to improve the adhesion reliability and electrical connection reliability between the electronic component chip and the metal plate. By using a plating method, the exposed metal surface can be covered with plating without leaking, unlike the case where conductive paste or the like is applied by printing.・
第１図は本発明の一実施例の断面図、＄２図（ａ）乃至
（ｅ）は同上の積層板の製造の各工程の断面図、第３図
（ａ）乃至（ｅ）は同上のプリント配線板の製造の各工
程の断面図である。
１は絶縁基板、２は金属板、３は基板、４は回路導体、
５はプリント配線板、６は電子部品チップ、１７はメッ
キ層である。Figure 1 is a cross-sectional view of one embodiment of the present invention, Figures 2 (a) to (e) are cross-sectional views of each step of manufacturing the same laminated board, and Figures 3 (a) to (e) are the same as above. FIG. 1 is an insulating substrate, 2 is a metal plate, 3 is a substrate, 4 is a circuit conductor,
5 is a printed wiring board, 6 is an electronic component chip, and 17 is a plating layer.
Claims (1)
板とで基板を形成し、基板の表裏面に絶縁接着層を介し
て金属箔を積層して積層板を作製し、次いで積層板の片
側表面を穴加工して金属板を露出させると共にこの露出
面にメッキを施してメッキ層を形成し、次に積層板の他
方の片側表面を穴加工して金属板を露出させた後上記メ
ッキ層に通電することにより、露出した金属板の表面に
メッキ層を設け、その後このメッキ層の表面に電子部品
チップを実装することを特徴とする電子素子用チップキ
ャリアの製造法。(1) A substrate is formed from an insulating substrate and a metal plate that replaces a part of the insulating substrate, and metal foil is laminated on the front and back surfaces of the substrate via an insulating adhesive layer to produce a laminate. A hole is formed on one side of the laminate to expose the metal plate, and this exposed surface is plated to form a plating layer. Next, a hole is formed on the other side of the laminate to expose the metal plate, and then the metal plate is plated. A method for manufacturing a chip carrier for an electronic device, characterized by providing a plating layer on the surface of an exposed metal plate by applying electricity to the layer, and then mounting an electronic component chip on the surface of the plating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25531785A JPS62114247A (en) | 1985-11-14 | 1985-11-14 | Manufacture of chip carrier for electronic element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25531785A JPS62114247A (en) | 1985-11-14 | 1985-11-14 | Manufacture of chip carrier for electronic element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62114247A true JPS62114247A (en) | 1987-05-26 |
Family
ID=17277100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25531785A Pending JPS62114247A (en) | 1985-11-14 | 1985-11-14 | Manufacture of chip carrier for electronic element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62114247A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4827783A (en) * | 1986-10-09 | 1989-05-09 | Kanzaki Kokyukoki Mfg. Co., Ltd. | Key-shift transmission |
| EP0766506A2 (en) * | 1995-09-29 | 1997-04-02 | Allen-Bradley Company, Inc. | A multilayer circuit board having a window exposing an enhanced conductive layer for use as an insulated mounting area |
| KR19990037873A (en) * | 1999-02-08 | 1999-05-25 | 구자홍 | Manufacturing method of PCB and PCB thereby |
| KR20000055589A (en) * | 1999-02-08 | 2000-09-05 | 구자홍 | Manufacturing method of PCB and PCB thereby |
| KR20120030762A (en) * | 2010-09-20 | 2012-03-29 | 엘지이노텍 주식회사 | A light emitting module, and a back light unit |
-
1985
- 1985-11-14 JP JP25531785A patent/JPS62114247A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4827783A (en) * | 1986-10-09 | 1989-05-09 | Kanzaki Kokyukoki Mfg. Co., Ltd. | Key-shift transmission |
| EP0766506A2 (en) * | 1995-09-29 | 1997-04-02 | Allen-Bradley Company, Inc. | A multilayer circuit board having a window exposing an enhanced conductive layer for use as an insulated mounting area |
| EP0766506A3 (en) * | 1995-09-29 | 1998-12-23 | Allen-Bradley Company, Inc. | A multilayer circuit board having a window exposing an enhanced conductive layer for use as an insulated mounting area |
| KR19990037873A (en) * | 1999-02-08 | 1999-05-25 | 구자홍 | Manufacturing method of PCB and PCB thereby |
| KR20000055589A (en) * | 1999-02-08 | 2000-09-05 | 구자홍 | Manufacturing method of PCB and PCB thereby |
| KR20120030762A (en) * | 2010-09-20 | 2012-03-29 | 엘지이노텍 주식회사 | A light emitting module, and a back light unit |
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