JP2510820B2 - Thin film semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device and a method for manufacturing the same, and more particularly to a thin film semiconductor device used for a liquid crystal panel or the like required for displaying a high-definition television image and a method for manufacturing the same. It is about.

[0002]

2. Description of the Related Art Conventionally, when displaying a high-definition television image on a liquid crystal panel, a method of switching a liquid crystal by a thin film transistor has been the mainstream. In this thin film transistor, the gate electrode was formed of only one polycrystalline silicon layer to which impurities were added. Even if this polycrystalline silicon film is deposited to a thickness of 3500Å, its sheet resistance is only reduced to about 20 Ω / □ (Technical report of IEICE, influence of Si electrode film on MOS characteristics, Maki Akizuki et al. , SDM 91-164, The Institute of Electrical Communication, 1991).

When this conventional gate electrode is applied to a liquid crystal display, there are the following problems.

1) Breakage of the gate line causes a line defect, which deteriorates the quality of the liquid crystal display and lowers the yield.
As a method of driving a liquid crystal display, it is usual to input gate signals to the gate lines from both left and right sides. For example, even if the gate line is broken at one point, gate signals are input to the gate line from both sides. However, when the resistance of the gate line is high, the delay of the gate signal cannot be ignored, and the delay of the response of the pixel near the disconnection becomes noticeable. Further, when there is a short circuit between the gate line and the source line, it is preferable to cut off the gate lines on both sides of this short circuit point to eliminate the influence of the short circuit. However, since the resistance of the gate line is high, a line defect will occur. If the resistance of the gate line can be reduced, the delay of the gate signals input from both sides will be small enough to cause no problem, and the display screen of the liquid crystal display will not be affected at all.

2) In the conventional liquid crystal display, it has been impossible to suppress the flickering of the screen and the display unevenness called flicker. That is, when a rectangular pulse is input to the gate line, if the time constant τ = R × C (R is the resistance of the gate line and C is the capacitance of the gate line) of the gate line is large, the rectangular pulse of the rectangular pulse appears in the center of the screen. The waveform becomes blunt, and the rising characteristics of the pixel transistor vary. As a result, flicker appears on the LCD screen. If the resistance of the gate line is large, the time constant τ becomes large, so that flicker could not be suppressed.

As described above, when applied to a liquid crystal display for high-definition television, the above-mentioned problem becomes particularly remarkable.

Further, when the conventional gate electrode is used in the liquid crystal display, there are the following problems.

1) When a polycrystalline silicon film to which an impurity is added as in the conventional case is used, even if the film thickness is 5000 Å, the sheet resistance is reduced by only about 15 Ω / □. To further reduce the sheet resistance, the film thickness should be 5
It is necessary to make it more than 000Å. However, in this case, the unevenness of the surface of the device becomes large, the step coverage of the film or wiring formed on the polycrystalline silicon film becomes a problem, and this becomes a major factor of reducing the yield.

2) When silicide is used to reduce the resistance of the gate electrode, there is a problem that the silicide receives a large stress. Here, comparing the values of the coefficient of linear expansion, the coefficient of linear expansion of the quartz substrate is 5.5 × 10 ^−7.
/ ° C., The coefficient of linear expansion of MoSi ₂ and WSi ₂ is 8.25 × 10 ⁻⁶ / ° C. And 6.
Since it is 25 × 10 ⁻⁶ / ° C., the coefficient of linear expansion of silicide is larger than the coefficient of linear expansion of a quartz substrate by one digit or more (Semiconductor Research, Vol. 24, 1986, Industrial Research Committee). Therefore, the silicide film formed on the quartz substrate receives stress, and cracks or the like are likely to occur in the silicide film, which causes a reduction in yield.

On the other hand, if the off-leakage current of the thin film transistor is large, the retention characteristic of the pixel is deteriorated. Therefore, it is necessary to reduce the off-leakage current in order to realize an excellent liquid crystal display. The leak current in the off region of a normal thin film transistor strongly depends on the electric field strength in the vicinity of the drain region, and when the gate voltage is increased to the off side, the off leak current remarkably increases. In order to reduce the off-leakage current, LDD (Light
It is known that it is effective to form a ly doped drain structure or an offset gate structure. However, in the conventional LDD structure or offset gate structure, complicated steps such as providing a gate electrode sidewall by utilizing anisotropic etching are required.

[0011]

In order to solve such a conventional problem, the sheet resistance value of the gate electrode is lowered to about 5 to 8 Ω / □ which is about one third of the conventional resistance value. Need to let. As one of the methods, there is reported a method of patterning a three-layer structure in which a polycrystalline silicon film is laminated on the lowermost layer, a silicide film is laminated on the intermediate layer and a polycrystalline silicon film is laminated on the uppermost layer by one photoetching ( Proceedings of the12th I
international Display Rese
archConfence, Japan Disp
lay, P2-6, Mo-Polycide Gate
High-Temperature Poly-Si
TFTs for HDTV LCDs, I.S. Yuda
saka et al, pp. 451-454,199
2).

FIG. 5 is a schematic sectional view of a thin film transistor in the case where a three-layer film of polycrystalline silicon / silicide / polycrystalline silicon forms a three-layer gate electrode by one-time photoetching.

In FIG. 5, a semiconductor thin film 52, a source region 53 and a drain region 54 are formed on an insulating substrate 51. Source region 53 and drain region 54
A voltage is applied to each of the source electrode 510 and the drain electrode 511. The gate insulating film 55 has
The lowermost polycrystalline silicon film 56, the silicide film 57, and the uppermost polycrystalline silicon film 58 are formed in this order to form a three-layer gate electrode as a whole. Reference numeral 59 is an interlayer insulating film.

In manufacturing the thin film transistor shown in FIG. 5, if the gate electrode is excessively etched to form an offset gate structure, the silicide film 57 has the highest etching rate. Therefore, the silicide film 57 of the intermediate layer is abnormally etched, resulting in an overhang shape. As a result, the coverage on the step of the interlayer insulating film 59 deteriorates, and the disconnection rate of the wiring (not shown) formed on the interlayer insulating film 59 increases.
Therefore, it has been difficult to reduce the resistance of the three-layer gate electrode and realize a semiconductor device having an offset gate structure.

Therefore, an object of the present invention is to solve the above-mentioned problems and to easily realize an offset gate structure by using a gate electrode having a small off leak current, a low gate line resistance and a low resistance. A thin film semiconductor device and a method for manufacturing the same are provided.

[0016]

In order to achieve such an object, the thin film semiconductor device of the present invention is a thin film semiconductor device having a source region, a drain region and a gate insulating film, and is formed on the gate insulating film. And a silicide film formed on the first polycrystalline silicon film, wherein the gate electrode is formed on the gate insulating film, and the first polycrystalline silicon film added with impurities is formed on the gate insulating film. And a second polycrystalline silicon film formed on the two-layer film and having impurities added thereto, and the width of the two-layer film is equal to that of the source region and the drain region. The channel length is shorter than the inter-channel length, and the two-layer film is covered with the second polycrystalline silicon film.

Further, in the method of manufacturing a thin film semiconductor device of the present invention, a step of forming a semiconductor layer on an insulating substrate, forming a gate insulating film on the semiconductor layer, and adding an impurity to the gate insulating film. Forming a first polycrystalline silicon film, forming a silicide film on the first polycrystalline silicon film, and patterning a two-layer film including the first polycrystalline silicon film and the silicide film. A step of making a pattern dimension of the two-layer film shorter than a channel length between a drain region and a source region, and a step of forming the patterned two-layer film with a second polycrystalline silicon film doped with impurities. And a step of using and covering.

[0018]

According to the present invention, since the width of the pattern of the two-layer film of polycrystalline silicon film / silicide film is made narrower than the channel length of the thin film transistor, the two-layer film is completely covered by the uppermost polycrystalline silicon film. No overhang or reverse taper shape. Therefore, the coverage on the step of the interlayer insulating film is improved, and the disconnection of the wiring formed on the interlayer insulating film can be prevented. As a result, the resistance of the gate line can be reduced and the off-leakage current can be reduced.

Further, according to the present invention, since the semiconductor device having the offset gate structure using the silicide film can be adopted, the sheet resistance value of the gate line is 25Ω / □ which is the resistance value of the conventional polycrystalline silicon. From 1/3 to 8Ω /
□ It can be reduced to a degree.

Furthermore, according to the present invention, among the three layers of gate electrodes of the offset gate structure, the lowermost layer is formed by using an impurity-doped polycrystalline silicon film, whereby the insulating substrate and the silicide film are formed. The stress of can be relaxed. Therefore, it is possible to eliminate defects such as cracks in the silicide film due to the difference in linear expansion coefficient. Further, since the adhesion of the silicide film to the insulating substrate is also improved, it is possible to prevent abnormal etching caused by insufficient adhesion during photoetching. On the other hand, the silicide film has a very large uneven surface, but by stacking a polycrystalline silicon film on the uppermost layer, this uneven surface can be smoothed and a flat surface can be obtained. As a result, the adhesion of the oxide film laminated on the gate electrode is improved, and abnormal etching when a contact hole is opened in this oxide film is eliminated.

Further, according to the present invention, since the gate signal is sent to the gate line from both the left and right sides, even if the gate line is broken, the resistance of the gate line is sufficiently small and the signal delay is reduced. Therefore, even if a short circuit occurs between the source line and the gate line, the short circuit defect can be eliminated by cutting the gate lines on both sides of this short circuit point.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. In this embodiment, the case of application to a thin film transistor (TFT) having a three-layer gate electrode will be described, but it goes without saying that the invention is not limited to this.

First, an amorphous semiconductor thin film is formed on an amorphous insulating substrate. As the amorphous insulating substrate, a quartz substrate,
Examples thereof include a glass substrate, a nitride film, SiO _{2 and the} like. The substrate is not only an amorphous insulating substrate,
Sapphire substrate, MgO / Al ₂ O ₃ , BP, CaF ₂
It is also possible to use a crystalline insulating substrate such as.

When a quartz substrate is used, the process temperature is 1
Up to about 200 ° C is allowed, but when a glass substrate is used, it is limited to a low temperature process of 600 ° C or lower. In the following examples, a case where a quartz substrate is used and a silicon thin film is grown as a semiconductor thin film by plasma CVD will be described. Of course, not only the plasma CVD method,
The present invention can also be realized by a film obtained by further solid-phase growing a polycrystalline silicon thin film formed by a low pressure CVD method, an EB vapor deposition method, a sputtering method or an MBE method, or a vapor phase growth film.

FIGS. 1A to 1E are process drawings showing a method of manufacturing the thin film transistor of this embodiment.

A quartz substrate 21 is used by using a plasma CVD apparatus.
A mixed gas of SiH ₄ and H ₂ was added on the top of the layer at 13.56 MH.
The amorphous silicon film 22 was deposited by decomposing it by a high frequency glow discharge of z (FIG. 1A). SiH of mixed gas
_The partial pressure of ₄ is 10 to 20%, and the internal pressure of the plasma CVD apparatus during thin film deposition is about 0.5 to 1.5 Torr. The temperature of the quartz substrate 21 is preferably 250 ° C. or lower, about 180 ° C. When the amount of bound hydrogen is calculated from infrared absorption measurement, it is about 8 at
It was mic%. The chamber before the deposition of the amorphous silicon film 22 was washed with Freon, and the amorphous silicon film 22 deposited subsequently contained 2 × 10 ¹⁸ cm ⁻³ of fluorine. Therefore, in this example, after cleaning with Freon, dummy deposition was performed and then actual deposition was performed. Alternatively, the cleaning with Freon is abolished, and the inside of the chamber is cleaned by another method such as bead treatment.

Then, the amorphous silicon film 22 is formed into 400
Heat treatment was performed at ℃ to 500 ℃ to release hydrogen. This process is intended to prevent the explosive desorption of hydrogen.

Next, the amorphous silicon film 22 is solid phase grown to form a solid phase grown silicon thin film 23 (FIG. 1).
(B)). As a solid phase growth method, furnace annealing with a quartz tube is convenient. As the annealing atmosphere, nitrogen gas, hydrogen gas, argon gas, helium gas, or the like is used. 1 x
Annealing may be performed in a high vacuum atmosphere of 10 ⁻⁶ to 1 × 10 ⁻¹⁰ Torr. Solid phase growth annealing temperature is 500 ° C
-700 degreeC. In such low temperature annealing, selectively, only the crystal grains having a crystal orientation with a small activation energy for crystal growth grow, and slowly grow large. Annealing time is 1 with annealing temperature of 600 ℃
By performing solid phase growth for 6 hours, a large grain silicon thin film of 2 μm or more was obtained.

Next, the solid-phase-grown silicon thin film 23 was patterned into islands by photolithography (FIG. 1).
(C)).

Next, a gate oxide film 24 was formed on the solid phase grown silicon thin film 23 (FIG. 1 (d)). As a method for forming the gate oxide film 24, LPCVD method, photoexcitation CVD
The low temperature growth method of 500 ° C. or lower, such as a plasma CVD method, a plasma CVD method, an ECR plasma CVD method, a high vacuum vapor deposition method, a plasma oxidation method or a high pressure oxidation method can be exemplified. The gate oxide film 24 formed by this low temperature growth method is
By heat treatment, an excellent film with higher density and less interface states was obtained. When the quartz substrate 21 is used as the amorphous insulating substrate, the thermal oxidation method can be used. This thermal oxidation method includes a dry oxidation method and a wet oxidation method. About 8
An oxide film was formed at temperatures above 00 ° C. Quartz substrate 2
To use 1, it is suitable to carry out dry oxidation at a temperature as high as possible, for example, 1000 ° C. or higher. A suitable film thickness of the gate oxide film 24 is about 500Å to 1500Å.

After the gate oxide film 24 is formed, boron may be channel-implanted and channel-doped if necessary. This is intended to prevent the threshold voltage of the N-channel thin film transistor from shifting to the negative side. When the thickness of the amorphous silicon film 22 deposited is about 500 to 1500Å, the dose amount of boron is 1 × 10 ^{12 to} 5 × 10 ¹² cm ^-2.
The degree is suitable. The thickness of the amorphous silicon film 22 is 50
If the thickness is less than 0Å, reduce the dose of boron,
As a guide, it should be 1 × 10 ¹² cm ^-2 or less. Further, when the thickness of the amorphous silicon film 22 is thicker than 1500 Å, the dose amount of boron is increased, and as a guide, it is 5 × 10 ^12.
cm ^-2 or more.

Instead of channeling ion implantation, boron may be added at the time of depositing the amorphous silicon film 22.
This can be obtained by flowing diborane gas (B ₂ H ₆ ) together with silane gas into the chamber during the deposition of the silicon film to cause a reaction.

Next, the process for producing a three-layer gate electrode will be described. Polycrystalline silicon film 25 with impurities added to the bottom layer
Was formed on the quartz substrate 21 and the gate oxide film 24 (FIG. 1E). First, a film forming method using the diffusion method will be described. A polycrystalline silicon film 25 is deposited by a method such as the LPCVD method, and then P is added to the polycrystalline silicon film 25 by a POCl ₃ diffusion method at 900 to 1000 ° C. At this time, since the polycrystalline silicon film 25 is covered with a thin oxide film, the oxide film is removed with an aqueous solution containing hydrofluoric acid. There is also a method of adding P by an ion implantation method. In addition, there is also a method of forming a lowermost layer film by depositing a doped polycrystalline silicon film. This is a method of forming a film by decomposing a mixed gas of SiO ₂ gas and PH ₃ gas. LPCVD
In the method, a polycrystalline silicon film to which impurities are added is formed by thermal decomposition at 500 to 700 ° C. and by glow discharge decomposition in the PECVD method. With the PECVD method, an amorphous silicon film can be formed at about 300 ° C. It is also an effective method to grow this doped amorphous silicon film into a high quality polycrystalline silicon film by the solid phase growth method as described above.

The polycrystalline silicon film 25 to which P of 1 × 10 ¹⁹ cm ^-3 or more is added by the method as described above is 500 to 20.
It was deposited to a thickness of about 00Å.

Next, the manufacturing process shown in FIGS. 2A to 2D will be described.

An intermediate silicide film 26 was formed on the polycrystalline silicon film 25 to form a two-layer film of polycrystalline silicon film / silicide film (FIG. 2 (a)). As a method for forming a silicide film, a co-evaporation method in which a refractory metal and silicon are simultaneously vapor-deposited from different crucibles is used.
position) method, or DC magnetron sputtering method using an alloy target, a method of forming a laminated film of refractory metal and silicon by alternately performing sputter deposition from two targets, and then forming a silicide by heat treatment (co-deposition), Alternatively, a CVD method or the like using a gas of a halide of a refractory metal such as MoF ₆ or WF ₆ and a gas of a silane gas (SiH ₄ ) can be exemplified. Among the methods for forming the silicide film 26, the sputtering method using a mixed crystal target of a refractory metal and silicon is often used because of the excellent controllability of the composition ratio of the silicide film 26.

As the silicide, CoSi ₂ , NiS
Examples thereof include i, TiSi ₂ , MoSi _{2 and} WSi ₂ .

For example, as the silicide film 26, MoSi
_{When two} films are used, sputtering is performed using a mixed crystal target having a composition ratio richer in silicon than stoichiometry (stoichiometry) such as MoSi _3.5 .
This aims at bringing the formed film close to a stoichiometric composition and relaxing the stress.
Regarding the film thickness, as described above, the silicide film 2
6 and the quartz substrate 21 are different from each other in linear expansion coefficient by one digit or more, the limit is about 2500 Å even if the thickness of the silicide film 26 is large. If the thickness is larger than this, cracks may occur in the silicide film 26 itself.

Next, a two-layer film (polycide film) of polycrystalline silicon film / silicide film is formed by photolithography.
Is patterned (FIG. 2B). At this time, the width of the polycide film pattern is at least 2 μm or more narrower than the channel length of the thin film transistor. The etching rate of the silicide film 26 in the upper layer depends on the polycrystalline silicon film 25.
Since it is faster than the etching rate of, the overhang and the reverse taper shape are not formed.

Then, a polycrystalline silicon film 27 having the uppermost layer doped with impurities was formed (FIG. 2C). Since this film forming method has been described so far, detailed description thereof is omitted here. However, in order to prevent the surface of the silicide film 26 from being oxidized, 400
A low temperature film forming method of ℃ or less is desirable. Even with the LPCVD method,
There is no problem if the substrate is placed in a chamber at 400 ° C. or lower and then the chamber is heated to a predetermined temperature to form a film. Considering the total thickness of the three layers, the uppermost polycrystalline silicon film 27 preferably has a film thickness of about 1000 Å.

Next, the resist mask 2 is formed so as to completely cover the pattern of the polycrystalline silicon film / silicide film two-layer film.
8 was formed, and the uppermost impurity-added polycrystalline silicon film 27 was etched ((d) of FIG. 2). The distance L ₁ between the pattern end of the two-layer film of the polycrystalline silicon film / silicide film and the pattern end of the resist mask 28 was at least 1 μm or more. Etching was completed when the pattern of the uppermost impurity-doped polycrystalline silicon film 27 and the pattern of the resist mask 28 became the same. Etching was performed using a dry etching device. Usually, the polycrystalline silicon film 25 or the silicide film 2 is formed by plasma-discharging Freon gas (CF ₄ ).
6 or polycide film is plasma etched.
At this time, if oxygen gas (O ₂ ) is mixed, the gate electrode is processed while the resist serving as the mask is also removed by etching. Therefore, a tapered gate electrode is formed. If the partial pressure of oxygen gas is increased,
It became a more gentle taper shape. Thus, the taper shape of the gate electrode could be controlled by the partial pressure ratio of oxygen gas.

Next, the manufacturing process shown in FIGS. 3A to 3D will be described. By an ion implantation method, an impurity ion beam 212 is implanted into the first semiconductor layer with a high concentration of acceptor-type or donor-type impurities to form the source region 210 and the drain region 211 in a self-aligned manner (see FIG. a)).

Here, since the boundaries between the source region 210 and the drain region 211 and the channel region do not overlap with the pattern of the uppermost impurity-doped polycrystalline silicon film 27, an offset gate structure is formed. be able to.

Boron (B) or the like is used as the acceptor type impurity. As the donor type impurity, phosphorus (P), arsenic (As), or the like is used. As a method for adding impurities, there is a method such as a laser doping method or a plasma doping method other than the ion implantation method.
When the quartz substrate 21 as the insulating amorphous material is used, the thermal diffusion method can be used. The dose of impurities is
It was set to about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻² . Converted to the impurity concentration, the impurity concentration in the source region 210 and the drain region 211 is approximately 1 × 10 ¹⁹ cm ⁻³ to 1 × 1.
It was about 0 ²² cm ^-3 .

Subsequently, with the resist mask 28 as a mask, the uppermost impurity-added polycrystalline silicon film 27 is used.
Was further excessively etched to narrow this pattern (FIG. 3B). The distance L ₂ between the edge of the resist mask 28 and the pattern edge of the uppermost impurity-doped polycrystalline silicon film 27 was at least 1 μm or more. This L
₂ is called the offset length. L ₂ is 1 μm to 1.5 μm
Is suitable.

After removing the resist mask 28, an interlayer insulating film 214 was laminated (FIG. 3C). Interlayer insulating film 21
As the material of 4, an oxide film or a nitride film is used. The insulating layer may have any thickness as long as it has a good insulating property, but it is usually several thousand Å to several μm. Here, as a method for forming the nitride film, the LPCVD method or the plasma CVD method is simple. Ammonia gas (NH
₃ ) and a mixed gas of silane gas and nitrogen gas, or a mixed gas of silane gas and nitrogen gas. Subsequently, activation annealing is performed for the purpose of densification of the interlayer insulating film 214, activation of the source region 210 and drain region 211, and recovery of crystallinity. As the conditions of activation annealing, the temperature is lowered to about 800 to 1000 ° C. in an N ₂ gas atmosphere, and the annealing time is set to about 20 minutes to 1 hour. The impurities are considerably activated by annealing for about 20 minutes at 900 to 1000 ° C. 800-90
Anneal at 20 ° C. for 20 minutes to 1 hour. On the other hand, after the crystallinity is sufficiently recovered by annealing at 500 to 800 ° C. for about 1 to 20 hours, 900 to 10
A two-step activation annealing method of activating at a high temperature of 00 ° C is also effective. In addition, RTA (Rapid Thermal) using an infrared lamp or a halogen lamp
The Annealing method is also effective. Furthermore, it is also effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, a dangling bond existing at a crystal grain boundary or a gate is formed. Defects existing at the interface of the oxide film and defects existing at the junction between the source region 210, the drain region 211 and the channel are inactivated. Such a hydrogenation process is performed by the interlayer insulating film 21.
It may be performed before stacking 4. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode described later.

Next, a contact hole is formed in the interlayer insulating film 214 by photoetching, and the source electrode 215 is formed.
And the drain electrode 216 was formed (FIG.3 (d)).
The source electrode 215 and the drain electrode 216 are formed of a metal material such as aluminum or chromium. Thus, the thin film transistor shown in FIG. 4 was formed.

Although the thin film transistor has been described above as an example, the present invention can be applied to an element using a thin film such as a bipolar transistor or a heterojunction bipolar transistor. Further, the present invention can be applied to an element using SOI technology such as a three-dimensional device.

[0050]

As described above, according to the present invention,
Since the resistance of the gate line is reduced, the time constant τ of the gate line is reduced. Therefore, the rising characteristics of the pixel transistor at the center and the edge of the image become uniform. As a result, flicker or display unevenness can be reduced. Moreover, since the line capacitance of the gate line does not have to be reduced, the pixel retention characteristics do not deteriorate. As described above, according to the present invention, it is possible to realize a liquid crystal display with extremely little flicker or display unevenness without deteriorating the pixel holding characteristic. Furthermore, since the resistance of the gate line is reduced, it is possible to eliminate the additional pixel holding capacitance line. Therefore, the aperture ratio is improved, and as a result, a very bright liquid crystal display can be realized.

Furthermore, according to the present invention, since the resistance of the gate line can be reduced and the off-leakage current can be reduced, a very large effect can be expected for improving the characteristics of the thin film transistor. Regarding a TFT for a high-definition television, a light valve or the like is required in order to configure it as a projection type display, so that a large TFT panel of about 4 inches must be prepared. When creating a panel with such long gate lines,
The effect of the present invention is further enhanced.

Since it has an offset gate structure,
The pixel retention characteristics are improved. Furthermore, a great effect is expected in reducing the current consumption.

Furthermore, by using the solid phase growth method, it becomes possible to form a silicon thin film having excellent crystallinity on an amorphous insulating substrate, which greatly contributes to the development of SOI technology. . Lowering the resistance of the gate line has a great effect in maximizing the characteristics of the thin film transistor improved by a method such as solid phase growth and realizing a very excellent liquid crystal display.

When the present invention is applied to a contact-type image sensor in which a photoelectric conversion element and its scanning circuit are integrated in the same chip, it is extremely useful in increasing the reading speed, increasing the resolution, and obtaining gradation. Produce a great effect on. If higher resolution is achieved, it will be easier to apply to a contact image sensor for color reading. Of course, reduction of power supply voltage,
The effect is great also for reduction of current consumption and improvement of reliability. Further, since it can be manufactured by a low temperature process, the contact type image sensor chip can be lengthened, and a single-chip chip can realize a reading device for a large-sized facsimile of A4 size or A3 size. Therefore, it is possible to avoid the technique of unreliableness such as double joining of the sensor chips, and to improve the mounting yield.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a thin film transistor which is an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of a thin film transistor which is an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a manufacturing process of a thin film transistor which is an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a thin film transistor manufactured by the manufacturing process of FIGS.

FIG. 5 is a schematic cross-sectional view showing a conventional thin film transistor.

[Explanation of Codes] 21 Quartz Substrate 23 Solid Phase Growth Silicon Thin Film 24 Gate Oxide Film 25 Polycrystalline Silicon Film 26 Silicide Film 27 Polycrystalline Silicon Film 28 Resist Mask 210 Source Region 211 Drain Region

Claims (2)

(57) [Claims] 1. A thin film semiconductor device having a source region, a drain region and a gate insulating film, comprising: a gate electrode formed on the gate insulating film, the gate electrode being formed on the gate insulating film, A two-layer film of a first polycrystalline silicon film to which impurities are added and a silicide film formed on the first polycrystalline silicon film;
A second polycrystalline silicon film formed on the two-layer film and having impurities added thereto, and the width of the two-layer film is shorter than a channel length between the source region and the drain region. , The two-layer film is the second
A thin film semiconductor device characterized by being covered with the polycrystalline silicon film of. 2. A step of forming a semiconductor layer on an insulating substrate and forming a gate insulating film on the semiconductor layer; and forming a first polycrystalline silicon film to which impurities are added on the gate insulating film. A step of forming a silicide film on the first polycrystalline silicon film, patterning a two-layer film of the first polycrystalline silicon film and the silicide film, and setting a pattern dimension of the two-layer film to a drain. A step of shortening the channel length between the region and the source region, and a step of covering the patterned two-layer film with a second polycrystalline silicon film to which an impurity is added. Method for manufacturing thin film semiconductor device.