JP2012151491A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SOI-MISFET which inhibits electrical short circuit due to residual of polycrystalline silicon, increase of parasitic capacitance in a gate electrode and a reverse narrow channel effect.SOLUTION: A gate insulation film 14, a first polycrystalline silicon film 15 and a stopper nitride film 16 are sequentially deposited on an SOI substrate having a silicon film 13. Etching is performed so as to form reverse tapered surfaces (taper angle θ is obtuse angle) on side faces of the silicon film 13 and the polycrystalline silicon film 15 to form an element isolation trench. After an STI implanted insulation film 17 is deposited and planarized by CMP, a flat surface is obtained by etching of the stopper nitride film 16 and the insulation film 17 by constant velocity RIE, and a second polycrystalline silicon film 18 is deposited on the flat surface (e). Laminated gate electrodes (15, 18) are formed by etching of a laminated polycrystalline silicon film (f). Subsequently, a source/drain region 21, a silicide film 22, an interlayer insulation film 23, metal wiring 24 and the like are formed (g).

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a semiconductor device using an SOI (Silicon On Insulator) substrate having a single crystal semiconductor layer formed on a semiconductor substrate via a buried oxide film. Is.

The demand for ultra-miniaturization and high density of LSI is becoming more and more intense, and the sub-100 nm era is approaching. On the other hand, demands for low power consumption and ultra-high speed are increasing, and it is becoming difficult to satisfy these demands using a conventional bulk substrate.
The MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on the SOI substrate has a smaller junction capacitance in the source / drain region and a smaller substrate bias effect than the MISFET formed on the conventional bulk substrate. Due to its excellent subthreshold characteristics, it is expected as a sub-100 nm generation ULSI element.
Thus, the SOI-MISFET includes a fully-depleted type (Fully-Depleted SOI-MISFET, hereinafter referred to as FD-type SOI-MISFET) and a partially-depleted type (Partial-Depleted SOI-MISFET, hereinafter referred to as PD-SOI-MISFET). ) There are two types of operation modes. The FD type SOI-MISFET is a MISFET whose SOI layer thickness is thinner than the maximum depletion width (the body region is always depleted), and PD-SOI is the SOI layer thickness less than the maximum depletion width. It is a thick MISFET. In particular, FD-SOI can be expected as a ULSI element excellent in low voltage and ultrahigh-speed operation because a steep subthreshold characteristic is obtained. In the sub 100 nm generation FD type SOI-MISFET, the thickness of the silicon layer of the SOI substrate is reduced to about 10 nm or less.

A method for manufacturing a conventional SOI-MISFET will be described below.
First, in the case where trench isolation (hereinafter referred to as STI) used for a MISFET on a general bulk substrate is applied to an SOI structure, cross-sectional views in order of steps of FIGS. (Hereinafter referred to as a first conventional example). After preparing an SOI substrate comprising a silicon substrate 51, a buried oxide film 52 and a silicon film 53 (FIG. 15A), a pad oxide film 54 having a thickness of about 5 nm and a stopper nitride film 55 having a thickness of about 120 nm are sequentially deposited. Then, the stopper nitride film 55, the pad oxide film 54, and the silicon film 53 are processed into an island shape by photolithography and reactive ion etching (hereinafter referred to as RIE) to form an element isolation trench 56 [FIG. 15 (b)]. Next, the STI buried insulating film 57 is deposited, and the STI buried insulating film 57 is flattened by a chemical mechanical polishing (CMP) method (FIG. 15C). Next, the stopper nitride film 55 is removed by hot phosphoric acid and the pad oxide film 54 is removed by wet etching using hydrofluoric acid (hereinafter referred to as HF) to expose the silicon film 53 (FIG. 15D). At this time, the buried oxide film 52 buried under the silicon film 53 is over-etched 59. Thereafter, a gate insulating film 60 is formed, a polycrystalline silicon film 61 is deposited and patterned to form a gate electrode [FIG. 16 (e)]. Thereafter, sidewall insulating film 63, source / drain regions 64, silicide film 65 are formed, interlayer insulating film 66 is deposited, contact holes are opened, and metal wiring 67 is formed to form a MISFET [FIG. 16 (f)]. ]. A plan view of the formed MISFET is shown in FIG. FIG. 15A to FIG. 16F are cross-sectional views in order of steps in the cross section taken along the line AA ′ of FIG.

  FIG. 17 is a cross-sectional view in order of steps showing a method for forming an element isolation region disclosed in Patent Document 1 (hereinafter referred to as a second conventional example). After sequentially depositing the gate insulating film 68 and the first polycrystalline silicon film 70 on the surface of the silicon film of the SOI substrate in which the buried oxide film 52 and the silicon film 53 are stacked on the silicon substrate 51, the first polycrystalline film is formed. The silicon film 70, the gate insulating film 68, and the silicon film 53 are patterned using the same mask [FIG. 17 (a)]. Subsequently, an STI buried insulating film 69 is deposited on the entire surface, and is planarized by CMP (FIG. 17B).

Next, a second polycrystalline silicon film 71 is deposited on the entire surface, and a mask pattern 58 made of a photoresist is provided (FIG. 17C). Using this mask pattern 58, the second polycrystalline silicon film 71, The first polycrystalline silicon film 70 and the gate insulating film 68 are patterned by the RIE method. Here, the first polycrystalline silicon film 70 becomes a gate electrode 70a, and the second polycrystalline silicon film 71 becomes a gate electrode line 71a connecting gate electrodes of adjacent transistors. Thereafter, source / drain regions 64 are formed by ion implantation to obtain the structure of FIG.
In the SOI-MISFET, it is known that when the end portion 72 of the element region is exposed, a leakage current is generated. However, according to this element isolation method, the side surface of the silicon film 53 on which the element is formed becomes STI. Since it is covered with the buried insulating film 69, the end 72 of the element region is not exposed, and the leakage current is suppressed (in fact, the leakage current is generated perpendicular to FIG. This is an end portion that is also present in the cross section in the depth direction in the drawing, but is shown in FIG. 17D for the convenience of illustration.

JP 2001-24202 A

A typical silicon film thickness in the era of high density is about 10 nm. However, when STI is applied to an SOI-MISFET having such a thin silicon film, the first conventional example has the following problems. Occurs. After the shape of FIG. 15C is formed, the stopper nitride film 55 is removed by hot phosphoric acid, and the pad oxide film 54 is removed by wet etching using HF. At this time, the STI buried insulating film 57 is simultaneously etched by HF. Therefore, as shown in FIG. 15D, the buried oxide film 52 under the silicon film 53 is over-etched (symbol 59 in FIG. 15). In particular, if the silicon film 53 is thin (for example, typically 10 nm), when the pad oxide film 54 is etched, the STI buried insulating film 57 on the side surface of the silicon film 53 is easily lost by etching. Therefore, overetching 59 is very likely to occur at the lower corner of the end of the silicon film 53.
Further, after forming the gate insulating film 60 in a shape in which the buried oxide film 52 at the lower corner at the end of the silicon film 53 is over-etched, a polycrystalline silicon film 61 is deposited, and then the polycrystalline silicon film 61 is formed. When patterning is performed, residual polycrystalline silicon 62 is left in the over-etched portion 59 [FIG. 16 (e)].

As shown in the plan view of FIG. 16G, the remaining polycrystalline silicon 62 is formed so as to surround the active region (island region). As a result, the residual polycrystalline silicon 62 and the polycrystalline silicon film 61 are connected to each other in the BB ′ cross section. At this time, if two or more gate electrodes are arranged in parallel, the gate electrodes are short-circuited by the remaining polycrystalline silicon film 62. In addition, since the electrostatic capacitance formed between the remaining polycrystalline silicon 62 and the source / drain region 64 becomes a parasitic capacitance connected in parallel to the gate capacitance, the load on the circuit is increased and the operation speed is increased. Reduce. Further, if the gate insulating film 60 is damaged by ion implantation for forming the source / drain regions 64 and the insulating properties deteriorate, the gate insulating film 60 is interposed between the gate electrode and the source / drain regions 64 through the residual polycrystalline silicon 62. An electrical short circuit may occur.
Further, when the end of the element is exposed due to the formation of the overetch 59, a leak current is likely to occur at the end of the element region (reference numeral 72 in FIG. 17).
Further, in the first conventional example, since the end of the element region is exposed, the gate electrode is formed so as to cover the side surface of the element region, so that the electric field applied from the gate electrode to the silicon film is enhanced. Thus, the reverse narrow channel effect in which the threshold value is lowered by miniaturization becomes remarkable.

In order to prevent such over-etching, it is conceivable to strictly control wet etching of the pad oxide film 54 by HF (although it is actually very difficult). However, at this time, a step is generated as shown in FIG. This is because the thickness of the pad oxide film 54 is very thin compared to the thickness of the STI buried insulating film 57. If wet etching with HF is continued to eliminate this step, overetching occurs as described above.
Here, a problem in the case where a step is generated will be described with reference to FIG. If there is such a step, a polycrystalline silicon film 61 is deposited after forming the gate insulating film 60 (FIG. 19A), and this polycrystalline silicon 61 is processed by RIE to form a gate electrode. Residual polycrystalline silicon 62 that is not etched is generated in the step portion [FIG. 19B]. The residual polycrystalline silicon 62 causes a short circuit between the polycrystalline silicon films or between the gate electrode and the source / drain regions. Moreover, when such a level | step difference arises, it will become a cause of deteriorating the shape of the resist pattern for gate electrode processing in a lithography process.

  Further, in the second conventional example, when polishing by CMP method is performed for processing as shown in FIG. 17B, the polishing rate for polycrystalline silicon is generally faster than the polishing rate for oxide film. The first polycrystalline silicon film 70 is polished deeper than the STI buried insulating film 69, resulting in a step (FIG. 20A). Furthermore, since it is impossible to cause the first polycrystalline silicon film 70 to act as a polishing stopper in the CMP method, all the polycrystalline silicon is lost when the polycrystalline silicon is thinned. [FIG. 20B] There is even a possibility.

  An object of the present invention is to solve the above-mentioned problems of the prior art, and the object is firstly to prevent the end of the element region from being exposed, and secondly, residual polycrystalline. It is to prevent generation of silicon, and thirdly, to prevent damage or disappearance of the polycrystalline silicon film as the gate electrode material.

In order to achieve the above object, according to the present invention, a semiconductor layer having a channel region and a source / drain region provided in an island shape on an insulator film, and the semiconductor layer that is a channel region A gate electrode provided on the top via a gate insulating film; and an element isolation insulating film formed on the insulator film so as to surround the semiconductor layer and having an upper surface protruding upward from the upper surface of the semiconductor layer; The side surface of the gate electrode in contact with the side surface of the element isolation insulating film is formed in a reverse taper shape.
Preferably, the side surface of the semiconductor layer is formed to have a reverse taper shape. More preferably, the height of the upper surface of the element isolation insulating film is substantially equal to the height of the upper surface of the gate electrode.

In order to achieve the above object, according to the present invention,
(1) a step of sequentially forming a gate insulating film, a first conductor layer, and a first insulating film on a semiconductor layer on the insulator film;
(2) forming an element isolation trench by etching and processing the semiconductor layer, the gate insulating film, the first conductor layer, and the first insulating film into an island shape;
(3) depositing a second insulating film on the entire surface;
(4) performing a planarization process to substantially match the height of the upper surface of the second insulating film with the height of the upper surface of the first insulating film;
(5) The first insulating film is removed and the second insulating film is removed by the thickness of the first insulating film to expose the height of the upper surface of the second insulating film. A step of substantially matching the height of the upper surface of the semiconductor layer;
(6) depositing a second conductor layer on the entire surface;
(7) patterning the second and first conductor layers to form a gate electrode and a gate lead-out wiring led out from the gate electrode;
A method for manufacturing a semiconductor device is provided.

In order to achieve the above object, according to the present invention,
(1 ′) a step of sequentially forming a gate insulating film, a first conductor layer, and a first insulating film on the semiconductor layer on the insulator film;
(2 ′) forming an element isolation trench by etching and processing the semiconductor layer, the gate insulating film, the first conductor layer, and the first insulating film into an island shape;
(3 ′) depositing a second insulating film on the entire surface;
(4 ′) performing a planarization process so that the height of the upper surface of the second insulating film substantially matches the height of the upper surface of the first insulating film;
(5 ′) removing the remaining first insulating film;
(6 ') A step of depositing a third conductor layer and subjecting it to a flattening process to form a third conductor layer having an upper surface whose height is substantially equal to the height of the upper surface of the second insulating film. When,
(7 ′) depositing a second conductor layer on the entire surface;
(8 ′) patterning the second, third and first conductor layers to form a gate electrode and a gate lead-out wiring led out from the gate electrode;
A method for manufacturing a semiconductor device is provided.
Preferably, the etching in the step (2) or the step (2 ′) is performed in the first conductor layer and the semiconductor layer, or the first insulating film, the first conductor. The side surfaces of the layer and the semiconductor layer are formed to have an inversely tapered shape.

In the semiconductor device of the present invention, the polycrystalline silicon film for the gate electrode in contact with the element isolation trench is formed so as to have a reverse taper shape, so that the generation of residual polycrystalline silicon can be prevented in advance when the gate electrode is formed. It is possible to suppress the generation of leakage current between the gate electrodes and the increase in parasitic capacitance in the gate electrode. In addition, since the element isolation insulating film is formed so as to cover the side surface of the silicon film and protrude from the silicon film, it is possible to suppress an increase in leakage current and to suppress the expression of the reverse narrow channel effect. Further, by forming the silicon film in a reverse taper shape, the concentration of the electric field can be reduced and the leakage current can be reduced.
Further, in the manufacturing method according to the present invention, since the treatment with HF is not performed in any step, it is possible to eliminate the remaining polycrystalline silicon due to the overetching of the buried oxide film, and the gate electrode, the source / drain region, It is possible to prevent an electrical short circuit, a leakage current between the gate electrodes, an increase in parasitic capacitance at the gate electrode, and the like. Further, since the photolithography process for forming the gate electrode is performed on a flat surface, generation of residual polycrystalline silicon can be prevented and high-precision patterning can be performed.

Sectional drawing in order of a process which shows the manufacturing method of the 1st Embodiment of this invention (the 1). Sectional drawing in order of the process which shows the manufacturing method of the 1st Embodiment of this invention (the 2). The figure which shows the production | generation conditions of the forward taper and reverse taper of an etching. Sectional drawing which shows the production | generation principle of a forward taper and a reverse taper. The comparison figure of the etching rate of the silicon oxide film and silicon nitride film in RIE. Sectional drawing in process order which shows the manufacturing method of the 2nd Embodiment of this invention (the 1). Sectional drawing in process order which shows the manufacturing method of the 2nd Embodiment of this invention (the 2). The figure which compared the polishing speed of a polycrystalline silicon and a silicon oxide film. Sectional drawing in process order which shows the manufacturing method of the 3rd Embodiment of this invention (the 1). Sectional drawing in process order which shows the manufacturing method of the 3rd Embodiment of this invention (the 2). Sectional drawing in process order which shows the manufacturing method of the 4th Embodiment of this invention (the 1). Sectional drawing in process order which shows the manufacturing method of the 4th Embodiment of this invention (the 2). Sectional drawing in order of a process which shows the manufacturing method of the comparative example of this invention (the 1). Sectional drawing in order of the process which shows the manufacturing method of the comparative example of this invention (the 2). Sectional drawing in order of a process which shows the manufacturing method of the 1st prior art example (the 1). Sectional drawing in order of the process which shows the manufacturing method of the 1st prior art example (the 2). Sectional drawing in order of a process which shows the manufacturing method of the 2nd prior art example. Sectional drawing for demonstrating the trouble of a prior art example. Sectional drawing in order of a process for demonstrating the problem of a 1st prior art example. Sectional drawing in order of a process for demonstrating the problem of the 2nd prior art example.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1A to FIG. 2G are cross-sectional views in order of steps showing the manufacturing method of the first embodiment of the present invention.
First, an SOI substrate including a silicon substrate 11, a buried oxide film 12, and a silicon film 13 shown in FIG. Here, the film thickness of the silicon film 13 is an ultra-thin film of 10 nm. A gate insulating film 14, a first polycrystalline silicon film 15, and a stopper nitride film 16 are sequentially deposited on the silicon film 13 (FIG. 1B). Next, the etching end face is perpendicular to the stopper nitride film 16, and the first polycrystalline silicon film 15, the gate insulating film 14, and the silicon film 13 are inversely tapered (the angle θ formed between the bottom surface of the silicon film 13 and its side surface is The stopper nitride film 16, the first polycrystalline silicon film 15, the gate insulating film 14 and the silicon film 13 are etched so as to form an element isolation trench so as to have an obtuse angle. Next, an STI buried insulating film 17 is deposited, and the STI buried insulating film 17 is planarized by CMP (FIG. 1C). At this time, a stopper nitride film 16 is provided on the first polycrystalline silicon film 15, and this acts as a stopper in the CMP process. Therefore, the first polycrystalline silicon film 15 for forming a gate electrode is formed. Is not damaged during the CMP process.

Here, a method for forming an etching end face in a reverse tapered shape or a forward tapered shape in the etching step will be described. FIG. 3 shows the relationship between the flow rate ratio of SF ₆ gas and the taper angle (θ) in etching under an HBr—Cl ₂ —O ₂ —SF ₆ mixed gas atmosphere. As shown in FIG. 3, in the case of using the mixed gas, increasing the flow ratio of SF ₆ gas is forward tapered shape, a reverse tapered shape is obtained when the reduced flow rate of SF ₆ gas.
The reason is considered as follows. FIG. 4 is a schematic cross-sectional view showing the shape of a silicon taper formed when silicon is etched in an HBr—Cl ₂ —O ₂ —SF ₆ mixed gas atmosphere, as in FIG. FIG. 4 (a), under the mixed gas atmosphere, when the flow ratio of SF ₆ gas is small, Fig. 4 (b) when the flow ratio of SF ₆ gas is large, shows the shape of the taper being formed Yes.

When the flow rate ratio of SF ₆ gas is small (FIG. 4A), in the initial stage of etching, etching products are deposited and a side surface protective film is formed at the end of the pattern. Since this side surface protective film has an action of protecting silicon from etching, side etching hardly occurs in the vicinity of the boundary between the mask material and silicon. However, the side surface protective film is hardly formed in the lower region. Therefore, the protective action against etching by the side surface protective film is reduced in the lower region portion, and side etching occurs mainly in the lower region portion of silicon. As a result, a reverse taper shape is obtained as the final shape [FIG. 4 (a)].

On the other hand, as shown in FIG. 4B, when the flow rate ratio of SF ₆ gas is large, it is difficult to form a side surface protective film during etching. Therefore, since there is no protective action against etching by the side surface protective film, side etching becomes remarkable from the beginning of etching, and the lower region portion of the mask material is intensively etched. Therefore, as the final shape, a forward tapered shape is obtained in which the upper region of silicon is strongly influenced by side etching in the lower region of the mask material.
A comparison with the case where the element isolation trench is formed in a forward tapered shape will be described later in [Comparative Example].

By the way, in the present embodiment, in the etching for forming the element isolation trench, both the first polycrystalline silicon film 15 which is the gate electrode material and the silicon film 13 have a reverse taper shape. Formed as follows. However, even if only the first polycrystalline silicon 15 has an inverse tapered shape, residual polycrystalline silicon can be prevented when the gate electrode portion is formed. This is because the silicon film 13 is not etched when the gate electrode portion is formed.
Here, the stopper nitride film 16 is etched vertically, but there is no problem even if it is formed in an inversely tapered shape.

  Next, as shown in FIG. 1D, the stopper nitride film 16 and a part of the STI buried insulating film 17 are removed, and the first polycrystalline silicon film 15 is exposed. At this time, in order to make the surface heights of the first polycrystalline silicon film 15 and the STI buried insulating film 17 equal, the stopper nitride film 16 and the STI buried insulating film 17 are etched by RIE under constant-speed etching conditions. Thereby, as shown in FIG. 1D, when the stopper nitride film 16 is removed, the heights of the first polycrystalline silicon film 15 and the STI buried insulating film 17 become equal.

A condition setting method for the constant speed etching method will be described below. FIG. 5 shows the relationship between the etching rate of SiO ₂ (STI buried insulating film 17) and Si ₃ N ₄ (stopper nitride film 16) and the flow rate ratio of O ₂ gas. This data was obtained by etching using a CHF ₃ —O ₂ —Ar mixed gas. From this figure, it can be seen that as the flow rate ratio of O ₂ gas increases, the etching rate of SiO ₂ decreases, while the etching rate of Si ₃ N ₄ increases, and the etching rates of both are equal at a certain point. I understand.
The etching operation for obtaining the state shown in FIG. 1 (d) is preferably performed under constant speed conditions, but the etching rate ratio between the two is within 20% even if etching cannot be performed under uniform speed conditions. If so, there is no problem in practical use.

  By the way, if the stopper nitride film 16 is removed by hot phosphoric acid in the process from FIG. 1C to FIG. 1D, the STI buried insulating film 17 is on the upper side by the thickness of the stopper nitride film 16. A protruding step is generated. Such a step deteriorates the shape of the gate electrode in the subsequent gate electrode formation step. However, in the present embodiment, the constant-speed etching method prevents a step between the first polycrystalline silicon film 15 and the STI buried insulating film 17, so that highly accurate patterning is possible. .

Here, in addition to the constant-speed etching method, the following means are effective as a method for eliminating the step.
In FIG. 1C, the upper ends of the stopper nitride film 16 and the STI buried insulating film 17 are planarized by CMP. Subsequently, the STI buried insulating film 17 is etched to the height below the stopper nitride film 16 under the RIE condition that is faster than the stopper nitride film 16 [FIG. 2 (h)]. Next, the stopper nitride film 16 is selectively removed with hot phosphoric acid.
Next, a second polycrystalline silicon film 18 for forming a gate lead-out wiring for leading the gate electrode to the outside of the element region is deposited [FIG. 2 (e)]. Subsequently, the second and first polycrystalline silicon films are patterned by lithography and a high-density plasma etching technique, and a gate lead-out wiring and a gate composed of the second polycrystalline silicon film 18 and the first polycrystalline silicon film 15 are obtained. A laminated structure of electrodes is formed [FIG. 2 (f)].
Next, an oxide having a thickness of 80 nm is formed on the entire surface by a chemical vapor deposition (hereinafter referred to as CVD) method, and then anisotropic dry etching is performed to form a sidewall insulating film on the sidewall of the gate electrode. 20 is formed. Next, source / drain regions 21 are formed by ion implantation and heat treatment. Subsequently, after a cobalt film is deposited on the entire surface by sputtering, heat treatment is performed to form a silicide film 22 and remove the cobalt film that has not been silicided. Next, after thickly forming the interlayer insulating film 23, contact holes are opened, a metal film such as aluminum is deposited by sputtering, and this is patterned to form a metal wiring 24 [FIG. 2 (g)].

  Here, since the patterning for forming the gate electrode is performed on the flat structure of the second polycrystalline silicon film 18 [FIG. 2 (e)], the element isolation groove has a reverse taper shape. Therefore, the polycrystalline silicon film does not remain on the sidewall of the STI buried insulating film 17. Furthermore, an electrical short circuit does not occur between the gate electrode and the source / drain region 21. Further, since the STI buried insulating film 17 has a structure protruding beyond the silicon film 13, the side surface of the silicon film is not covered with the gate electrode, and the reverse narrow channel effect which becomes a problem when using the conventional STI isolation is used. Can be suppressed. Further, it is not necessary to perform HF processing for the purpose of removing the pad oxide film (54 in FIG. 15) after the STI buried insulating film 17 is buried. Therefore, the STI buried insulating film 57 is not reduced or lost as in the case of the first conventional example. Therefore, over-etching of the buried oxide film 12 under the end of the silicon film, which becomes a problem when using an ultra-thin SOI substrate, does not occur. As a result, residual polycrystalline silicon (reference numeral 62 in FIG. 16) is not generated, and an electrical short circuit between the gate electrodes and between the gate electrode and the source / drain regions does not occur.

(Second Embodiment)
FIG. 6A to FIG. 7I are cross-sectional views in order of steps showing the manufacturing method of the second embodiment of the present invention. First, the gate insulating film 14, the first polycrystalline silicon film 15, and the stopper nitride film 16 are formed on the SOI substrate including the silicon substrate 11, the buried oxide film 12, and the 10 nm thick silicon film 13 shown in FIG. The layers are sequentially deposited (FIG. 6B).
Next, the stopper nitride film 16, the first polycrystalline silicon film 15, the gate insulating film 14 and the silicon film 13 are selectively etched to form element isolation trenches. At this time, the side surfaces of the stopper nitride film 16, the first polycrystalline silicon film 15, and the silicon film 13 are processed so as to have a reverse taper shape. Next, the STI buried insulating film 17 is deposited, and the STI buried insulating film 17 is planarized by CMP (FIG. 6C).

Next, the stopper nitride film 16 is removed using hot phosphoric acid to expose the surface of the first polycrystalline silicon film 15 (FIG. 6D). Subsequently, a second polycrystalline silicon film 18 is deposited [FIG. 6E], and further, the second polycrystalline silicon film 18 is planarized by CMP (FIG. 7F). In this CMP process, the STI buried insulating film 17 can be used as a stopper film.
Here, FIG. 8 shows a change with time of the polishing amount of polycrystalline silicon and silicon oxide (STI buried insulating film) in the CMP process. From FIG. 8, it can be seen that the polishing rate of polycrystalline silicon (polishing amount per minute) is about 1.5 times the polishing rate of silicon oxide, and when polishing the polycrystalline silicon film by the CMP method. It can be seen that the STI buried insulating film can be used as a stopper.

  Next, a third polycrystalline silicon film 25 for forming a gate lead-out wiring is deposited (FIG. 7G), and the laminated polycrystalline silicon film is patterned by lithography and high-density plasma etching technology. A gate lead-out wiring composed of the polycrystalline silicon film 25 and a gate electrode composed of a laminated structure of the first polycrystalline silicon film 15 and the first polycrystalline silicon film 18 are formed [FIG. 7 (h)]. Thereafter, the sidewall insulating film 20, the source / drain regions 21 and the silicide film 22 are formed by the same method as described in the first embodiment, the interlayer insulating film 23 is deposited, and the metal wiring 24 is formed. This completes the MISFET [FIG. 7 (i)]. In the present embodiment, the constant-speed etching method or the like is not used, and the process proceeds to the next step with a step difference [FIG. 6 (d)]. However, after the second polycrystalline silicon film 18 is deposited [FIG. 6 (e)], the STI buried insulating film 17 acts as a stopper in the next CMP step, so that the second polycrystalline silicon film 18 and The level difference from the STI buried insulating film 17 is eliminated [FIG. 7 (f)]. Further, after the third polycrystalline silicon film 25 is formed on the flat structure [FIG. 7G], the patterning for forming the gate electrode is performed, so that the generation of residual polycrystalline silicon can be suppressed. . Therefore, the same effect as the first embodiment can be obtained. That is, an electrical short circuit between the gate electrode and the source / drain regions and between the gate electrodes does not occur. In addition, the reverse narrow channel effect which is a problem when STI separation is used by the conventional method is suppressed. Further, since the HF process is not performed, the STI buried insulating film 17 is not reduced or lost.

(Third embodiment)
FIG. 9A to FIG. 10G are cross-sectional views in order of steps showing the manufacturing method of the third embodiment of the present invention. This embodiment is a method in which the first polycrystalline silicon film 15 and the silicon film 13 do not have an inversely tapered shape.
A gate insulating film 14, a first polycrystalline silicon film 15, and a stopper nitride film 16 are sequentially deposited on an SOI substrate having a silicon substrate 11, a buried oxide film 12, and a silicon film 13 shown in FIG. FIG. 9 (b)]. Next, the device isolation trench is formed by selectively etching the stopper nitride film 16, the first polycrystalline silicon film 15, the gate insulating film 14 and the silicon film 13, and at this time, the side surface of the device isolation trench is formed vertically. To be. Subsequently, an STI buried insulating film 17 is deposited and flattened by a CMP method (FIG. 9C).

Next, by using a constant speed etching method, when the stopper nitride film 16 is removed, the upper surface of the first polycrystalline silicon film 15 and the upper surface of the STI buried insulating film 17 become substantially the same height. [FIG. 9 (d)]. Instead of this method, first, the STI buried insulating film 17 is once etched to almost the same height as the lower surface of the stopper nitride film 16 (FIG. 10H), and then the stopper nitride film 16 is removed by hot phosphoric acid. To do. Thereafter, the process is advanced by the same method as in the first embodiment (FIGS. 10E and 10F), and the MISFET is completed [FIG. 10G].
In this method, the persistence of the polycrystalline silicon at the time of forming the gate electrode is slightly inferior to that of the first embodiment by the amount that the taper angle θ is perpendicular to the first polycrystalline silicon film 15. It seems to be. However, in this method, the first polycrystalline silicon film 15 and the STI buried insulating film 17 are planarized by a constant speed etching method, or the STI buried insulating film 17 is etched to the lower end of the stopper nitride film 16. After removing [FIG. 10H], the stopper nitride film 16 is removed and planarized to suppress the generation of residual polycrystalline silicon.

(Fourth embodiment)
FIG. 11A to FIG. 12I are cross-sectional views in order of steps showing the manufacturing method of the fourth embodiment of the present invention. A gate insulating film 14, a first polycrystalline silicon film 15, and a stopper nitride film 16 are sequentially deposited on an SOI substrate having a silicon substrate 11, a buried oxide film 12, and a silicon film 13 shown in FIG. FIG. 11B]. Next, the stopper nitride film 16, the first polycrystalline silicon film 15, the gate insulating film 14 and the silicon film 13 are selectively etched to form an element isolation trench having a vertical side surface, and an STI buried insulating film 17 is deposited. Then, planarization is performed by CMP (FIG. 11C).
Next, the stopper nitride film 16 is removed using hot phosphoric acid to expose the surface of the first polycrystalline silicon film 15 (FIG. 11D).

Next, a second polycrystalline silicon film 18 is deposited [FIG. 11E], and the second polycrystalline silicon film 18 is planarized by CMP (FIG. 11F). In this CMP process, the STI buried insulating film 17 can be used as a stopper film.
Next, a third polycrystalline silicon film 25 for forming a gate lead-out wiring is deposited (FIG. 12G), and the laminated polycrystalline silicon film is patterned by lithography and high-density plasma etching technology. Then, a gate lead wiring composed of the polycrystalline silicon film 25 and a gate electrode composed of a laminated structure of the second polycrystalline silicon film 18 and the first polycrystalline silicon film 15 are formed [FIG. 12 (h)].
Thereafter, the sidewall insulating film 20, the source / drain regions 21, and the silicide film 22 are formed by the same method as that described in the first embodiment, the interlayer insulating film 23 is deposited, and the contact hole is opened. After that, the metal wiring 24 is formed to complete the MISFET [FIG. 12 (i)].
In this method, since the second polycrystalline silicon film 18 is deposited and then planarized by CMP using the STI buried insulating film 17 as a stopper, the same effect as that of the second embodiment can be obtained.

Next, specific examples will be described.
Example 1
An example based on the first embodiment of the present invention will be described with reference to FIG. 1 and FIG. First, an SOI substrate comprising a silicon substrate 11, a buried oxide film 12 having a thickness of 50 to 100 nm, and a silicon film 13 having a thickness of 10 nm is prepared [FIG. 1 (a)]. Then, after forming a gate insulating film 14 having a thickness of 1.5 nm, a first polycrystalline silicon film 15 having a thickness of 50 nm and a stopper nitride film 16 having a thickness of 50 nm are sequentially deposited (FIG. 1B).
Next, after forming a resist film by photolithography, the stopper nitride film 16 is etched using the resist film as a mask so that the etching side surface is vertical, and then the first polycrystalline silicon film 15, the gate insulating film 14, and the silicon The film 13 is sequentially etched so as to have a reverse taper shape to form an element isolation groove.

Next, an STI buried insulating film 17 made of a high-density plasma oxide film having a thickness of 300 nm is deposited, and the STI buried insulating film 17 is planarized by CMP (FIG. 1C). Here, in the CMP method using a high-purity colloidal silica slurry, the high-density plasma oxide film has a value five times or more higher than the polishing rate of the nitride film. Therefore, in the CMP polishing of the STI buried insulating film 17, the stopper nitride film 16 functions sufficiently as a stopper film even if the film thickness is 50 nm.
Next, the stopper nitride film 16 and the STI buried insulating film 17 are etched by RIE under constant-speed etching conditions to expose the first polycrystalline silicon film 15.

Next, in order to form a gate lead-out wiring, a second polycrystalline silicon film 18 having a thickness of 100 nm is deposited [FIG. 2 (e)], and subsequently, stacked and multi-layered using lithography and high-density plasma etching. The crystalline silicon film is patterned to form a laminated structure of a gate lead-out wiring made of the second polycrystalline silicon film 18 and a gate electrode made of the first polycrystalline silicon film 15 [FIG. 2 (f)].
Next, after depositing a silicon oxide film having a thickness of 80 nm on the entire surface by CVD and performing anisotropic etching to form the sidewall insulating film 20, the source / drain regions 21 are formed by ion implantation and heat treatment. As the formation conditions of the source / drain regions at this time, for example, the source / drain layers in the nMISFET region are ion-implanted under the conditions of As ⁺ with energy: 8 keV and dose: 4 × 10 ¹⁵ ions / cm ^−2. In addition, the source / drain layer in the pMISFET region is formed under the conditions of, for example, B ⁺ with an energy of 2 keV and a dose of 5 × 10 ¹⁵ ions / cm ⁻² . Further, activation treatment (heat treatment) is performed at 1010 ° C. for 10 seconds.
Thereafter, a CoSi ₂ silicide film 22 having a thickness of 5 nm is formed, followed by forming an interlayer insulating film 23 having a thickness of 500 nm, and forming a metal wiring 24 after opening a contact hole, thereby completing a MISFET. [FIG. 2 (g)].

(Example 2)
Next, an example based on the second embodiment of the present invention will be described with reference to cross-sectional views in the order of steps in FIGS.
First, an SOI substrate including a silicon substrate 11, a buried oxide film 12 having a thickness of 50 nm to 100 nm, and a silicon film 13 having a thickness of 10 nm is prepared as shown in FIG. Next, a gate insulating film 14 having a thickness of 1.5 nm is formed, and a first polycrystalline silicon film 15 having a thickness of 50 nm and a stopper nitride film 16 having a thickness of 50 nm are sequentially deposited [FIG. 6B].
Subsequently, a resist film is formed by photolithography, and the stopper nitride film 16, the first polycrystalline silicon film 15, the gate insulating film 14 and the silicon film 13 are sequentially etched so as to have a reverse taper by using the resist film as a mask. An element isolation trench is formed. Next, an STI buried insulating film 17 made of a high-density plasma oxide film having a thickness of 300 nm is deposited and planarized by CMP (FIG. 6C).

Next, the stopper nitride film 16 is removed using hot phosphoric acid to expose the first polycrystalline silicon film 15 (FIG. 6D), and then the second polycrystalline silicon film 18 having a thickness of 100 nm. [FIG. 6 (e)]. Thereafter, the second polycrystalline silicon film 18 is planarized by CMP (FIG. 7F). Here, the STI buried insulating film 17 functions as a stopper when the second polycrystalline silicon film 18 is planarized.
Next, as shown in FIG. 7G, a third polycrystalline silicon film 25 having a thickness of 100 nm for forming a gate lead-out wiring is deposited. Subsequently, the stacked polycrystalline silicon film is patterned by lithography and high-density plasma etching technology, and the gate lead-out wiring made of the third polycrystalline silicon film 25, the second polycrystalline silicon film 18 and the first polycrystalline silicon film A gate electrode having a laminated structure of the crystalline silicon film 15 is formed (FIG. 7H).

Next, after depositing a silicon oxide film having a thickness of 80 nm on the entire surface by CVD and performing anisotropic etching to form the sidewall insulating film 20, the source / drain regions 21 are formed by ion implantation and heat treatment. As the formation conditions of the source / drain regions at this time, for example, the source / drain layers in the nMISFET region are ion-implanted under the conditions of As ⁺ with energy: 8 keV and dose: 4 × 10 ¹⁵ ions / cm ^−2. In addition, the source / drain layer in the pMISFET region is formed under the conditions of, for example, B ⁺ with an energy of 2 keV and a dose of 5 × 10 ¹⁵ ions / cm ⁻² . Further, activation treatment (heat treatment) is performed at 1010 ° C. for 10 seconds.
Thereafter, a CoSi ₂ silicide film 22 having a thickness of 5 nm is formed, followed by forming an interlayer insulating film 23 having a thickness of 500 nm, and forming a metal wiring 24 after opening a contact hole, thereby completing a MISFET. [FIG. 7 (i)].

[Comparative example]
Here, an example in which the etching shape of the polycrystalline silicon film 15, the gate insulating film 14, and the silicon film 13 is processed to be a forward tapered shape with respect to the first embodiment is shown as a comparative example. This will be described with reference to FIGS. 13 (a) to 14 (f).
Similar to the first embodiment, an SOI substrate having a silicon substrate 11, a buried oxide film 12 and a silicon film 13 is prepared (FIG. 13A), and a gate insulating film 14 and a first polycrystal are formed thereon. A silicon film 15 and a stopper nitride film 16 are sequentially deposited (FIG. 13B).
Next, after patterning the stopper nitride film 16 so that the end face is vertical, the polycrystalline silicon film 15, the gate insulating film 14, and the silicon film 13 are patterned so as to have a forward tapered shape (θ is an acute angle). A separation groove is formed. Subsequently, an STI buried insulating film 17 is deposited and planarized by CMP (FIG. 13C). Next, the first polycrystalline silicon film 15 and the STI buried nitride film 17 are planarized by, for example, a constant-speed etching method [FIG. 14D], and then a second polycrystalline silicon film 18 is deposited [ FIG. 14 (e)]. Next, in the step of patterning the laminated polycrystalline silicon film by plasma etching or the like, the lower end face of the first polycrystalline silicon film 15 covered with the STI buried insulating film 17 is shielded by the STI buried insulating film 17. As a result, residual polycrystalline silicon 19 is generated without being etched (FIG. 14F). As a result, since this residual polycrystalline silicon 19 is connected to the gate electrode, the leakage current between the parallel gate electrodes is generated, and the parasitic capacitance in the gate electrode is increased.

  If the device isolation groove is processed to have a forward tapered shape as in this comparative example, residual polycrystalline silicon 19 is generated, which is not preferable. Further, in a short channel SOI-MOSFET, a drain current may be concentrated in the lower corner of the element region, thereby causing a leakage current. However, if the silicon film 13 is also processed to have a reverse taper shape and an obtuse angle is formed at the lower corner of the element region end, the electric field is difficult to concentrate. That is, it is preferable that the element isolation groove has a reverse taper shape in that generation of a leakage current can be suppressed.

11, 51 Silicon substrate 12, 52 Embedded oxide film 13, 53 Silicon film 14, 60, 68 Gate insulating film 15, 70 First polycrystalline silicon film 16, 55 Stopper nitride film 17, 57, 69 STI embedded insulating film 18 , 71 Second polycrystalline silicon film 19, 62 Residual polycrystalline silicon 20, 63 Side wall insulating film 21, 64 Source / drain region 22, 65 Silicide film 23, 66 Interlayer insulating film 24, 67 Metal wiring 25 Third poly Crystalline silicon film 54 pad oxide film 56 element isolation trench 58 mask pattern 59 overetching 61 polycrystalline silicon film 70a gate electrode 71a gate electrode line 72 end

The present invention relates to semiconductor equipment, using an SOI (Silicon On Insulator) substrate having a particularly semiconductor layer of a single crystal formed through the buried oxide film on the semiconductor substrate, it relates to a structure of a semiconductor device is there.

In order to achieve the above object, according to the present invention, a semiconductor layer having a channel region and a source / drain region provided in an island shape on an insulator film, and the semiconductor layer that is a channel region A gate electrode provided on the top via a gate insulating film; and an element isolation insulating film formed on the insulator film so as to surround the semiconductor layer and having an upper surface protruding upward from the upper surface of the semiconductor layer; A side surface of the element isolation insulating film and a side surface of the gate electrode in contact with the side surface of the element isolation insulating film are formed in a reverse taper shape. Is done.
Preferably, the side surface of the semiconductor layer is formed to have a reverse taper shape. More preferably, the height of the upper surface of the element isolation insulating film is substantially equal to the height of the upper surface of the gate electrode.

In the semiconductor device of the present invention, the polycrystalline silicon film for the gate electrode in contact with the element isolation trench is formed so as to have a reverse taper shape, so that the generation of residual polycrystalline silicon can be prevented in advance when the gate electrode is formed. It is possible to suppress the generation of leakage current between the gate electrodes and the increase in parasitic capacitance in the gate electrode. In addition, since the element isolation insulating film is formed so as to cover the side surface of the silicon film and protrude from the silicon film, it is possible to suppress an increase in leakage current and to suppress the expression of the reverse narrow channel effect. Further, by forming the silicon film in a reverse taper shape, the concentration of the electric field can be reduced and the leakage current can be reduced .

Claims (18)

  A semiconductor layer having a channel region and a source / drain region provided by patterning in an island shape on the insulator film, and a gate electrode provided above the semiconductor layer which is the channel region via a gate insulating film, A device isolation insulating film formed on the insulator film so as to surround the semiconductor layer and having an upper surface protruding upward from the upper surface of the semiconductor layer; and a side surface of the element isolation insulating film The side surface of the said gate electrode which touches is formed in the reverse taper shape, The semiconductor device characterized by the above-mentioned.   2. The semiconductor device according to claim 1, wherein a side surface of the semiconductor layer is formed in a reverse taper shape.   The semiconductor device according to claim 1, wherein a gate electrode lead-out wiring extending in contact with the upper surface of the gate electrode and extending on the upper surface of the element isolation insulating film is formed.   The semiconductor device according to claim 1, wherein the gate electrode is formed of a first conductive material layer and a second conductive material layer provided on the first conductive material layer.   The semiconductor device according to claim 1, wherein the height of the upper surface of the element isolation insulating film is substantially equal to the height of the upper surface of the gate electrode.   The semiconductor device according to claim 1, wherein the insulator film and the semiconductor layer are a buried insulating film of an SOI substrate and a silicon film formed thereon. (1) a step of sequentially forming a gate insulating film, a first conductor layer, and a first insulating film on a semiconductor layer on the insulator film;
(2) forming an element isolation trench by etching and processing the semiconductor layer, the gate insulating film, the first conductor layer, and the first insulating film into an island shape;
(3) depositing a second insulating film on the entire surface;
(4) performing a planarization process to substantially match the height of the upper surface of the second insulating film with the height of the upper surface of the first insulating film;
(5) The first insulating film is removed and the second insulating film is removed by the thickness of the first insulating film to expose the height of the upper surface of the second insulating film. A step of substantially matching the height of the upper surface of the semiconductor layer;
(6) depositing a second conductor layer on the entire surface;
(7) patterning the second and first conductor layers to form a gate electrode and a gate lead-out wiring led out from the gate electrode;
A method for manufacturing a semiconductor device, comprising:   8. The method of manufacturing a semiconductor device according to claim 7, wherein the step (5) is performed by an RIE (Reactive Ion Etching) method.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the step (5) is performed by removing the second insulating film by an RIE method and removing the first insulating film by a wet method. Method. (1 ′) a step of sequentially forming a gate insulating film, a first conductor layer, and a first insulating film on the semiconductor layer on the insulator film;
(2 ′) forming an element isolation trench by etching and processing the semiconductor layer, the gate insulating film, the first conductor layer, and the first insulating film into an island shape;
(3 ′) depositing a second insulating film on the entire surface;
(4 ′) performing a planarization process so that the height of the upper surface of the second insulating film substantially matches the height of the upper surface of the first insulating film;
(5 ′) removing the remaining first insulating film;
(6 ') A step of depositing a third conductor layer and subjecting it to a flattening process to form a third conductor layer having an upper surface whose height is substantially equal to the height of the upper surface of the second insulating film. When,
(7 ′) depositing a second conductor layer on the entire surface;
(8 ′) patterning the second, third and first conductor layers to form a gate electrode and a gate lead-out wiring led out from the gate electrode;
A method for manufacturing a semiconductor device, comprising:   11. The method of manufacturing a semiconductor device according to claim 10, wherein the planarization process of the (6 ') step is performed by a CMP (Chemical Mechanical Polishing) method.   The method for manufacturing a semiconductor device according to claim 7, wherein the planarization process in the step (4) or the step (4 ′) is performed by a CMP method.   13. The method for manufacturing a semiconductor device according to claim 7, wherein the etching in the step (2) or the step (2 ') is performed by an RIE method.   The etching in the step (2) or the step (2 ′) is performed by performing the first conductor layer and the semiconductor layer, or the first insulating film, the first conductor layer, and the semiconductor layer. The method of manufacturing a semiconductor device according to claim 7, wherein the side surfaces of the semiconductor device are formed in a reverse tapered shape. The semiconductor according to claim 7, wherein the etching in the step (2) or the step (2 ′) is performed using an HBr—Cl ₂ —O ₂ —SF ₆ -based gas. Device manufacturing method. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the etching in the step (2) or the step (2 ′) is performed while controlling the inclination of the etching side surface by adjusting the flow rate of O _2. Method.   17. The method of manufacturing a semiconductor device according to claim 7, wherein the first insulating film is a silicon nitride film and the second insulating film is a silicon oxide film.   The first conductor layer and the second conductor layer, or the first conductor layer, the second conductor layer, and the third conductor layer are formed of polysilicon. A method for manufacturing a semiconductor device according to claim 7, wherein:

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