JPH0482270A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To effectively suppress a hump phenomenon in a subthreshold characteristic by a method wherein one implantation process is added without changing an ordinary manufacturing apparatus. CONSTITUTION:A mask 2 is formed on a silicon substrate 1. While an ion beam 3 is tilted at an angle to the substrate 1 and a wafer is turned, ions are implanted into ends 5a, 5b in the lower part of the mask. After that, a groove is formed in the substrate 1 by an etching process by making use of the protruding part 2 as a mask; ions are implanted; and ion implantation region 4 is formed. Adjacent elements are isolated electrically by the region 4. Then, the groove is filled with an oxide film 6 or the like; a MOS element is completed. Thereby, the ions are implanted surely into the channel edge part of the MOS element, a high-concentration region can be formed, and a hump phenomenon in a subthreshold characteristic can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device.Background ArtIn a conventional semiconductor device, a buried isolation method has been used to reduce the element isolation region as the density increases. An example of this prior art will be explained using FIG. 3.

This figure is a cross-sectional view along the Y-Y' direction shown in FIG. 4. A groove (or recess) is formed in a silicon substrate 31, and an ion implantation region 32 for channel stop is formed at the bottom of the groove by boron ion implantation.The groove is filled with an oxide film 33 or the like to form a "6" MOSFET. here 3
4 is a gate electrode.

In this structure, no boron is implanted into the silicon trench sidewalls, and the boron concentration is the same as the substrate concentration. Third
In the case shown in the figure, boron is sucked out during the oxidation process after boron ion implantation, resulting in a decrease in surface concentration.Vt of the MO8 element formed in the active region decreases at the edge of the channel.

For this reason, a hump phenomenon like A appears in the subthreshold current of the MOS transistor shown in FIG.

Therefore, a method has been proposed in which the subthreshold current characteristics of the MO8 element to be manufactured later are improved by tilting the wafer and implanting boron into the etched side surface. As shown in FIGS. 5(a) to 5(c), a mask 52 is formed on a silicon substrate 51 and the isolation region is etched away.The wafer is then tilted and boron 53 is implanted. It is formed not only on the bottom but also on the sides.

Problems to be Solved by the Invention However, in order to suppress this hump phenomenon, a method has been proposed in which ions are implanted into the side wall of the recess as shown in FIG. If the angle (θ) with the side wall is small, the beam will be reflected by the side wall, making the ion concentration implanted into the side wall unstable.
θ3) has less reflection and stable injection.

Therefore, in order to prevent reflection, it is possible to increase the angle between the beam and the side wall. It becomes difficult to implant ions into the region. Another problem is that the sidewalls of the grooves are not necessarily perpendicular to the plane of the silicon substrate (see Figure 9).
As shown in a) and (b), the present invention has a problem in that it becomes tapered (a) or inverted tapered (b), which also causes instability in the amount of ions implanted. In view of this, an object of the present invention is to provide a method for manufacturing a semiconductor device having stable subthreshold characteristics in an MO3 element without changing conventional manufacturing equipment.

Means for Solving the Problems The present invention provides a method for manufacturing a semiconductor device having a highly concentrated ion implantation region in a channel edge portion directly under a gate electrode in an MO3 type semiconductor device using buried isolation. forming a mask for the mask, and performing ion implantation by tilting the angle between the wafer surface and a plane perpendicular to the ion beam, and installing the wafer so that ions are implanted also into a part of the lower part of the mask. ((The wafer is rotated on the installation plane of the wafer, the wafer is placed in a second position where ions can be implanted into the other part of the lower part of the mask, and ions are implanted into the desired part of the lower part of the mask. A method for manufacturing a semiconductor device, comprising a step of implanting ions, and a step of forming a recessed portion using the ion implantation mask.

Effect of the Invention With the above-described configuration, the present invention eliminates instability of the implantation amount due to reflection of the ion concentration at the channel edge portion of the transistor due to buried isolation by adding one implantation step without changing the conventional manufacturing equipment. Embodiment of preventing the drop in Vt at the channel edge portion and effectively suppressing the hump phenomenon in subthreshold characteristics Figures 1(a) to 1(f) show the first embodiment of the present invention. This figure shows a process cross-sectional view of a schematic manufacturing method of a semiconductor device in an example. This figure is a cross-sectional view in the y-Y" direction shown in FIG. 4.

In FIG. 1(a), a mask 2 for ion implantation and recess formation is formed on a silicon substrate 1.

In FIG. 1(b, c), the ion beam 3 is implanted at an angle (for example, 20 to 45 degrees) with respect to the silicon substrate so that it is also implanted into the lower part 5a of the mask 2.The wafer is rotated. Then, ions are implanted into the other end 5b of the lower part of the mask.

1 in FIG. 1(d). Thereafter, a groove (or recess) is formed in the silicon substrate 1 by an etching process using the projection 2 as a mask.

In FIG. 1(e), ions are further implanted into the bottom of the trench to form an ion implantation region 4. This ion implantation region 4
To electrically isolate adjacent elements, as shown in FIG. 1(f), the grooves are filled with an oxide film 6.

In FIG. 1(g), an MO8 element is completed using a known technique. Here, 7 is a gate electrode wiring.

As described above, with this manufacturing method, ions can be reliably implanted into the channel edge portion of the MO3 element without being affected by variations in other processes, and a high concentration region can be reliably formed at the channel edge portion. Therefore, the hang phenomenon in subthreshold characteristics can be eliminated.

FIG. 2 shows a cross-sectional structural diagram of a semiconductor device according to a second embodiment of the present invention. In Figure 2, 5 a
, 5b is a high concentration ion implantation region provided at the channel edge, 4 is an ion implantation region provided at the bottom of the groove (or recess), and 4a is a high concentration ion implantation region provided on the side wall of the trench (or recess) by tilting the angle between the ion beam and the wafer. The implanted ion implantation region.

4i In this embodiment, an ion implantation region 4a is further provided on the trench side wall compared to the first embodiment.

As described in detail, according to the present invention, by adding one ion implantation step to the conventional manufacturing method, the ion concentration at the channel edge portion of the transistor due to buried isolation can be reduced by ion beam reflection or other steps. It is possible to reliably increase the implantation amount without causing instability due to the influence of shape variations in the channel, to prevent the drop in Vt at the channel edge, and to effectively suppress the hump phenomenon in the subthreshold characteristics, which has a great practical effect. .

[Brief explanation of the drawing]

Figure 1 is a process cross-section of a schematic manufacturing method of a semiconductor device according to the first embodiment of the present invention @ Figure 2 is a cross-sectional structure diagram of a semiconductor device according to the second embodiment of the present invention Figures 3 and 5 are Figure 4 is a cross-sectional diagram for explaining a conventional semiconductor device and its manufacturing method. Figure 4 is a plane view of an MO8 type semiconductor device. FIG. 9 is an explanatory diagram of the conventional problem. 1...Silicon substrate (wafer), 2...Masuku 3
...AEON B A, 4.4a, 5a, 5b...
Ion implantation area 6...Oxidation wind 7...Name of gate electric cage agent Patent attorney Shigetaka Awano and one other person 1 Figure Figure Figure Figure Figure Figure Happy Figure Gate 9 Catty<V) Figure Figure Figure Figure

Claims (1)

[Claims] forming a mask for ion implantation on a semiconductor wafer; and installing the wafer so that ions are implanted under a part of the mask by tilting the angle between the wafer surface and a plane perpendicular to the ion beam. The wafer is rotated on the installation plane of the wafer, and the wafer is placed in a position where ions can be implanted into another part of the lower part of the mask, and ions are implanted into the desired lower part of the mask. A method for manufacturing a semiconductor device, comprising the steps of implanting ions, and then forming a recess inside the semiconductor wafer using the ion implantation mask.