JPH02219272A - Manufacture of mis type semiconductor device - Google Patents

Abstract

PURPOSE:To suppress an excessive side-wall current by providing high- concentration diffused layers of the same conduction type as that of a substrate on side faces of the substrate facing a groove without relying on channel widths by controlling widths of side wall insulating films. CONSTITUTION:An insulating film 2 is selectively formed on one conductive type semiconductor substrate 1 and a groove section 3 which becomes a groove type insulating separation layer is formed by etching the substrate 1 by using the film 2 as a mask. Then, after forming side wall insulating films 4 on both side walls of the groove section 3 and insulating films 2, diffused layers 7 having a concentration which is different from that of the substrate 1 are formed on side faces of the substrate facing the groove type insulating separation layer by implanting impurity ions into the substrate 1 through the films 4. Therefore, an excessive side-wall current can be suppressed by providing the high- concentration diffused layers 7 (silicon oxide layers) of the same conduction type as that of the substrate on the side faces of the substrate facing the groove 3 without relying on channel widths by controlling widths of the side-wall insulating films 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing an MIS type semiconductor device having a groove type insulating layer in an ultra-high density LSI.

Conventional Technology IEEE Transactions on Electron Devices r (IEEE T
RANSACTION ON ELECTRON DE
VICES), VOL, ED-32, NO2, 198
5J P, 441-445. N, ShIgyo, e
A sloped groove-type insulating layer structure in which a groove with a slope is formed and an impurity of the same conductivity type as the substrate is implanted using the slope proposed in the R1985 Symposium on B.I. Technology (SYM
PO5IUM ON VLSI TECHNOLOGY
) J P, 58-59. G, Fuse, et al.
There is a trench-type isolation layer structure with oblique impurity implantation of the same conductivity type as the substrate, which was proposed in .

First, FIG. 6 shows a cross-sectional view of a MIS type semiconductor device having a sloped groove-type insulating separation layer when the semiconductor substrate is of P type. In this case, in the old S-type semiconductor device having a groove-type insulating separation layer with an inclination as described above, the vertical isolation that improves the integration density, which is a characteristic of trench-type isolation, is not formed.
Process control of the tilt angle is difficult.

Further, FIG. 7 shows a cross-sectional view of a MIS type semiconductor device having a trench type insulating layer with oblique impurity implantation when the semiconductor substrate is of P type. In this case, in a trench-type semiconductor device having a trench-type insulating layer with oblique impurity implantation, the sidewall current is improved for devices with a large channel width, but only the sidewall current is improved for devices with a small channel width. The problem is that impurities of the same conductivity type cannot be implanted into the channel, and the sidewall current cannot be improved. This can be confirmed by examining the electron current density distribution in the channel width direction. FIG. 8 shows this current distribution. The figure shows n below the gate, in the channel width direction, at a position 8 nm from the oxide film/silicon interface.
It shows the electron current density distribution of channel MO8FET.

From the same figure, by diagonal impurity implantation, the channel width is large (W = 1°36 μm) at the threshold voltage.
It can be seen that although the sidewall current is suppressed in the case where the channel width is small (Who, 7 μm), the sidewall current flows excessively.

Problems to be Solved by the Invention The present invention provides a trench type insulation separation layer with a necessary depth and controls the sidewall insulation film thickness of the trench sidewalls, thereby providing a region on the side surface of the substrate in contact with the trench, regardless of the channel width. This method of manufacturing a semiconductor device aims to suppress excessive sidewall current by forming a highly doped diffusion layer of the same conductivity type as the substrate and using easy manufacturing technology.

In addition, in the trench type semiconductor device having a trench type insulating layer with oblique impurity implantation as described above, the back gate bias effect is large because impurities of the same conductivity type as the substrate are implanted into the entire side wall of the substrate in contact with the trench. There was a problem. The present invention has a groove-type insulating separation layer with a necessary depth, and forms a highly concentrated diffusion layer of the same conductivity type as the substrate in a part of the upper part of the side surface of the substrate that is in contact with the groove and in a region of the substrate that is in contact with the surface of the substrate. , is a method of manufacturing a semiconductor device that aims to suppress excessive sidewall current and back gate bias effect using a simple manufacturing technique.

Furthermore, in a trench semiconductor device having a trench isolation layer with oblique impurity implantation as described above, there is a problem in that the channel stop at the bottom of the trench isolation layer and the impurity implantation on the side surface of the substrate in contact with the trench are performed at the same time. Was. The present invention has a trench-type insulating separation layer with a necessary depth, and forms a highly concentrated diffusion layer of the same conductivity type as the substrate in a part of the upper part of the side surface of the substrate that is in contact with the trench and in a region of the substrate that is in contact with the surface of the substrate. By using simple manufacturing technology, excessive sidewall current can be suppressed, the back gate bias effect can be suppressed, and the channel stop at the bottom of the trench-type isolation layer and the impurity implantation at the side surface of the substrate in contact with the trench can be separated into separate processes. This is a method for manufacturing semiconductor devices that is intended to be performed with good control.

Furthermore, the method of filling the trenches by depositing an insulating film as described above has the problem that sidewall currents tend to flow because it is difficult to flatten the insulating film deposited in the trenches. The present invention is a method for manufacturing a semiconductor device, which aims to facilitate planarization by forming a sidewall insulating film on the sidewalls of a trench of a required depth and then depositing and filling the trench with an insulating film.

Means for Solving the Problems The present invention includes a first step of selectively forming an insulating film on one conductive type semiconductor substrate, and etching the semiconductor substrate using the insulating film as a mask to form a groove shape. a second etching step for forming a groove that will become an insulating separation layer;
and a third step of forming a sidewall insulating film on both side walls of the insulating film, and implanting impurity ions through the sidewall insulating film, and diffusing impurities at a concentration different from that of the substrate into the side surface of the substrate in contact with the groove-type insulating separation layer. This is a method for manufacturing an MIS semiconductor device characterized by comprising a fourth ion implantation step for forming a layer.

Effect of the present invention By controlling the width of the sidewall insulating film with the above-described configuration, the excessive sidewall current can be suppressed by having a highly concentrated diffusion layer of the same conductivity type as the substrate on the side surface of the substrate in contact with the groove, regardless of the channel width. Can be suppressed.

In addition, the present invention has the above-described structure and has a highly concentrated diffusion layer of the same conductivity type as the substrate in a part of the upper part of the side surface of the substrate in contact with the groove and in contact with the surface of the substrate, regardless of the channel width. It is possible to suppress sidewall current and improve the back gate bias effect.

Furthermore, according to the present invention, with the above-described structure, the channel stop at the bottom of the groove-type insulating isolation layer and the impurity implantation at the side surface of the substrate in contact with the groove can be performed in separate steps.

Further, according to the present invention, after a sidewall insulating film is formed on the sidewall of a trench of a required depth using the above-described structure, the trench can be easily flattened by depositing and filling the trench with an insulating film.

Embodiment (Embodiment 1) FIG. 1 shows an embodiment of a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. As an example, an n-channel MO8) transistor will be explained. Figure 1(a)
-(C) are cross-sectional views in the channel direction.

First, an insulating film 2 with a thickness of 1.3 μm is formed on a P-type silicon substrate 1 having a (100) plane, and then the substrate 1 is etched with a thickness of about 0.0 μm. A groove 3 with a depth of 5 μm is formed (Figure (a)
). At this time, the insulating film 2 may have a multilayer structure of, for example, polysilicon and a CVD oxide film.

Next, an insulating film is deposited on both side walls of the trench 3 to a desired thickness, and then removed by anisotropic etching to form a sidewall insulating film 4. Let the width of the sidewall insulating film 4 be Ls, and now Ls
Using the insulating film 2 and sidewall insulating film 4 with a diameter of 0.02 μm as masks, boron 5 was implanted at a dose of 2.0×10 cm 2 at an implantation angle of 8 cm and an energy of 80 kev four times (the semiconductor wafer was rotated four times). (injecting impurities)
A high concentration P1 region 6 is formed (FIG. 2(b)).

Furthermore, after removing the insulating film 2, a silicon oxide film 7 is deposited in the trench 3 to a thickness approximately the same as the depth of the trench, using the CVD method.
Dose amount 4. Boron 8 of OX 10"crrr2 was implanted at an implantation angle of 0° and an energy of 40 keys to form a ■τ control region 9, and then this V.

A MOS transistor is formed in the control region 9 by a well-known method.

As described above, according to this embodiment, the sidewall boron high concentration region can be controlled by the film thickness Ls of the sidewall insulating film 4 and the implantation energy, and the sidewall current can be suppressed even in the case where the channel width is small. .

(Embodiment 2) Furthermore, FIG. 2 shows an example of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
) is a cross-sectional view in the channel direction for explaining a transistor; The main steps are the same as in the first embodiment, and the steps in FIG. 2 (b') + (c') are replaced by the steps in FIG. 1 (b) and (C) in the first embodiment. This is what we do.

In the same figure (b'), an insulating film is deposited on both side walls of the trench 3 to a desired thickness, and then removed by anisotropic etching, so that the side wall insulating film thickness at the shoulder of the silicon substrate 1 becomes thinner. The sidewall insulating film 4 is formed in this manner. Now, the side wall insulating film 4
Let the width of LS be LS, now LS is 0.02μ, m, and the dose amount is 2.0 using the insulating film 2 and this sidewall insulating film 4 as a mask.
Boron 5 of X10"cm-2 is implanted four times at an implantation angle of 8° and an energy of 80 keV to form a high concentration P◆ region. Since the sidewall insulating film at the shoulder edge is thin, there is a large amount of boron 5 at the shoulder edge of the silicon substrate 1. It is possible to effectively form the high concentration P4 region 6. This point is one of the features that is significantly different from the first embodiment.

Furthermore, after removing the insulating film 2, a silicon oxide film 7 is deposited in the trench 2 to a thickness approximately equal to the depth of the trench 2 using the CVD method and planarized while leaving the sidewall insulating film 4 in the trench 3. Then, boron 8 with a dose of 4.0XIO"cm-2 is implanted at an energy of 40keV to form a VT control region 9, and then a MOS (MOS) transistor is formed by a well-known method using the same steps as in the first embodiment. form.

As described above, according to this embodiment, the sidewall boron high concentration region can be controlled by the sidewall insulating film thickness Ls and the implantation energy, and by controlling the amount of anisotropic etching of the sidewall insulating film, the sidewall boron high concentration region can be more effectively etched at the edge of the silicon substrate. Therefore, it is possible to form a region with a high boron concentration, thereby suppressing sidewall current even in a case where the channel width is small. In addition, planarization can be easily achieved by depositing a silicon oxide film after forming a sidewall insulating film with a thin shoulder edge.

(Embodiment 3) FIG. 3 shows an example of a method for manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps. As an example, an n-channel MO8) transistor will be explained. Figure 3(a)
-(d) are cross-sectional views in the channel direction.

First, after forming an insulating film 10 with a thickness of 1.3 μm on a silicon substrate 1 having a P-type (100) plane, a photoresist 11 is applied to the insulating film 10 to form a region that will become a transistor section.
0 (see figure (a)).

Next, the insulating film 10 is etched using the photoresist 11 to form the insulating film 2. Further, using this insulating film 2 as a mask, boron 5 at a dose of 2.0.times.10'' cm@-2 is implanted four times at an implantation angle of 8.degree.

Next, using the insulating film 2 as a mask, etching is performed to form a groove 3 with a depth of about 0.5 μm in the silicon substrate 1, and boron 13 is implanted at a dose of 1.0×IO” cm −2 at an angle of 0” energy. Inject at 25 keV to form a channel stop 14 at the bottom of the groove 3 ((C) in the same figure)
.

Furthermore, after removing the insulating film 2, a silicon oxide film 7 is deposited in the trench 3 by CVD to a thickness approximately equal to the depth of the trench, and at a dose of 4. Boron 8 of oxto12cm-2 was implanted at an implantation angle of 0° and an energy of 40keV to form a vT control region 9.
After forming, a MOS (MOS) transistor is formed by a well-known method.

As described above, according to the third embodiment, since the boron high concentration region is all formed in a separate process, it is easy to set the conditions. Furthermore, since a high boron concentration layer is formed in a part of the upper part of the side surface in contact with the groove, the back gate bias effect can be suppressed and the sidewall current can be effectively suppressed.

(Embodiment 4) FIG. 4 shows an example of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of steps. As an example, an n-channel MO8) transistor will be explained. Figure 4(a)
-(d) are cross-sectional views in the channel direction.

First, an insulating film 2 with a thickness of 0.5 μm is formed on a P-type silicon substrate 1 having a (100) plane, and the dose is 4°0XIO”c.
Boron 13 of m-2 is implanted at an angle of 0° and an energy of 700
Kev is implanted to form a highly doped layer 14 on the entire surface, leaving only the channel region shallow (FIG. 4(a)).

Next, a groove 3 with a depth of about 0.5 μm is formed in the substrate 1 by etching, and this groove 3 is etched with a depth of about 0.45 μm shallower than the depth of the groove.
A silicon oxide film 15 is deposited by the CVD method (see (b) in the same figure).
)).

Furthermore, using the insulating film 2 as a mask, the dose is 2.0XIO"
cm-2 boron 5, implantation angle 8” energy 8
Rotary implantation is performed four times at 0 keV to form a high concentration P+ region 6 (FIG. 4(C)).

Next, after removing the insulating film 2, a silicon oxide film 16 is deposited in the trench 3 to a thickness approximately equal to the depth of the trench, and boron 8 is implanted at a dose of 4.0XIO12crrr2 at an angle of 0° and energy. After forming a vT control region 9 by implanting 40 keys, a MOS transistor is formed by a well-known method.

As described above, according to the fourth embodiment, since the boron high concentration region is all formed in a separate process, it is easy to set the conditions. Furthermore, since a high boron concentration layer is formed in a part of the upper part of the side surface in contact with the groove, the back gate bias effect can be suppressed and the sidewall current can be effectively suppressed.

(Embodiment 5) FIG. 5 shows an example of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention in the order of steps. As an example, it is a cross-sectional view of the n-channel MO8) transistor.

First, an insulating film 2 with a thickness of 0.5 μm is formed on a P-type silicon substrate 1 having a (100) plane, and the substrate 1 is etched with a thickness of about 0.5 μm. A groove 3 with a depth of 5 μm is formed. Furthermore, boron 13 with a dose of 1.0×10"cm-" was implanted at an implantation angle of 0°.
Injected with energy 25keV, channel stop 1
4 is formed at the bottom of the groove (FIG. 4(a)).

Next, a silicon oxide film 15 of approximately 0.45 μm is deposited in the trench 3 to a depth shallower than the depth of the trench by the CVD method, using the insulating film 2 as a mask at a dose of 2. Boron 5 of OXIO 13cm-2 was injected 4 times at an injection angle of 8° and an energy of 80keV.
A high concentration P+ region 6 is formed (FIG. 2(b)).

Furthermore, after removing the insulating film 2, a silicon oxide film 16 is deposited in the trench 3 to a thickness approximately the same as the depth of the trench, using the CVD method.
Dose amount 4. Boron 8 of OX 1012 cm-2 is implanted at an implantation angle of 0° and an energy of 40 kev to form a vT control region 9, and then a MOS transistor is formed by a well-known method.

According to the fifth embodiment, since the high boron concentration region is all processed in a separate process, it is easy to set the conditions. Furthermore, since a high boron concentration layer is formed in a part of the upper part of the side surface in contact with the groove, the back gate bias effect can be suppressed and the sidewall current can be effectively suppressed.

As described in detail, according to the present invention, by controlling the width of the sidewall insulating film with the above-described configuration, high concentration diffusion of the same conductivity type as the substrate is formed on the side surface of the substrate in contact with the groove regardless of the channel width. By having the layer, excessive sidewall current can be suppressed.

Furthermore, the present invention eliminates excessive sidewall current by providing a highly concentrated diffusion layer of the same conductivity type as the substrate in a part of the upper part of the side surface of the substrate in contact with the groove and in contact with the surface of the substrate. can be suppressed and the backgate bias effect can be improved.

Further, according to the present invention, the channel stop at the bottom of the trench-type isolation layer and the impurity implantation into the side surface of the substrate in contact with the trench can be performed in separate steps.

Further, according to the structure of the present invention, a trench of a required depth can be easily flattened by forming a sidewall insulating film on the trench sidewall and then depositing and filling the trench with an insulating film, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the manufacturing process of an n-channel MO8) transistor according to the first embodiment of the present invention, and FIG. 2 is a partial cross-sectional view of the manufacturing process of an n-channel MO3) transistor of the second embodiment of the present invention. , FIG. 3 is a cross-sectional view of the manufacturing process of an n-channel MO8) transistor according to the third embodiment of the present invention, and FIG. 4 is a cross-sectional view of the manufacturing process of an n-channel MO8) transistor according to the fourth embodiment of the present invention. , FIG. 5 shows the n-channel M of the fifth embodiment of the present invention.
O8) Cross-sectional diagram of transistor manufacturing process, Figures 8 and 7
The figure is a partial sectional view of a conventional manufacturing process, and FIG. 8 is an electron current density distribution characteristic diagram of an n-channel MO8FET having a conventional trench-type separation layer and a standardized channel width. 1... P-type silicon substrate, 2... Insulating film, 3...
Groove, 4... side wall insulating film, 6... P'' region, 7...
Silicon oxide film, 9...VT control region. Name of agent: Patent attorney Shigetaka Awano and 1 other persona)

Claims (5)

[Claims] (1) A first step of selectively forming an insulating film on a semiconductor substrate of one conductivity type, and using the insulating film as a mask,
a second etching step of etching the semiconductor substrate to form a trench that will become a groove-type insulation separation layer; a third step of forming a sidewall insulating film on the trench and both side walls of the insulating film; Implanting impurity ions through the insulating film,
A method for manufacturing an MIS type semiconductor device, comprising a fourth ion implantation step of forming a diffusion layer having a concentration different from that of the substrate on a side surface of the substrate in contact with the groove-type insulating separation layer. (2) A first step of selectively forming an insulating film on a semiconductor substrate of one conductivity type, and using the insulating film as a mask,
a second etching step of etching the semiconductor substrate to form a groove that will become a groove-type insulating separation layer; a third step of forming a sidewall insulating film with a thin upper thickness only on the sidewalls of the groove; Implanting impurity ions through the insulating film,
a fourth ion implantation step in which a diffusion layer having a concentration different from that of the substrate is formed on a side surface of the substrate in contact with the trench-type insulating separation layer, and the concentration in the upper part of the diffusion layer is higher due to the thinner film thickness in the upper part; , a fifth step of depositing an insulating film in the trench while forming the sidewall insulating film to form a trench-type insulating isolation layer.
A method for manufacturing an S-type semiconductor device. (3) A first step of forming an insulating film on one semiconductor substrate, and a diffusion layer having a concentration different from that of the substrate by ion implantation at an angle of 7° or more using the insulating film as a mask. a second step, and a third step of etching the substrate using the insulating film as a mask to form a trench that will become a trench-type insulation separation layer; and forming a diffusion layer having a concentration different from that of the substrate at the bottom of the trench. A method for manufacturing an MIS type semiconductor device, comprising a fourth injection step. (4) A first step of selectively forming an insulating film on a semiconductor substrate of one conductivity type, and a second step of ion-implanting impurities to form a highly concentrated layer of the same conductivity type as the substrate. a third step of etching the semiconductor substrate using the insulating film as a mask to form a trench; a fourth step of depositing an insulating film in the trench to a depth shallower than the depth of the trench; and a fourth step of depositing the insulating film as a mask. A fifth step of forming a diffusion layer having a concentration different from that of the substrate on a part of the upper part of the side wall of the substrate by ion implantation at an angle of 7° or more.
A method for manufacturing an IS type semiconductor device. (5) A first step of selectively forming an insulating film on a semiconductor substrate of one conductivity type, and using the insulating film as a mask,
a second etching step of etching the semiconductor substrate to form a groove that will become a groove-type insulating separation layer; a third implantation step of forming a diffusion layer having a concentration different from that of the substrate at the bottom of the groove; A fourth step is to deposit an insulating film in the trench to a depth shallower than the depth of the trench, and by using the insulating film as a mask and ion implantation at an angle of 7° or more, a diffusion layer having a concentration different from that of the substrate is deposited on the upper side wall of the substrate. A method for manufacturing an MIS type semiconductor device, comprising a fifth step of forming a part of the MIS type semiconductor device.