JP2025512235A - 選択的金属堆積のための選択的阻害 - Google Patents

選択的金属堆積のための選択的阻害 Download PDF

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Publication number
JP2025512235A
JP2025512235A JP2024549153A JP2024549153A JP2025512235A JP 2025512235 A JP2025512235 A JP 2025512235A JP 2024549153 A JP2024549153 A JP 2024549153A JP 2024549153 A JP2024549153 A JP 2024549153A JP 2025512235 A JP2025512235 A JP 2025512235A
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JP
Japan
Prior art keywords
metal
substrate
smi
lmi
recess
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Pending
Application number
JP2024549153A
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English (en)
Japanese (ja)
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JP2025512235A5 (https=
Inventor
ユ，カイ－フン
クラーク，ロバート
亮太 米澤
寛明 新実
秀直 鈴木
タピリー，カンダバラ
孝広 宮原
ワイダ，コーリー
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Tokyo Electron US Holdings Inc
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Tokyo Electron US Holdings Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Tokyo Electron US Holdings Inc filed Critical Tokyo Electron US Holdings Inc
Publication of JP2025512235A publication Critical patent/JP2025512235A/ja
Publication of JP2025512235A5 publication Critical patent/JP2025512235A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4432—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2024549153A 2022-02-28 2023-02-27 選択的金属堆積のための選択的阻害 Pending JP2025512235A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202263315062P 2022-02-28 2022-02-28
US63/315,062 2022-02-28
US18/156,142 2023-01-18
US18/156,142 US12588435B2 (en) 2022-02-28 2023-01-18 Selective inhibition for selective metal deposition
PCT/US2023/063327 WO2023164685A1 (en) 2022-02-28 2023-02-27 Selective inhibition for selective metal deposition

Publications (2)

Publication Number Publication Date
JP2025512235A true JP2025512235A (ja) 2025-04-17
JP2025512235A5 JP2025512235A5 (https=) 2026-01-21

Family

ID=87761179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024549153A Pending JP2025512235A (ja) 2022-02-28 2023-02-27 選択的金属堆積のための選択的阻害

Country Status (5)

Country Link
US (1) US12588435B2 (https=)
JP (1) JP2025512235A (https=)
KR (1) KR20240157662A (https=)
TW (1) TW202348825A (https=)
WO (1) WO2023164685A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240431025A1 (en) * 2023-06-26 2024-12-26 International Business Machines Corporation Corrosion resistant single damascene interconnects
WO2025217071A1 (en) * 2024-04-08 2025-10-16 Lam Research Corporation Isonitrile inhibitors in ald

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8242019B2 (en) 2009-03-31 2012-08-14 Tokyo Electron Limited Selective deposition of metal-containing cap layers for semiconductor devices
SG11202009105YA (en) 2018-03-20 2020-10-29 Tokyo Electron Ltd Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same
KR102800886B1 (ko) 2018-08-23 2025-04-29 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치 및 방법
JP2020056104A (ja) 2018-10-02 2020-04-09 エーエスエム アイピー ホールディング ビー．ブイ． 選択的パッシベーションおよび選択的堆積
CN112805818B (zh) * 2018-10-10 2024-10-18 东京毅力科创株式会社 用低电阻率金属填充半导体器件中的凹陷特征的方法
US11282745B2 (en) 2019-04-28 2022-03-22 Applied Materials, Inc. Methods for filling features with ruthenium
US20200347493A1 (en) 2019-05-05 2020-11-05 Applied Materials, Inc. Reverse Selective Deposition
US11286556B2 (en) 2020-04-14 2022-03-29 Applied Materials, Inc. Selective deposition of titanium films
WO2021262527A1 (en) 2020-06-23 2021-12-30 Lam Research Corporation Selective deposition using graphene as an inhibitor
US11094543B1 (en) 2020-12-04 2021-08-17 Tokyo Electron Limited Defect correction on metal resists

Also Published As

Publication number Publication date
TW202348825A (zh) 2023-12-16
US12588435B2 (en) 2026-03-24
US20230274932A1 (en) 2023-08-31
KR20240157662A (ko) 2024-11-01
WO2023164685A1 (en) 2023-08-31

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