Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P70/00—Cleaning of wafers, substrates or parts of devices
  • H10P70/20—Cleaning during device manufacture
  • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6328—Deposition from the gas or vapour phase
  • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
  • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
  • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
  • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
  • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
  • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
  • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
  • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/44—Conductive materials thereof
  • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
  • H10W20/4432—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold

Definitions

• the present invention relates generally to methods of processing a substrate, and, in particular embodiments, to selective inhibition for selective metal deposition.
• a semiconductor device such as an integrated circuit (IC) is fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconductor materials over a substrate to form a network of electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated in a monolithic structure.
• interconnect elements e.g., transistors, resistors, capacitors, metal lines, contacts, and vias
• a method for processing a substrate includes treating the substrate with a small molecular inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer in the recess, the SMI covering a surface of the first metal layer.
• the method further includes, after treating the substrate with the SMI, treating the substrate with a large molecular inhibitor (LMI), the LMI covering sidewalls of the dielectric layer in the recess.
• the method further includes heating the substrate to remove the SMI from the first metal layer and to expose the first metal layer in the recess, where the LMI remains on the sidewalls after removing the SMI from the first metal layer.
• the method further includes depositing a second metal over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.
• a method for processing a substrate includes performing a cyclic chemical vapor deposition (CVD) process, the substrate including a dielectric layer having a recess and a first metal layer at a bottom of the recess.
• one cycle of the cyclic CVD process includes treating the substrate with a small molecular inhibitor (SMI), the SMI covering a surface of a second metal formed over the first metal layer, and treating the substrate with a large molecular inhibitor (LMI) after treating the substrate with the SMI, the LMI covering sidewalls of the dielectric layer in the recess.
• SI small molecular inhibitor
• LMI large molecular inhibitor
• one cycle of the cyclic CVD process includes heating the substrate to remove the SMI from over the second metal and to expose the second metal, where the LMI remains on the sidewalls, and depositing the second metal over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.
• a method for processing a substrate includes exposing the substrate to a first vapor including a small molecular inhibitor (SMI), the substrate including a dielectric surface and a first metal surface, the SMI adsorbing on the first metal surface selectively to the dielectric surface.
• SI small molecular inhibitor
• the method includes exposing the substrate to a second vapor including a large molecular inhibitor (LMI), the LMI selectively adsorbing on the dielectric surface, the adsorbed SMI preventing the LMI from adsorbing on the first metal surface.
• LMI large molecular inhibitor
• the method includes removing the SMI from the first metal surface without removing the LMI from the dielectric surface, and depositing a second metal over the first metal surface by chemical vapor deposition (CVD), where a deposition rate over the first metal surface is at least 100 times as high as a deposition rate over the dielectric surface.
• CVD chemical vapor deposition
• Figures 1 A-1B schematically illustrate an impurity interface issue caused by a conventional chemical vapor deposition (CVD) process for metal deposition, wherein Figure 1 A illustrates a cross sectional view of an example substrate during the conventional CVD process, and Figure IB illustrates a cross sectional view of the substrate after cycles of the conventional CVD process;
• CVD chemical vapor deposition
• Figures 2A-2H illustrate cross sectional views of a substrate at various stages of a metal deposition process in accordance with various embodiments, wherein Figure 2A illustrates an incoming substrate comprising a first metal layer and a dielectric layer with a recess feature, Figure 2B illustrates the substrate after a pretreatment to expose the first metal layer, Figure 2C illustrates the substrate after a selective treatment with a small molecular inhibitor (SMI), Figure 2D illustrates the substrate after a selective treatment with a large molecular inhibitor (LMI), Figure 2E illustrates the substrate after removing the SMI, Figure 2F illustrates the substrate after depositing a second metal, Figure 2G illustrates the substrate after a metal nuclei removal etch, and Figure 2H illustrates the substrate after cycles of the metal deposition process to fill the recess with the second metal;
• SMI small molecular inhibitor
• LMI large molecular inhibitor
• Figure 2E illustrates the substrate after removing the SMI
• Figure 2F illustrates the substrate after depositing a second
• Figures 3 A-3D schematically illustrate step-wise area- selective surface modification of the metal deposition process in accordance with one embodiment, wherein Figure 3 A illustrates selective adsorption of the small molecular inhibitor (SMI) onto a metal, Figure 3B illustrates selective adsorption of the large molecular inhibitor (LMI) onto silicon oxide, Figure 3C illustrates selective removal of the SMI by a FL treatment, and Figure 3D illustrates selective metal deposition onto the metal; and
• SMI small molecular inhibitor
• LMI large molecular inhibitor
• Figures 4A-4C illustrate process flow diagrams of the methods of metal deposition process in accordance with various embodiments, wherein Figure 4A illustrates an embodiment, Figure 4B illustrates another embodiment, and Figure 4C illustrates yet another embodiment.
• This application relates to methods of processing a substrate, more particularly to selective metal deposition using two types of molecular inhibitors.
• conductive materials are used in semiconductor devices to enable electrical connections between various components.
• copper (Cu) has been used for interconnects in integrated circuits (ICs) for decades
• new conductive materials with lower electrical resistivity e.g., Ru, Mo, Co, and W
• MOL sub- 10 nm node middle of line
• BEOL back end of line
• some of these new conductive materials, unlike Cu may not require a diffusion barrier layer, which advantageously simplifies the fabrication process.
• HAR high-aspect ratio
• a molecular inhibitor during a deposition process, which may preferentially deposit metal on a metal surface compared to the inhibitor-covered surface of, for example, a dielectric.
• the inhibitor may also adsorb on the metal surface to cause impurity issues and decrease the metal deposition rate. Therefore, a new method for selective metal deposition may be desired.
• Embodiments of the present application disclose methods of selective metal deposition with two different molecular inhibitors: one for a metal surface and the other for a dielectric surface.
• the metal surface may first be treated and passivated with a first molecular inhibitor (e.g., a small molecular inhibitor, SMI).
• the dielectric surface may then be treated and passivated with a second molecular inhibitor (e.g., a large molecular inhibitor, LMI), where the presence of the SMI may prevent the undesired LMI adsorption on the metal surface.
• a first molecular inhibitor e.g., a small molecular inhibitor, SMI
• a second molecular inhibitor e.g., a large molecular inhibitor, LMI
• the SMI may then be removed from the metal surface such that a subsequent metal deposition process (e.g., CVD) may occur preferentially on the exposed metal surface while the LMI prevents metal deposition on the dielectric.
• a subsequent metal deposition process e.g., CVD
• the methods may be applied as a cyclic process to fill a high-aspect ratio (HAR) recess.
• the methods described in this disclosure may advantageously improve the selectivity of various metal deposition methods.
• the methods of metal deposition may overcome the impurity issue at metal-metal interfaces.
• the methods may particularly be advantageous for fabrication processes for sub- 10 nm node middle of line (MOL) and back end of line (BEOL) logic interconnects, and may also enable using new metal materials such as Ru, Mo, Co, and W for these applications.
• MOL node middle of line
• BEOL back end of line
• new metal materials such as Ru, Mo, Co, and W for these applications.
• various embodiments of the methods are primarily described as CVD in this disclosure, the use of two molecular inhibitors may also be applied in other methods such as atomic layer deposition (ALD) and wet processes.
• ALD atomic layer deposition
• FIGS 1 A-1B schematically illustrate an impurity interface issue caused by a conventional chemical vapor deposition (CVD) process for metal deposition.
• CVD chemical vapor deposition
• FIG. 1 A a cross sectional view of an example substrate with a recess during the conventional CVD process using a molecular inhibitor is illustrated, where the conventional CVD process selectively deposits a second metal 104 over a first metal 102 to fill the recess.
• the molecular inhibitor may prevent the metal deposition on sidewalls, it may also form an impurity layer 106 (e.g., Si-containing) at an interface between the first metal 102 and the second metal 104.
• the impurity layer 106 may be formed at each metal -metal interface.
• the impurity layer 106 is often detrimental to the quality of the metal interconnects, and furthermore, it may also decrease the metal deposition rate during the CVD process.
• the inventors of this application identified that this impurity issue is caused by the undesired passivation of the metal surface by the molecular inhibitor.
• the methods of metal deposition described in this disclosure may advantageously solve this impurity issue by pre-passivating the metal surface with another molecular inhibitor that can be readily moved in a subsequent step.
• Figures 2A-2H illustrate cross sectional views of a substrate 100 at various stages of a metal deposition process in accordance with various embodiments.
• the selective surface modification of the metal deposition process is further schematically illustrated in Figures 3 A-3D, which will be described along with Figures 2C-2F, respectively.
• Figure 2A illustrates a cross-sectional view of an incoming substrate 100.
• the substrate 100 may be a part of, or includes, a semiconductor device, and may have undergone a number of steps of processing following, for example, a conventional process.
• the substrate 100 accordingly may comprise layers of semiconductors useful in various microelectronics.
• the semiconductor structure may comprise the substrate 100 in which various device regions are formed.
• the substrate 100 may be a silicon wafer, or a silicon-on-insulator (SOI) wafer.
• the substrate 100 may comprise a silicon germanium wafer, silicon carbide wafer, gallium arsenide wafer, gallium nitride wafer and other compound semiconductors.
• the substrate 100 comprises heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, as well layers of silicon on a silicon or SOI substrate.
• the substrate 100 is patterned or embedded in other components of the semiconductor device.
• the substrate 100 may comprise a recess 115 formed in a dielectric layer 110.
• the substrate 100 may further comprise an etch stop layer (ESL) 120 as a bottom layer of the dielectric layer 110, and a first metal layer 130 at the bottom of the recess 115.
• ESL etch stop layer
• a surface oxide layer 135 may be present on the surface of the first metal layer 130.
• the dielectric layer 110 may silicon oxide, a low dielectric constant (low-k) material such as fluorinated silicon glass (FSG), carbon doped oxide, a polymer, a SiCOH-containing low-k material, a non-porous low-k material, a porous low-k material, a CVD low-k material, a spin-on dielectric (SOD) low-k material, or any other suitable dielectric material, including a high dielectric constant (high-k) material.
• a critical dimension (CD) of the recess 115 may be between about 10 nm and about 65 nm for via dominant structure, or between about 10 nm and about 100 nm for trench dominant in another embodiment.
• the depth of the recess 115 may be between about 40 nm and about 80 nm for single damascene structure, or between about 80 nm and about 150 nm for dual damascene structure. In various embodiments, the recess 115 may have an aspect ratio between about 4 and about 8 for single damascene, or between about 6 and about 10 for dual damascene.
• the first metal layer 130 may comprise a low-resistivity metal such as copper (Cu), ruthenium (Ru), cobalt (Co), molybdenum (Mo) or tungsten (W).
• a low-resistivity metal such as copper (Cu), ruthenium (Ru), cobalt (Co), molybdenum (Mo) or tungsten (W).
• the first metal layer 130 may comprise two or more stacked conductive layers. Examples of the stacked conductive layers include Co metal on Cu metal (Co/Cu) and Ru metal on Cu metal (Ru/Cu).
• the ESL 120 may comprise a dielectric such as silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride.
• the ESL 120 may be deposited using deposition techniques such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes such as plasma enhanced CVD (PECVD), sputtering, and other processes.
• the thickness of the ESL 120 may be between 2 nm to 5 nm.
• Figure 2B illustrates a cross sectional view of the substrate 100 after a pretreatment to expose the first metal layer 130.
• the pretreatment may be performed to remove the surface oxide layer 135 and to expose the first metal layer 130.
• the pretreatment may comprise treating the surface oxide layer 135, for example, with a plasma comprising dihydrogen (EE).
• EE dihydrogen
• the pretreatment may be skipped if the substrate 100 is already free from any surface oxide.
• FIG. 2C illustrates a cross sectional view of the substrate after a selective treatment with a small molecular inhibitor (SMI).
• SI small molecular inhibitor
• Figure 3 A illustrates selective adsorption of the SMI onto a metal in accordance with one embodiment.
• the substrate 100 may be treated with a small molecular inhibitor (SMI) to selectively cover the exposed surface of the first metal layer 130, resulting in a passivated first metal surface 140.
• SMI small molecular inhibitor
• the SMI may only adsorb on a metal selectively to a dielectric surface such as silicon oxide.
• a subsequent step with another molecular inhibitor may advantageously adsorb selectively on the dielectric layer 110.
• the SMI may be vaporized and delivered to the substrate 100 as a vapor diluted in a carrier gas (e.g., N2), where the substrate temperature about room temperature may be maintained.
• a carrier gas e.g., N2
• this exposure with the SMI may be performed for 1-120 s with heated stage or temperature-elevated techniques.
• the SMI may comprise a nitrogen-containing compound, and in certain embodiments, the nitrogen-containing compound comprises NH3, N2H4, or an aromatic compound.
• nitrogenous aromatic SMI include pyridine, pyrimidine, pyrazine, pyrrole, imidazole, pyrazole, aniline, and benzotriazole (BTA).
• the SMI may comprise R-PO3H, R-COOH, R-SH, or R-SOx.
• any suitable molecular inhibitor may be used, where it satisfies the following criteria: the SMI adsorbs on a metal layer (e.g., the first metal layer 130) selectively to other layers (e.g., the dielectric layer 110); and the metal layer may be regenerated by a later removal step for the SMI.
• the SMI may be oxygen-free to prevent any chance of oxygen interacting with the metal and cause impurity issues.
• FIG. 2D illustrates the substrate 100 after a selective treatment with a large molecular inhibitor (LMI).
• LMI large molecular inhibitor
• Figure 3B illustrates selective adsorption of the LMI onto a silicon oxide surface.
• the substrate 100 may be treated with a large molecular inhibitor (LMI).
• LMI large molecular inhibitor
• the LMI may selectively cover the exposed surface of the dielectric layer 110, both sidewalls and a top horizontal surface, resulting in a passivated dielectric surface 150.
• the presence of the SMI can prevent the undesired LMI adsorption on the first metal layer 130.
• Figure 3B where the LMI adsorbs only on the silicon oxide surface.
• the treatment with the LIM may make the surface of the dielectric layer 110 more hydrophobic, which may be beneficial in reducing deposition of a metal precursor during a metal deposition step.
• the LMI may be vaporized and delivered to the substrate 100 as a vapor diluted in a carrier gas (e.g., N2).
• a carrier gas e.g., N2
• the treatment may be performed with a substrate temperature between about 80°C and about 250°C, and a process chamber pressure of about 1-10 Torr, and a 1-120 s exposure time with no plasma excitation.
• the LMI comprises an alkyl silane, an alkoxysilane, an alkyl alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an alkyl alkoxysiloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA), bis(dimethylamino) dimethylsilane (BDMADMS), N,0 bistrimethylsilyltrifluoroacetamide (BSTFA), or trimethylsilyl-pyrrole (TMS-pyrrole).
• DMSDMA dimethylsilane dimethylamine
• TMSDMA trimethylsilane dimethylamine
• BDMADMS bis(dimethylamino) dimethylsilane
• BSTFA N,0 bistrimethylsilyltrifluoroacet
• the first molecular inhibitor used for passivating the metal surface is referred to as small molecular inhibitor (SMI) and the second molecular inhibitor used for passivating the dielectric surface (e.g., Figures 2D and 3B) is referred to as large molecular inhibitor (LMI) because of their relative molecular size in general.
• a LMI may have a greater molecular weight than a SMI.
• a LMI may have a greater molecular volume or surface area than a SMI.
• molecular inhibitors with any molecular size may be used.
• Figure 2E illustrates a cross sectional view of the substrate 100 after removing the SMI.
• Figure 3C illustrates selective removal of the SMI by a H2 treatment.
• a SMI removal step may be performed.
• the SMI removal step may be an annealing process at a temperature below 400°C under an inert gas flow or a reductive environment (e.g., H2).
• the reductive environment for the annealing process may advantageously minimize undesired reaction of the metal in the first metal layer 130 such as nitridation and oxidation.
• the annealing temperature may be between 250°C and 400°C such that the annealing process may not exceed the thermal budget for the target semiconductor device fabrication.
• the annealing process may selectively remove the SMI from the metal surface (e.g., the first metal layer 130) while retaining the LMI on the dielectric surface (e.g., the dielectric layer 110). With this selective SMI removal, the metal surface is recovered and accessible for the subsequent metal deposition step.
• Figure 2F illustrates a cross sectional view of the substrate 100 after depositing a second metal 160.
• Figure 3D illustrates selective metal deposition onto the metal.
• the metal deposition step may be performed using chemical vapor deposition (CVD), but in other embodiment, other techniques including wet process may be used.
• the second metal 160 may comprise a low-resistivity metal such as Cu, Ru, Co, or W.
• the second metal 160 may or may not be the same material used for the first metal layer 130.
• more than one metal may be deposited to form an alloy or stacked conductive layers. Because the sidewalls and top surface of the dielectric layer 110 is still passivated with the LMI, the second metal 160 may be selectively deposited over the first metal layer 130 and grow bottom-up.
• Ru metal may be deposited by chemical vapor phase deposition (CVD) or atomic layer deposition (ALD) using Ru-containing precursors.
• Ru-containing precursors include Ru3(CO)i2, (2,4-dimethylpentadienyl) (ethylcyclopentadienyl) ruthenium (Ru(DMPD)(EtCp)), bis(2,4-dimethylpentadienyl) ruthenium (Ru(DMPD)2), 4-dimethylpentadienyl) (methylcyclopentadienyl) ruthenium (Ru(DMPD)(MeCp)), and bis(ethylcyclopentadienyl) ruthenium (Ru(EtCp)2), as well as combinations of these and other precursors.
• the process condition for a Ru metal CVD process may include a process gas containing Ru3(CO)i2 and CO (e.g., a gas flow ratio of about 1 : 100), a substrate temperature between about 100°C and about 250°C, a process chamber pressure between about 1 mTorr and about 500 mTorr, and a 400 s exposure without plasma excitation that deposits between about 10 nm and 20 nm of Ru metal on the metal surface.
• a process gas containing Ru3(CO)i2 and CO e.g., a gas flow ratio of about 1 : 100
• a substrate temperature between about 100°C and about 250°C
• a process chamber pressure between about 1 mTorr and about 500 mTorr
• a 400 s exposure without plasma excitation that deposits between about 10 nm and 20 nm of Ru metal on the metal surface.
• the metal deposition step may fill a portion of the recess 115, for example, about a fourth of the initial depth of the recess 115.
• the recess 115 may be completely filled with one metal deposition step.
• the metal deposition step may be terminated at a certain height to avoid excessive formation of metal nuclei 165 over the dielectric layer 110. These metal nuclei 165 may be formed due to adsorption of the metal precursor on the LMI or imperfect passivation of the dielectric layer 110 by the LMI.
• the metal nuclei 165 over the dielectric layer 110, especially over the sidewalls, may lead to lateral growth of the second metal 160, potentially creating voids in the second metal 160 and causing pinch-off issues.
• the metal deposition step may be performed as a cyclic process including a metal nuclei removal etch as described below ( Figure 2G), and the recess 115 may be filled with the cycles of the metal deposition process.
• Figure 2G illustrates a cross sectional view of the substrate 100 after a metal nuclei removal etch.
• the metal nuclei removal etch may be performed to clean the sidewalls and top surface of the dielectric layer 110. It may be preferable to remove the metal nuclei 165 before they become too large and more difficult to remove efficiently. As illustrated in Figure 2G, after the metal nuclei removal etch, the LIM may also be removed from the dielectric layer 110. In certain embodiments, the metal nuclei removal etch may be performed using reactive ion etching (RIE), for example using plasma-excited O2 gas and optionally adding a halogencontaining gas (e.g., Ch).
• RIE reactive ion etching
• the process conditions for the O2-CI2 RIE for the metal nuclei removal etch may include an etching comprising O2 and Ch (e.g., a gas flow ratio of about 100: 1), a substrate temperature between about room temperature and about 370°C, plasma excitation using a capacitively coupled plasma (CCP) source with about 1200 W of RF power applied to a top electrode and between about 0 W and about 300 W of RF power applied to a bottom electrode, a process chamber pressure of about 5 mTorr, and a 40 s exposure time to remove the equivalent of about 5 nm of metal nuclei.
• the metal nuclei removal etch may be performed using chemical vaper etching (CVE).
• a treatment with ozone (O3) gas may also be used for the metal nuclei removal etch.
• the ozone for the ozone treatment may be generated from dioxygen (O2) gas with UV excitation with an example process conditions as follows: process temperature between about 50°C and 200°C; pressure range between about 500 mT to 10 Torr diluted with Ar gas; ozone exposure duration between 1 s to 60 s; and ozone density between 100 g/m 3 and 300 g/m 3 .
• the ozone treatment can be applied onto BEOL metallization without causing damage on low-k dielectric and may be advantageous over a O2-plasma-based RIE.
• the metal deposition ( Figure 2F) may be achieved without any metal nuclei (e.g., the metal nuclei 165 in Figure 2F) over the sidewall of the dielectric layer 110, and in these cases, the metal nuclei removal etch may be skipped.
• the LMI may not completely stop metal deposition over the dielectric layer 110, while it may substantially slow the deposition rate.
• the deposition rate over the first metal layer 130 may be at least 100 times as high as the deposition rate over the dielectric layer 110.
• Figure 2H illustrates a cross sectional view of the substrate 100 after cycles of the metal deposition process to fill the recess 115 with the second metal 160.
• the methods of selective metal deposition process may be performed as a cyclic process by repeating the steps of selective SMI treatment (e.g., Figures 2C and 3A), selective LMI treatment (e.g., Figures 2D and 3B), selective SMI removal (e.g., Figures 2E and 3C), metal deposition (e.g., Figures 2F and 3D), and metal nuclei removal etch (e.g., Figure 2G).
• Each cycle of the selective metal deposition process may fill a portion of the recess 115 with the second metal 160, and may be repeated until the recess 115 is completely filled.
• the filled recess may be free from impurity unlike the case with the conventional method illustrated in Figures 1 A and IB.
• the impurity level (e.g., Si) in the filled recess may be below a detection limit (e.g., ⁇ 0.1 atom %)) of a common technique such as elemental analysis or X-ray photoelectron spectroscopy (XPS).
• the filled recess may be void-free.
• the recess 115 may be completely filled by four cycles of the selective metal deposition process, but in other embodiments, any number of cycles may be performed.
• process conditions for the steps of the selective metal deposition process may be adjusted for each cycle in view of the aspect ratio of the remaining recess.
• the exposure time for the metal deposition for the first cycle may be shorter than those for the subsequent cycles because the metal nuclei formation over the sidewalls may be more likely to occur due to higher surface area.
• the cycles of the selective metal deposition process may use more than one deposition technique since the use of two molecular inhibitors in the methods is not limited to any particular deposition technique.
• each step of selective metal deposition process (e.g., Figures 2A-2H) may be performed within the thermal budget for the target semiconductor device fabrication, for example, below 400°C.
• FIGS 4A-4C illustrate process flow diagrams of the methods of metal deposition process in accordance with various embodiments. The process flow can be followed with the figures ( Figures 2C-2G) discussed above and hence will not be described again.
• a process flow 40 starts with treating a substrate with a small molecular inhibitor (SMI), where the substrate comprises a recess formed in a dielectric layer and a first metal layer in the recess (block 410, Figure 2C).
• the surface of the first metal layer may be selectively covered with the SMI.
• the substrate may then be treated with a large molecular inhibitor (LMI) to cover sidewalls of the dielectric layer in the recess (block 420, Figure 2D).
• LMI large molecular inhibitor
• the substrate may be heated to remove the SMI from the first metal layer and to expose the first metal layer in the recess, while the LMI remains on the sidewalls (block 430, Figure 2E).
• a second metal may then be selectively deposited over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer (block 440, Figure 2F).
• a cyclic chemical vapor deposition (CVD) process 42 starts with treating a substrate with a SMI to cover a surface of a metal (e.g., a first metal layer in a first cycle of the cyclic CVD process and a surface of a second metal in subsequent cycles) (block 412, Figure 2C).
• the substrate may comprise a dielectric layer having a recess and the first metal layer exposed at a bottom of the recess.
• the substrate may then be treated with a LMI to cover sidewalls of the dielectric layer in the recess (block 422, Figure 2D).
• the substrate may be heated to remove the SMI from the first metal layer and to expose the first metal layer in the recess, where the LMI remains on the sidewalls (block 432, Figure 2E).
• a second metal may then be selectively deposited over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer (block 442, Figure 2F).
• an additional etch may be inserted in one or more of the cycles of the cyclic CVD process to remove the second metal nuclei from the portion of the sidewalls (block 452, Figure 2G).
• FIG. 4C another process flow 44 starts with exposing a substrate to a first vapor comprising a SMI, where the substrate comprises a recess formed in a dielectric layer and a first metal layer in the recess (block 414, Figure 2C).
• the SMI adsorbs on the first metal layer selectively to sidewalls of the dielectric layer in the recess.
• the substrate may then be exposed to a second vapor comprising a LMI (block 424, Figure 2D), where the LMI selectively adsorbs on the sidewalls and the adsorbed SMI preventing the LMI from adsorbing on the first metal layer.
• the SMI may be removed from the first metal layer without removing the LMI from the sidewalls (block 434, Figure 2E).
• a second metal may then be selectively deposited over the first metal layer in the recess by CVD, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer (block 444, Figure 2F).
• the selective metal deposition using two types of molecular inhibitors in various embodiments may advantageously eliminate or minimize the impurity issues from inhibitor contamination.
• the methods are particularly useful for vapor metal deposition to fill a high- aspect ratio (HAR) recess for applications such as sub- 10 nm node middle of line (MOL) and back end of line (BEOL) logic interconnects, where the impurity, even at a very low level, hampers the conductivity and thereby device performance.
• HAR aspect ratio
• MOL sub- 10 nm node middle of line
• BEOL back end of line
• the methods may also be applied to atomic layer deposition (ALD) or other deposition techniques.
• the methods may be used to deposit metal compounds (e.g., metal oxide and metal nitride), where the step of selective metal deposition may be followed by an additional treatment to convert the deposited metal into the metal compounds.
• a method for processing a substrate includes treating the substrate with a small molecular inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer in the recess, the SMI covering a surface of the first metal layer.
• the method further includes, after treating the substrate with the SMI, treating the substrate with a large molecular inhibitor (LMI), the LMI covering sidewalls of the dielectric layer in the recess.
• the method further includes heating the substrate to remove the SMI from the first metal layer and to expose the first metal layer in the recess, where the LMI remains on the sidewalls after removing the SMI from the first metal layer.
• the method further includes depositing a second metal over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.
• Example 2 The method of example 1, where the substrate further includes a surface oxide layer over the first metal layer, and where the method further includes, prior to treating the substrate with the SMI, removing the surface oxide layer to expose the first metal layer in the recess.
• Example 3 The method of one of examples 1 or 2, where depositing the second metal deposits second metal nuclei on a portion of the sidewalls, further including removing the second metal nuclei.
• Example 4 The method of one of examples 1 to 3, where depositing the second metal is achieved bottom-up from the first metal layer without the second metal growing from the dielectric layer.
• Example 5 The method of one of examples 1 to 4, where heating the substrate includes heating the substrate to a temperature between 250°C and 400°C.
• Example 6 The method of one of examples 1 to 5, where heating the substrate including exposing the substrate to a gas including dihydrogen (H2).
• Example 7 The method of one of examples 1 to 6, where the SMI includes a nitrogen-containing compound.
• Example 8 The method of one of examples 1 to 7, where the nitrogen-containing compound includes NEE, N2H4, or an aromatic compound.
• Example 9 The method of one of examples 1 to 8, where the SMI includes R- PO3H, R-COOH, R-SH, or R-SOx.
• Example 10 The method of one of examples 1 to 9, where the LMI includes an alkyl silane, an alkoxysilane, an alkyl alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an alkyl alkoxysiloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, dimethyl silane dimethylamine (DMSDMA), trimethyl silane dimethylamine (TMSDMA), bis(dimethylamino) dimethylsilane (BDMADMS), N,0 bistrimethylsilyltrifluoroacetamide (BSTFA), or trimethylsilyl-pyrrole (TMS-pyrrole).
• Example 11 The method of one of examples 1 to 10, where the first metal layer includes Ru, Co, or W, and where the second metal includes Cu, Ru, Co, or W.
• a method for processing a substrate includes performing a cyclic chemical vapor deposition (CVD) process, the substrate including a dielectric layer having a recess and a first metal layer at a bottom of the recess.
• one cycle of the cyclic CVD process includes treating the substrate with a small molecular inhibitor (SMI), the SMI covering a surface of a second metal formed over the first metal layer, and treating the substrate with a large molecular inhibitor (LMI) after treating the substrate with the SMI, the LMI covering sidewalls of the dielectric layer in the recess.
• SI small molecular inhibitor
• LMI large molecular inhibitor
• one cycle of the cyclic CVD process includes heating the substrate to remove the SMI from over the second metal and to expose the second metal, where the LMI remains on the sidewalls, and depositing the second metal over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.
• Example 13 The method of example 12, where depositing the second metal deposits second metal nuclei on a portion of the sidewalls, and where one of the cyclic CVD process further includes removing the second metal nuclei from the portion of the sidewalls.
• Example 14 The method of one of examples 12 or 13, where the cyclic CVD process fills the recess without forming any void.
• Example 15 The method of one of examples 12 to 14, where the LMI includes a silane, and the second metal that fills the recess is without any detectable silicon or silane impurity.
• a method for processing a substrate includes exposing the substrate to a first vapor including a small molecular inhibitor (SMI), the substrate including a dielectric surface and a first metal surface, the SMI adsorbing on the first metal surface selectively to the dielectric surface.
• the method includes exposing the substrate to a second vapor including a large molecular inhibitor (LMI), the LMI selectively adsorbing on the dielectric surface, the adsorbed SMI preventing the LMI from adsorbing on the first metal surface.
• SMI small molecular inhibitor
• LMI large molecular inhibitor
• the method includes removing the SMI from the first metal surface without removing the LMI from the dielectric surface, and depositing a second metal over the first metal surface by chemical vapor deposition (CVD), where a deposition rate over the first metal surface is at least 100 times as high as a deposition rate over the dielectric surface.
• CVD chemical vapor deposition
• Example 17 The method of example 16, where the removing includes treating the substrate with a gas including dihydrogen (H2) at a substrate temperature between 250°C and 400°C.
• H2 dihydrogen
• Example 18 The method of one of examples 16 or 17, where the first metal layer includes Ru, Co, Mo, or W, and where the second metal includes Cu, Ru, Co, Mo, or W.
• Example 19 The method of one of examples 16 to 18, where the SMI is silicon- free and the LMI includes silicon.
• Example 20 The method of one of examples 16 to 19, where the substrate includes a recess, the recess includes the dielectric surface as sidewalls and the first metal surface as a bottom surface, the recess having a critical dimension (CD) between 10 nm and 650 nm.
• CD critical dimension

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