JP2025501951A5 - - Google Patents
Info
- Publication number
- JP2025501951A5 JP2025501951A5 JP2024539495A JP2024539495A JP2025501951A5 JP 2025501951 A5 JP2025501951 A5 JP 2025501951A5 JP 2024539495 A JP2024539495 A JP 2024539495A JP 2024539495 A JP2024539495 A JP 2024539495A JP 2025501951 A5 JP2025501951 A5 JP 2025501951A5
- Authority
- JP
- Japan
- Prior art keywords
- thickness
- level
- conductive trace
- electronic device
- package substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/563,403 | 2021-12-28 | ||
| US17/563,403 US12266597B2 (en) | 2021-12-28 | 2021-12-28 | Multilevel package substrate with stair shaped substrate traces |
| PCT/US2022/054139 WO2023129582A1 (en) | 2021-12-28 | 2022-12-28 | Multilevel package substrate with stair shaped substrate traces |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025501951A JP2025501951A (ja) | 2025-01-24 |
| JP2025501951A5 true JP2025501951A5 (enExample) | 2026-01-09 |
Family
ID=86897129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024539495A Pending JP2025501951A (ja) | 2021-12-28 | 2022-12-28 | 段形状の基板トレースを備えるマルチレベルパッケージ基板 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US12266597B2 (enExample) |
| JP (1) | JP2025501951A (enExample) |
| CN (1) | CN118302856A (enExample) |
| WO (1) | WO2023129582A1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12702007B2 (en) * | 2023-06-29 | 2026-08-04 | Texas Instruments Incorporated | Multilevel package substrate for interlevel dielectric crack mitigation |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011138869A (ja) | 2009-12-28 | 2011-07-14 | Ngk Spark Plug Co Ltd | 多層配線基板の製造方法及び多層配線基板 |
| TWI528517B (zh) * | 2013-03-26 | 2016-04-01 | 威盛電子股份有限公司 | 線路基板、半導體封裝結構及線路基板製程 |
| JP6162458B2 (ja) | 2013-04-05 | 2017-07-12 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
| US10867924B2 (en) | 2017-07-06 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing |
| US11769719B2 (en) * | 2018-06-25 | 2023-09-26 | Intel Corporation | Dual trace thickness for single layer routing |
| TWI738069B (zh) | 2019-09-27 | 2021-09-01 | 恆勁科技股份有限公司 | 覆晶封裝基板及其製法 |
-
2021
- 2021-12-28 US US17/563,403 patent/US12266597B2/en active Active
-
2022
- 2022-12-28 CN CN202280077803.XA patent/CN118302856A/zh active Pending
- 2022-12-28 WO PCT/US2022/054139 patent/WO2023129582A1/en not_active Ceased
- 2022-12-28 JP JP2024539495A patent/JP2025501951A/ja active Pending
-
2025
- 2025-03-04 US US19/069,984 patent/US20250201689A1/en active Pending
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