CN110868797A - 电路板及其制造方法、半导体元件模板 - Google Patents
电路板及其制造方法、半导体元件模板 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000009713 electroplating Methods 0.000 claims abstract description 8
- 238000005553 drilling Methods 0.000 claims abstract description 6
- 230000007797 corrosion Effects 0.000 claims abstract description 4
- 238000005260 corrosion Methods 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000012545 processing Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 239000000126 substance Substances 0.000 claims abstract description 3
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000011161 development Methods 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
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Abstract
本发明公开了一种电路板及其制造方法,以及应用该电路板的半导体元件模板。电路板的制作方法,包括以下步骤:a)提供一多层板,该多层板包括有从上至下设置的导电层、绝缘层以及线路层;b)采用激光钻孔的工艺在导电层、绝缘层形成通孔,该通孔上下贯穿导电层、绝缘层;c)对多层板进行电镀,通孔内沉积出导电柱,导电柱与线路层导电连接;d)采用机械打磨或/与化学腐蚀的工艺对导电层、导电柱进行处理,去除导电层并露出绝缘层的表面,使导电柱的顶面不高于绝缘层的表面。本发明中,通过激光钻孔的方式得到通孔,通孔内通过电镀沉积出导电柱,使得导电柱的直径尺寸精度达到±3um,位置精度达到±10um,满足半导体元件技术发展的应用趋势。
Description
技术领域
本发明涉及半导体元件技术领域,特别是指一种电路板及其制造方法,以及应用该电路板的半导体元件模板。
背景技术
如图1所示,现有技术中的半导体元件模板,半导体元件模板包括有电路板(PCB)和多个半导体元件40,电路板表面有焊盘60,半导体元件40底部的焊脚41通过导电结合层50与焊盘60焊接,使得半导体元件贴合于电路板上。
电路板加工的典型工艺采用“图形电镀法”。即先在钻有通孔的基板进行电镀,在基板表面和通孔内壁同时形成一铜层,并获得金属化孔,然后在焊盘的图形部分上预镀一层抗蚀层,最后用化学方式将其余的底铜腐蚀掉,留下焊盘,得到电路板。
由“图形电镀法”得到的电路板,其焊盘的直径尺寸精度只能达到±25um,位置精度只能达到±30um。随着半导体元件技术的不断发展,半导体元件的尺寸越来越小,其安装精度要求也越来越高,由“图形电镀法”得到的电路板其焊盘的直径尺寸精度、位置精度均无法小半导体元件的安装精度要求。
发明内容
本发明要解决的技术问题是根据上述现有技术的不足,提出一种电路板及其制造方法,以及应用该电路板的半导体元件模板,解决了现有半导体元件模板中焊盘直径尺寸精度、位置精度不够的技术问题。
本发明的技术方案是这样实现的:
电路板的制作方法,包括以下步骤:
a)提供一多层板,该多层板包括有从上至下设置的导电层、绝缘层以及线路层;
b)采用激光钻孔的工艺在导电层、绝缘层形成通孔,该通孔上下贯穿导电层、绝缘层;
c)对多层板进行电镀,通孔内沉积出导电柱,导电柱与线路层导电连接;
d)采用机械打磨或/与化学腐蚀的工艺对导电层、导电柱进行处理,去除导电层并露出绝缘层的表面,使导电柱的顶面不高于绝缘层的表面。
由上述电路板的制作方法制得的电路板,包括有多层板,该多层板的顶层为绝缘层,该绝缘层底部设置有线路层;绝缘层设置有上下贯穿的通孔,该通孔内设置有导电柱,导电柱的顶面不高于绝缘层的表面,导电柱与线路层导电连接。
半导体元件模板,包括有半导体元件和上述电路板,半导体元件底部设置有焊脚,焊脚通过导电结合层与导电柱导电结合。
采用上述技术方案,本发明的有益效果在于:通过激光钻孔的方式得到通孔,通孔内通过电镀沉积出导电柱,使得导电柱的直径尺寸精度达到±3um,位置精度达到±10um,相比传统的焊盘结构,直径尺寸精度和位置精度均大大提高,满足半导体元件技术发展的应用趋势,比如适用于Micro LED技术和Mini LED技术中。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术中的LED显示灯板的剖面图。
图2为第一实施例中步骤b)后的剖面图。
图3为第一实施例中步骤c)后的剖面图。
图4为第一实施例中步骤d)后的剖面图及第二实施例的剖面图。
图5是第三实施例的剖面图。
图中,10-多层板,11-导电层,12-绝缘层,13-线路层,14-通孔,20-导电柱,40-半导体元件,41-焊脚,50-导电结合层,60-焊盘。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
如图2-4所示,在本发明提供的第一实施例,电路板的制作方法,包括以下步骤:
a)提供一多层板10,该多层板10包括有从上至下设置的导电层11、绝缘层12以及线路层13。需要说明的是,该描述为限定多层板10的外部层状结构,该顶部层状结构底下可以根据实际需求设置更多的绝缘层、线路层、导电层等其他结构。
b)如图2所示,采用激光钻孔的工艺在导电层11、绝缘层12形成通孔14,该通孔14上下贯穿导电层11、绝缘层12。
c)如图3所示,对多层板10进行电镀,通孔14内沉积出导电柱20,导电柱20与线路层13导电连接。其中,导电层表面也会沉积出导电物质,进而增加了导电层的厚度。
d)如图4所示,采用机械打磨或/与化学腐蚀的工艺对导电层11、导电柱20进行处理,去除导电层11并露出绝缘层12的表面,使导电柱20的顶面不高于绝缘层12的表面。
如图4所示,本发明提供的第二实施例,由第一实施例制得的电路板,包括有多层板10,该多层板10的顶层为绝缘层12,该绝缘层12底部设置有线路层13;绝缘层12设置有上下贯穿的通孔14,该通孔14内设置有导电柱20,导电柱20的顶面不高于绝缘层12的表面,导电柱20与线路层13导电连接。其中,本实施例中,导电柱20的顶面和绝缘层12的表面位于同一水平面上。
如图5所示,本发明提供的第三实施例,半导体元件模板,包括有半导体元件40和第二实施例所述电路板,半导体元件40底部设置有焊脚41,焊脚41通过导电结合层50与导电柱20导电结合。其中,半导体元件40可以为LED芯片、IC芯片等电子器件。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (3)
1.电路板的制作方法,其特征在于,包括以下步骤:
a)提供一多层板,该多层板包括有从上至下设置的导电层、绝缘层以及线路层;
b)采用激光钻孔的工艺在导电层、绝缘层形成通孔,该通孔上下贯穿导电层、绝缘层;
c)对多层板进行电镀,通孔内沉积出导电柱,导电柱与线路层导电连接;
d)采用机械打磨或/与化学腐蚀的工艺对导电层、导电柱进行处理,去除导电层并露出绝缘层的表面,使导电柱的顶面不高于绝缘层的表面。
2.由权利要求1所述电路板的制作方法制得的电路板,其特征在于:包括有多层板,该多层板的顶层为绝缘层,该绝缘层底部设置有线路层;绝缘层设置有上下贯穿的通孔,该通孔内设置有导电柱,导电柱的顶面不高于绝缘层的表面,导电柱与线路层导电连接。
3.半导体元件模板,其特征在于:包括有半导体元件和如权利要求2所述电路板,半导体元件底部设置有焊脚,焊脚通过导电结合层与导电柱导电结合。
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CN112420685A (zh) * | 2020-11-09 | 2021-02-26 | 东莞阿尔泰显示技术有限公司 | 一种led显示模块的制造方法 |
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CN112420685A (zh) * | 2020-11-09 | 2021-02-26 | 东莞阿尔泰显示技术有限公司 | 一种led显示模块的制造方法 |
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